2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 * Portions Copyright 2011 NVIDIA Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <asm/arch/clk_rst.h>
26 #include <asm/arch/clock.h>
27 #include "tegra2_mmc.h"
29 /* support 4 mmc hosts */
30 struct mmc mmc_dev[4];
31 struct mmc_host mmc_host[4];
35 * Get the host address and peripheral ID for a device. Devices are numbered
38 * @param host Structure to fill in (base, reg, mmc_id)
39 * @param dev_index Device index (0-3)
41 static void tegra2_get_setup(struct mmc_host *host, int dev_index)
43 debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
47 host->base = TEGRA2_SDMMC3_BASE;
48 host->mmc_id = PERIPH_ID_SDMMC3;
51 host->base = TEGRA2_SDMMC2_BASE;
52 host->mmc_id = PERIPH_ID_SDMMC2;
55 host->base = TEGRA2_SDMMC1_BASE;
56 host->mmc_id = PERIPH_ID_SDMMC1;
60 host->base = TEGRA2_SDMMC4_BASE;
61 host->mmc_id = PERIPH_ID_SDMMC4;
65 host->reg = (struct tegra2_mmc *)host->base;
68 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
72 debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
73 (u32)data->dest, data->blocks, data->blocksize);
75 writel((u32)data->dest, &host->reg->sysad);
80 * 10 = Selects 32-bit Address ADMA2
81 * 11 = Selects 64-bit Address ADMA2
83 ctrl = readb(&host->reg->hostctl);
84 ctrl &= ~(3 << 3); /* SDMA */
85 writeb(ctrl, &host->reg->hostctl);
87 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
88 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
89 writew(data->blocks, &host->reg->blkcnt);
92 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
95 debug(" mmc_set_transfer_mode called\n");
98 * MUL1SIN0[5] : Multi/Single Block Select
99 * RD1WT0[4] : Data Transfer Direction Select
102 * ENACMD12[2] : Auto CMD12 Enable
103 * ENBLKCNT[1] : Block Count Enable
104 * ENDMA[0] : DMA Enable
106 mode = (1 << 1) | (1 << 0);
107 if (data->blocks > 1)
109 if (data->flags & MMC_DATA_READ)
112 writew(mode, &host->reg->trnmod);
115 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
116 struct mmc_data *data)
118 struct mmc_host *host = (struct mmc_host *)mmc->priv;
120 unsigned int timeout;
122 unsigned int retry = 0x100000;
123 debug(" mmc_send_cmd called\n");
130 * CMDINHDAT[1] : Command Inhibit (DAT)
131 * CMDINHCMD[0] : Command Inhibit (CMD)
134 if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
138 * We shouldn't wait for data inhibit for stop commands, even
139 * though they might use busy signaling
144 while (readl(&host->reg->prnsts) & mask) {
146 printf("%s: timeout error\n", __func__);
154 mmc_prepare_data(host, data);
156 debug("cmd->arg: %08x\n", cmd->cmdarg);
157 writel(cmd->cmdarg, &host->reg->argument);
160 mmc_set_transfer_mode(host, data);
162 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
167 * CMDIDX[13:8] : Command index
168 * DATAPRNT[5] : Data Present Select
169 * ENCMDIDX[4] : Command Index Check Enable
170 * ENCMDCRC[3] : Command CRC Check Enable
175 * 11 = Length 48 Check busy after response
177 if (!(cmd->resp_type & MMC_RSP_PRESENT))
179 else if (cmd->resp_type & MMC_RSP_136)
181 else if (cmd->resp_type & MMC_RSP_BUSY)
186 if (cmd->resp_type & MMC_RSP_CRC)
188 if (cmd->resp_type & MMC_RSP_OPCODE)
193 debug("cmd: %d\n", cmd->cmdidx);
195 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
197 for (i = 0; i < retry; i++) {
198 mask = readl(&host->reg->norintsts);
199 /* Command Complete */
200 if (mask & (1 << 0)) {
202 writel(mask, &host->reg->norintsts);
208 printf("%s: waiting for status update\n", __func__);
212 if (mask & (1 << 16)) {
214 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
216 } else if (mask & (1 << 15)) {
217 /* Error Interrupt */
218 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
222 if (cmd->resp_type & MMC_RSP_PRESENT) {
223 if (cmd->resp_type & MMC_RSP_136) {
224 /* CRC is stripped so we need to do some shifting. */
225 for (i = 0; i < 4; i++) {
226 unsigned int offset =
227 (unsigned int)(&host->reg->rspreg3 - i);
228 cmd->response[i] = readl(offset) << 8;
234 debug("cmd->resp[%d]: %08x\n",
235 i, cmd->response[i]);
237 } else if (cmd->resp_type & MMC_RSP_BUSY) {
238 for (i = 0; i < retry; i++) {
239 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
240 if (readl(&host->reg->prnsts)
241 & (1 << 20)) /* DAT[0] */
246 printf("%s: card is still busy\n", __func__);
250 cmd->response[0] = readl(&host->reg->rspreg0);
251 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
253 cmd->response[0] = readl(&host->reg->rspreg0);
254 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
260 mask = readl(&host->reg->norintsts);
262 if (mask & (1 << 15)) {
263 /* Error Interrupt */
264 writel(mask, &host->reg->norintsts);
265 printf("%s: error during transfer: 0x%08x\n",
268 } else if (mask & (1 << 3)) {
272 } else if (mask & (1 << 1)) {
273 /* Transfer Complete */
274 debug("r/w is done\n");
278 writel(mask, &host->reg->norintsts);
285 static void mmc_change_clock(struct mmc_host *host, uint clock)
289 unsigned long timeout;
291 debug(" mmc_change_clock called\n");
294 * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
299 clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
301 debug("div = %d\n", div);
303 writew(0, &host->reg->clkcon);
307 * SELFREQ[15:8] : base clock divided by value
308 * ENSDCLK[2] : SD Clock Enable
309 * STBLINTCLK[1] : Internal Clock Stable
310 * ENINTCLK[0] : Internal Clock Enable
313 clk = (div << 8) | (1 << 0);
314 writew(clk, &host->reg->clkcon);
318 while (!(readw(&host->reg->clkcon) & (1 << 1))) {
320 printf("%s: timeout error\n", __func__);
328 writew(clk, &host->reg->clkcon);
330 debug("mmc_change_clock: clkcon = %08X\n", clk);
336 static void mmc_set_ios(struct mmc *mmc)
338 struct mmc_host *host = mmc->priv;
340 debug(" mmc_set_ios called\n");
342 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
344 /* Change clock first */
345 mmc_change_clock(host, mmc->clock);
347 ctrl = readb(&host->reg->hostctl);
351 * 0 = Depend on WIDE4
357 if (mmc->bus_width == 8)
359 else if (mmc->bus_width == 4)
364 writeb(ctrl, &host->reg->hostctl);
365 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
368 static void mmc_reset(struct mmc_host *host)
370 unsigned int timeout;
371 debug(" mmc_reset called\n");
374 * RSTALL[0] : Software reset for all
378 writeb((1 << 0), &host->reg->swrst);
382 /* Wait max 100 ms */
385 /* hw clears the bit when it's done */
386 while (readb(&host->reg->swrst) & (1 << 0)) {
388 printf("%s: timeout error\n", __func__);
396 static int mmc_core_init(struct mmc *mmc)
398 struct mmc_host *host = (struct mmc_host *)mmc->priv;
400 debug(" mmc_core_init called\n");
404 host->version = readw(&host->reg->hcver);
405 debug("host version = %x\n", host->version);
408 writel(0xffffffff, &host->reg->norintstsen);
409 writel(0xffffffff, &host->reg->norintsigen);
411 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
413 * NORMAL Interrupt Status Enable Register init
414 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
415 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
416 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
417 * [0] ENSTACMDCMPLT : Command Complete Status Enable
419 mask = readl(&host->reg->norintstsen);
421 mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
422 writel(mask, &host->reg->norintstsen);
425 * NORMAL Interrupt Signal Enable Register init
426 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
428 mask = readl(&host->reg->norintsigen);
431 writel(mask, &host->reg->norintsigen);
436 static int tegra2_mmc_initialize(int dev_index, int bus_width)
440 debug(" mmc_initialize called\n");
442 mmc = &mmc_dev[dev_index];
444 sprintf(mmc->name, "Tegra2 SD/MMC");
445 mmc->priv = &mmc_host[dev_index];
446 mmc->send_cmd = mmc_send_cmd;
447 mmc->set_ios = mmc_set_ios;
448 mmc->init = mmc_core_init;
450 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
452 mmc->host_caps = MMC_MODE_8BIT;
454 mmc->host_caps = MMC_MODE_4BIT;
455 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
458 * min freq is for card identification, and is the highest
459 * low-speed SDIO card frequency (actually 400KHz)
460 * max freq is highest HS eMMC clock as per the SD/MMC spec
462 * Both of these are the closest equivalents w/216MHz source
463 * clock and Tegra2 SDMMC divisors.
466 mmc->f_max = 48000000;
468 mmc_host[dev_index].clock = 0;
469 tegra2_get_setup(&mmc_host[dev_index], dev_index);
475 int tegra2_mmc_init(int dev_index, int bus_width)
477 debug(" tegra2_mmc_init: index %d, bus width %d\n",
478 dev_index, bus_width);
479 return tegra2_mmc_initialize(dev_index, bus_width);