2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 * Portions Copyright 2011 NVIDIA Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <asm/arch/clk_rst.h>
26 #include "tegra2_mmc.h"
28 /* support 4 mmc hosts */
29 struct mmc mmc_dev[4];
30 struct mmc_host mmc_host[4];
32 static inline struct tegra2_mmc *tegra2_get_base_mmc(int dev_index)
35 debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
39 offset = TEGRA2_SDMMC4_BASE;
42 offset = TEGRA2_SDMMC3_BASE;
45 offset = TEGRA2_SDMMC2_BASE;
48 offset = TEGRA2_SDMMC1_BASE;
51 offset = TEGRA2_SDMMC4_BASE;
55 return (struct tegra2_mmc *)(offset);
58 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
62 debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
63 (u32)data->dest, data->blocks, data->blocksize);
65 writel((u32)data->dest, &host->reg->sysad);
70 * 10 = Selects 32-bit Address ADMA2
71 * 11 = Selects 64-bit Address ADMA2
73 ctrl = readb(&host->reg->hostctl);
74 ctrl &= ~(3 << 3); /* SDMA */
75 writeb(ctrl, &host->reg->hostctl);
77 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
78 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
79 writew(data->blocks, &host->reg->blkcnt);
82 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
85 debug(" mmc_set_transfer_mode called\n");
88 * MUL1SIN0[5] : Multi/Single Block Select
89 * RD1WT0[4] : Data Transfer Direction Select
92 * ENACMD12[2] : Auto CMD12 Enable
93 * ENBLKCNT[1] : Block Count Enable
94 * ENDMA[0] : DMA Enable
96 mode = (1 << 1) | (1 << 0);
99 if (data->flags & MMC_DATA_READ)
102 writew(mode, &host->reg->trnmod);
105 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
106 struct mmc_data *data)
108 struct mmc_host *host = (struct mmc_host *)mmc->priv;
110 unsigned int timeout;
112 unsigned int retry = 0x100000;
113 debug(" mmc_send_cmd called\n");
120 * CMDINHDAT[1] : Command Inhibit (DAT)
121 * CMDINHCMD[0] : Command Inhibit (CMD)
124 if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
128 * We shouldn't wait for data inhibit for stop commands, even
129 * though they might use busy signaling
134 while (readl(&host->reg->prnsts) & mask) {
136 printf("%s: timeout error\n", __func__);
144 mmc_prepare_data(host, data);
146 debug("cmd->arg: %08x\n", cmd->cmdarg);
147 writel(cmd->cmdarg, &host->reg->argument);
150 mmc_set_transfer_mode(host, data);
152 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
157 * CMDIDX[13:8] : Command index
158 * DATAPRNT[5] : Data Present Select
159 * ENCMDIDX[4] : Command Index Check Enable
160 * ENCMDCRC[3] : Command CRC Check Enable
165 * 11 = Length 48 Check busy after response
167 if (!(cmd->resp_type & MMC_RSP_PRESENT))
169 else if (cmd->resp_type & MMC_RSP_136)
171 else if (cmd->resp_type & MMC_RSP_BUSY)
176 if (cmd->resp_type & MMC_RSP_CRC)
178 if (cmd->resp_type & MMC_RSP_OPCODE)
183 debug("cmd: %d\n", cmd->cmdidx);
185 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
187 for (i = 0; i < retry; i++) {
188 mask = readl(&host->reg->norintsts);
189 /* Command Complete */
190 if (mask & (1 << 0)) {
192 writel(mask, &host->reg->norintsts);
198 printf("%s: waiting for status update\n", __func__);
202 if (mask & (1 << 16)) {
204 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
206 } else if (mask & (1 << 15)) {
207 /* Error Interrupt */
208 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
212 if (cmd->resp_type & MMC_RSP_PRESENT) {
213 if (cmd->resp_type & MMC_RSP_136) {
214 /* CRC is stripped so we need to do some shifting. */
215 for (i = 0; i < 4; i++) {
216 unsigned int offset =
217 (unsigned int)(&host->reg->rspreg3 - i);
218 cmd->response[i] = readl(offset) << 8;
224 debug("cmd->resp[%d]: %08x\n",
225 i, cmd->response[i]);
227 } else if (cmd->resp_type & MMC_RSP_BUSY) {
228 for (i = 0; i < retry; i++) {
229 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
230 if (readl(&host->reg->prnsts)
231 & (1 << 20)) /* DAT[0] */
236 printf("%s: card is still busy\n", __func__);
240 cmd->response[0] = readl(&host->reg->rspreg0);
241 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
243 cmd->response[0] = readl(&host->reg->rspreg0);
244 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
250 mask = readl(&host->reg->norintsts);
252 if (mask & (1 << 15)) {
253 /* Error Interrupt */
254 writel(mask, &host->reg->norintsts);
255 printf("%s: error during transfer: 0x%08x\n",
258 } else if (mask & (1 << 3)) {
262 } else if (mask & (1 << 1)) {
263 /* Transfer Complete */
264 debug("r/w is done\n");
268 writel(mask, &host->reg->norintsts);
275 static void mmc_change_clock(struct mmc_host *host, uint clock)
279 unsigned long timeout;
280 unsigned int reg, hostbase;
281 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
282 debug(" mmc_change_clock called\n");
284 /* Change Tegra2 SDMMCx clock divisor here */
285 /* Source is 216MHz, PLLP_OUT0 */
290 if (clock <= 400000) {
291 hw_div = ((9-1)<<1); /* Best match is 375KHz */
293 } else if (clock <= 20000000)
294 hw_div = ((11-1)<<1); /* Best match is 19.6MHz */
295 else if (clock <= 26000000)
296 hw_div = ((9-1)<<1); /* Use 24MHz */
298 hw_div = ((4-1)<<1) + 1; /* 4.5 divisor for 48MHz */
300 debug("mmc_change_clock: hw_div = %d, card clock div = %d\n",
303 /* Change SDMMCx divisor */
305 hostbase = readl(&host->base);
306 debug("mmc_change_clock: hostbase = %08X\n", hostbase);
308 if (hostbase == TEGRA2_SDMMC1_BASE) {
309 reg = readl(&clkrst->crc_clk_src_sdmmc1);
310 reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
311 reg |= hw_div; /* n-1 */
312 writel(reg, &clkrst->crc_clk_src_sdmmc1);
313 } else if (hostbase == TEGRA2_SDMMC2_BASE) {
314 reg = readl(&clkrst->crc_clk_src_sdmmc2);
315 reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
316 reg |= hw_div; /* n-1 */
317 writel(reg, &clkrst->crc_clk_src_sdmmc2);
318 } else if (hostbase == TEGRA2_SDMMC3_BASE) {
319 reg = readl(&clkrst->crc_clk_src_sdmmc3);
320 reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
321 reg |= hw_div; /* n-1 */
322 writel(reg, &clkrst->crc_clk_src_sdmmc3);
324 reg = readl(&clkrst->crc_clk_src_sdmmc4);
325 reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
326 reg |= hw_div; /* n-1 */
327 writel(reg, &clkrst->crc_clk_src_sdmmc4);
330 writew(0, &host->reg->clkcon);
335 * SELFREQ[15:8] : base clock divided by value
336 * ENSDCLK[2] : SD Clock Enable
337 * STBLINTCLK[1] : Internal Clock Stable
338 * ENINTCLK[0] : Internal Clock Enable
340 clk = (div << 8) | (1 << 0);
341 writew(clk, &host->reg->clkcon);
345 while (!(readw(&host->reg->clkcon) & (1 << 1))) {
347 printf("%s: timeout error\n", __func__);
355 writew(clk, &host->reg->clkcon);
357 debug("mmc_change_clock: clkcon = %08X\n", clk);
358 debug("mmc_change_clock: CLK_SOURCE_SDMMCx = %08X\n", reg);
364 static void mmc_set_ios(struct mmc *mmc)
366 struct mmc_host *host = mmc->priv;
368 debug(" mmc_set_ios called\n");
370 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
372 /* Change clock first */
374 mmc_change_clock(host, mmc->clock);
376 ctrl = readb(&host->reg->hostctl);
380 * 0 = Depend on WIDE4
386 if (mmc->bus_width == 8)
388 else if (mmc->bus_width == 4)
393 writeb(ctrl, &host->reg->hostctl);
394 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
397 static void mmc_reset(struct mmc_host *host)
399 unsigned int timeout;
400 debug(" mmc_reset called\n");
403 * RSTALL[0] : Software reset for all
407 writeb((1 << 0), &host->reg->swrst);
411 /* Wait max 100 ms */
414 /* hw clears the bit when it's done */
415 while (readb(&host->reg->swrst) & (1 << 0)) {
417 printf("%s: timeout error\n", __func__);
425 static int mmc_core_init(struct mmc *mmc)
427 struct mmc_host *host = (struct mmc_host *)mmc->priv;
429 debug(" mmc_core_init called\n");
433 host->version = readw(&host->reg->hcver);
434 debug("host version = %x\n", host->version);
437 writel(0xffffffff, &host->reg->norintstsen);
438 writel(0xffffffff, &host->reg->norintsigen);
440 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
442 * NORMAL Interrupt Status Enable Register init
443 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
444 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
445 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
446 * [0] ENSTACMDCMPLT : Command Complete Status Enable
448 mask = readl(&host->reg->norintstsen);
450 mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
451 writel(mask, &host->reg->norintstsen);
454 * NORMAL Interrupt Signal Enable Register init
455 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
457 mask = readl(&host->reg->norintsigen);
460 writel(mask, &host->reg->norintsigen);
465 static int tegra2_mmc_initialize(int dev_index, int bus_width)
469 debug(" mmc_initialize called\n");
471 mmc = &mmc_dev[dev_index];
473 sprintf(mmc->name, "Tegra2 SD/MMC");
474 mmc->priv = &mmc_host[dev_index];
475 mmc->send_cmd = mmc_send_cmd;
476 mmc->set_ios = mmc_set_ios;
477 mmc->init = mmc_core_init;
479 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
481 mmc->host_caps = MMC_MODE_8BIT;
483 mmc->host_caps = MMC_MODE_4BIT;
484 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
487 * min freq is for card identification, and is the highest
488 * low-speed SDIO card frequency (actually 400KHz)
489 * max freq is highest HS eMMC clock as per the SD/MMC spec
491 * Both of these are the closest equivalents w/216MHz source
492 * clock and Tegra2 SDMMC divisors.
495 mmc->f_max = 48000000;
497 mmc_host[dev_index].clock = 0;
498 mmc_host[dev_index].reg = tegra2_get_base_mmc(dev_index);
499 mmc_host[dev_index].base = (unsigned int)mmc_host[dev_index].reg;
505 int tegra2_mmc_init(int dev_index, int bus_width)
507 debug(" tegra2_mmc_init: index %d, bus width %d\n",
508 dev_index, bus_width);
509 return tegra2_mmc_initialize(dev_index, bus_width);