drivers/mmc/sunxi_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2011
   4  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   5  * Aaron <leafy.myeh@allwinnertech.com>
   6  *
   7  * MMC driver for allwinner sunxi platform.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <clk.h>
  17 #include <reset.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc.h>
  23 #include <asm-generic/gpio.h>
  24 #include <linux/delay.h>
  25
  26 struct sunxi_mmc_plat {
  27         struct mmc_config cfg;
  28         struct mmc mmc;
  29 };
  30
  31 struct sunxi_mmc_priv {
  32         unsigned mmc_no;
  33         uint32_t *mclkreg;
  34         unsigned fatal_err;
  35         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  36         int cd_inverted;                /* Inverted Card Detect */
  37         struct sunxi_mmc *reg;
  38         struct mmc_config cfg;
  39 };
  40
  41 #if !CONFIG_IS_ENABLED(DM_MMC)
  42 /* support 4 mmc hosts */
  43 struct sunxi_mmc_priv mmc_host[4];
  44
  45 static int sunxi_mmc_getcd_gpio(int sdc_no)
  46 {
  47         switch (sdc_no) {
  48         case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  49         case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  50         case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  51         case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  52         }
  53         return -EINVAL;
  54 }
  55
  56 static int mmc_resource_init(int sdc_no)
  57 {
  58         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  59         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  60         int cd_pin, ret = 0;
  61
  62         debug("init mmc %d resource\n", sdc_no);
  63
  64         switch (sdc_no) {
  65         case 0:
  66                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  67                 priv->mclkreg = &ccm->sd0_clk_cfg;
  68                 break;
  69         case 1:
  70                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  71                 priv->mclkreg = &ccm->sd1_clk_cfg;
  72                 break;
  73         case 2:
  74                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  75                 priv->mclkreg = &ccm->sd2_clk_cfg;
  76                 break;
  77 #ifdef SUNXI_MMC3_BASE
  78         case 3:
  79                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  80                 priv->mclkreg = &ccm->sd3_clk_cfg;
  81                 break;
  82 #endif
  83         default:
  84                 printf("Wrong mmc number %d\n", sdc_no);
  85                 return -1;
  86         }
  87         priv->mmc_no = sdc_no;
  88
  89         cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  90         if (cd_pin >= 0) {
  91                 ret = gpio_request(cd_pin, "mmc_cd");
  92                 if (!ret) {
  93                         sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  94                         ret = gpio_direction_input(cd_pin);
  95                 }
  96         }
  97
  98         return ret;
  99 }
 100 #endif
 101
 102 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 103 {
 104         unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
 105         bool new_mode = true;
 106         bool calibrate = false;
 107         u32 val = 0;
 108
 109         if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
 110                 new_mode = false;
 111
 112         /* A83T support new mode only on eMMC */
 113         if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
 114                 new_mode = false;
 115
 116 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_SUN50I_GEN_H6)
 117         calibrate = true;
 118 #endif
 119
 120         if (hz <= 24000000) {
 121                 pll = CCM_MMC_CTRL_OSCM24;
 122                 pll_hz = 24000000;
 123         } else {
 124 #ifdef CONFIG_MACH_SUN9I
 125                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
 126                 pll_hz = clock_get_pll4_periph0();
 127 #elif defined(CONFIG_SUN50I_GEN_H6)
 128                 pll = CCM_MMC_CTRL_PLL6X2;
 129                 pll_hz = clock_get_pll6() * 2;
 130 #else
 131                 pll = CCM_MMC_CTRL_PLL6;
 132                 pll_hz = clock_get_pll6();
 133 #endif
 134         }
 135
 136         div = pll_hz / hz;
 137         if (pll_hz % hz)
 138                 div++;
 139
 140         n = 0;
 141         while (div > 16) {
 142                 n++;
 143                 div = (div + 1) / 2;
 144         }
 145
 146         if (n > 3) {
 147                 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
 148                        hz);
 149                 return -1;
 150         }
 151
 152         /* determine delays */
 153         if (hz <= 400000) {
 154                 oclk_dly = 0;
 155                 sclk_dly = 0;
 156         } else if (hz <= 25000000) {
 157                 oclk_dly = 0;
 158                 sclk_dly = 5;
 159 #ifdef CONFIG_MACH_SUN9I
 160         } else if (hz <= 52000000) {
 161                 oclk_dly = 5;
 162                 sclk_dly = 4;
 163         } else {
 164                 /* hz > 52000000 */
 165                 oclk_dly = 2;
 166                 sclk_dly = 4;
 167 #else
 168         } else if (hz <= 52000000) {
 169                 oclk_dly = 3;
 170                 sclk_dly = 4;
 171         } else {
 172                 /* hz > 52000000 */
 173                 oclk_dly = 1;
 174                 sclk_dly = 4;
 175 #endif
 176         }
 177
 178         if (new_mode) {
 179 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
 180 #ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
 181                 val = CCM_MMC_CTRL_MODE_SEL_NEW;
 182 #endif
 183                 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 184 #endif
 185         } else if (!calibrate) {
 186                 /*
 187                  * Use hardcoded delay values if controller doesn't support
 188                  * calibration
 189                  */
 190                 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 191                         CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
 192         }
 193
 194         writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
 195                CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
 196
 197         debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 198               priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
 199
 200         return 0;
 201 }
 202
 203 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
 204 {
 205         unsigned int cmd;
 206         unsigned timeout_msecs = 2000;
 207         unsigned long start = get_timer(0);
 208
 209         cmd = SUNXI_MMC_CMD_START |
 210               SUNXI_MMC_CMD_UPCLK_ONLY |
 211               SUNXI_MMC_CMD_WAIT_PRE_OVER;
 212
 213         writel(cmd, &priv->reg->cmd);
 214         while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
 215                 if (get_timer(start) > timeout_msecs)
 216                         return -1;
 217         }
 218
 219         /* clock update sets various irq status bits, clear these */
 220         writel(readl(&priv->reg->rint), &priv->reg->rint);
 221
 222         return 0;
 223 }
 224
 225 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
 226 {
 227         unsigned rval = readl(&priv->reg->clkcr);
 228
 229         /* Disable Clock */
 230         rval &= ~SUNXI_MMC_CLK_ENABLE;
 231         writel(rval, &priv->reg->clkcr);
 232         if (mmc_update_clk(priv))
 233                 return -1;
 234
 235         /* Set mod_clk to new rate */
 236         if (mmc_set_mod_clk(priv, mmc->clock))
 237                 return -1;
 238
 239         /* Clear internal divider */
 240         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 241         writel(rval, &priv->reg->clkcr);
 242
 243 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_SUN50I_GEN_H6)
 244         /* A64 supports calibration of delays on MMC controller and we
 245          * have to set delay of zero before starting calibration.
 246          * Allwinner BSP driver sets a delay only in the case of
 247          * using HS400 which is not supported by mainline U-Boot or
 248          * Linux at the moment
 249          */
 250         writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
 251 #endif
 252
 253         /* Re-enable Clock */
 254         rval |= SUNXI_MMC_CLK_ENABLE;
 255         writel(rval, &priv->reg->clkcr);
 256         if (mmc_update_clk(priv))
 257                 return -1;
 258
 259         return 0;
 260 }
 261
 262 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
 263                                     struct mmc *mmc)
 264 {
 265         debug("set ios: bus_width: %x, clock: %d\n",
 266               mmc->bus_width, mmc->clock);
 267
 268         /* Change clock first */
 269         if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
 270                 priv->fatal_err = 1;
 271                 return -EINVAL;
 272         }
 273
 274         /* Change bus width */
 275         if (mmc->bus_width == 8)
 276                 writel(0x2, &priv->reg->width);
 277         else if (mmc->bus_width == 4)
 278                 writel(0x1, &priv->reg->width);
 279         else
 280                 writel(0x0, &priv->reg->width);
 281
 282         return 0;
 283 }
 284
 285 #if !CONFIG_IS_ENABLED(DM_MMC)
 286 static int sunxi_mmc_core_init(struct mmc *mmc)
 287 {
 288         struct sunxi_mmc_priv *priv = mmc->priv;
 289
 290         /* Reset controller */
 291         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 292         udelay(1000);
 293
 294         return 0;
 295 }
 296 #endif
 297
 298 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 299                                  struct mmc_data *data)
 300 {
 301         const int reading = !!(data->flags & MMC_DATA_READ);
 302         const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
 303                                               SUNXI_MMC_STATUS_FIFO_FULL;
 304         unsigned i;
 305         unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 306         unsigned byte_cnt = data->blocksize * data->blocks;
 307         unsigned timeout_msecs = byte_cnt >> 8;
 308         unsigned long  start;
 309
 310         if (timeout_msecs < 2000)
 311                 timeout_msecs = 2000;
 312
 313         /* Always read / write data through the CPU */
 314         setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 315
 316         start = get_timer(0);
 317
 318         for (i = 0; i < (byte_cnt >> 2); i++) {
 319                 while (readl(&priv->reg->status) & status_bit) {
 320                         if (get_timer(start) > timeout_msecs)
 321                                 return -1;
 322                 }
 323
 324                 if (reading)
 325                         buff[i] = readl(&priv->reg->fifo);
 326                 else
 327                         writel(buff[i], &priv->reg->fifo);
 328         }
 329
 330         return 0;
 331 }
 332
 333 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 334                          uint timeout_msecs, uint done_bit, const char *what)
 335 {
 336         unsigned int status;
 337         unsigned long start = get_timer(0);
 338
 339         do {
 340                 status = readl(&priv->reg->rint);
 341                 if ((get_timer(start) > timeout_msecs) ||
 342                     (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
 343                         debug("%s timeout %x\n", what,
 344                               status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
 345                         return -ETIMEDOUT;
 346                 }
 347         } while (!(status & done_bit));
 348
 349         return 0;
 350 }
 351
 352 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
 353                                      struct mmc *mmc, struct mmc_cmd *cmd,
 354                                      struct mmc_data *data)
 355 {
 356         unsigned int cmdval = SUNXI_MMC_CMD_START;
 357         unsigned int timeout_msecs;
 358         int error = 0;
 359         unsigned int status = 0;
 360         unsigned int bytecnt = 0;
 361
 362         if (priv->fatal_err)
 363                 return -1;
 364         if (cmd->resp_type & MMC_RSP_BUSY)
 365                 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
 366         if (cmd->cmdidx == 12)
 367                 return 0;
 368
 369         if (!cmd->cmdidx)
 370                 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 371         if (cmd->resp_type & MMC_RSP_PRESENT)
 372                 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 373         if (cmd->resp_type & MMC_RSP_136)
 374                 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 375         if (cmd->resp_type & MMC_RSP_CRC)
 376                 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 377
 378         if (data) {
 379                 if ((u32)(long)data->dest & 0x3) {
 380                         error = -1;
 381                         goto out;
 382                 }
 383
 384                 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 385                 if (data->flags & MMC_DATA_WRITE)
 386                         cmdval |= SUNXI_MMC_CMD_WRITE;
 387                 if (data->blocks > 1)
 388                         cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 389                 writel(data->blocksize, &priv->reg->blksz);
 390                 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
 391         }
 392
 393         debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
 394               cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 395         writel(cmd->cmdarg, &priv->reg->arg);
 396
 397         if (!data)
 398                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 399
 400         /*
 401          * transfer data and check status
 402          * STATREG[2] : FIFO empty
 403          * STATREG[3] : FIFO full
 404          */
 405         if (data) {
 406                 int ret = 0;
 407
 408                 bytecnt = data->blocksize * data->blocks;
 409                 debug("trans data %d bytes\n", bytecnt);
 410                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 411                 ret = mmc_trans_data_by_cpu(priv, mmc, data);
 412                 if (ret) {
 413                         error = readl(&priv->reg->rint) &
 414                                 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 415                         error = -ETIMEDOUT;
 416                         goto out;
 417                 }
 418         }
 419
 420         error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
 421                               "cmd");
 422         if (error)
 423                 goto out;
 424
 425         if (data) {
 426                 timeout_msecs = 120;
 427                 debug("cacl timeout %x msec\n", timeout_msecs);
 428                 error = mmc_rint_wait(priv, mmc, timeout_msecs,
 429                                       data->blocks > 1 ?
 430                                       SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
 431                                       SUNXI_MMC_RINT_DATA_OVER,
 432                                       "data");
 433                 if (error)
 434                         goto out;
 435         }
 436
 437         if (cmd->resp_type & MMC_RSP_BUSY) {
 438                 unsigned long start = get_timer(0);
 439                 timeout_msecs = 2000;
 440
 441                 do {
 442                         status = readl(&priv->reg->status);
 443                         if (get_timer(start) > timeout_msecs) {
 444                                 debug("busy timeout\n");
 445                                 error = -ETIMEDOUT;
 446                                 goto out;
 447                         }
 448                 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 449         }
 450
 451         if (cmd->resp_type & MMC_RSP_136) {
 452                 cmd->response[0] = readl(&priv->reg->resp3);
 453                 cmd->response[1] = readl(&priv->reg->resp2);
 454                 cmd->response[2] = readl(&priv->reg->resp1);
 455                 cmd->response[3] = readl(&priv->reg->resp0);
 456                 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
 457                       cmd->response[3], cmd->response[2],
 458                       cmd->response[1], cmd->response[0]);
 459         } else {
 460                 cmd->response[0] = readl(&priv->reg->resp0);
 461                 debug("mmc resp 0x%08x\n", cmd->response[0]);
 462         }
 463 out:
 464         if (error < 0) {
 465                 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 466                 mmc_update_clk(priv);
 467         }
 468         writel(0xffffffff, &priv->reg->rint);
 469         writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
 470                &priv->reg->gctrl);
 471
 472         return error;
 473 }
 474
 475 #if !CONFIG_IS_ENABLED(DM_MMC)
 476 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
 477 {
 478         struct sunxi_mmc_priv *priv = mmc->priv;
 479
 480         return sunxi_mmc_set_ios_common(priv, mmc);
 481 }
 482
 483 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
 484                                      struct mmc_data *data)
 485 {
 486         struct sunxi_mmc_priv *priv = mmc->priv;
 487
 488         return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
 489 }
 490
 491 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
 492 {
 493         struct sunxi_mmc_priv *priv = mmc->priv;
 494         int cd_pin;
 495
 496         cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
 497         if (cd_pin < 0)
 498                 return 1;
 499
 500         return !gpio_get_value(cd_pin);
 501 }
 502
 503 static const struct mmc_ops sunxi_mmc_ops = {
 504         .send_cmd       = sunxi_mmc_send_cmd_legacy,
 505         .set_ios        = sunxi_mmc_set_ios_legacy,
 506         .init           = sunxi_mmc_core_init,
 507         .getcd          = sunxi_mmc_getcd_legacy,
 508 };
 509
 510 struct mmc *sunxi_mmc_init(int sdc_no)
 511 {
 512         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 513         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
 514         struct mmc_config *cfg = &priv->cfg;
 515         int ret;
 516
 517         memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
 518
 519         cfg->name = "SUNXI SD/MMC";
 520         cfg->ops  = &sunxi_mmc_ops;
 521
 522         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 523         cfg->host_caps = MMC_MODE_4BIT;
 524 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_SUN50I_GEN_H6)
 525         if (sdc_no == 2)
 526                 cfg->host_caps = MMC_MODE_8BIT;
 527 #endif
 528         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 529         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 530
 531         cfg->f_min = 400000;
 532         cfg->f_max = 52000000;
 533
 534         if (mmc_resource_init(sdc_no) != 0)
 535                 return NULL;
 536
 537         /* config ahb clock */
 538         debug("init mmc %d clock and io\n", sdc_no);
 539 #if !defined(CONFIG_SUN50I_GEN_H6)
 540         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 541
 542 #ifdef CONFIG_SUNXI_GEN_SUN6I
 543         /* unassert reset */
 544         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 545 #endif
 546 #if defined(CONFIG_MACH_SUN9I)
 547         /* sun9i has a mmc-common module, also set the gate and reset there */
 548         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
 549                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
 550 #endif
 551 #else /* CONFIG_SUN50I_GEN_H6 */
 552         setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
 553         /* unassert reset */
 554         setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
 555 #endif
 556         ret = mmc_set_mod_clk(priv, 24000000);
 557         if (ret)
 558                 return NULL;
 559
 560         return mmc_create(cfg, priv);
 561 }
 562 #else
 563
 564 static int sunxi_mmc_set_ios(struct udevice *dev)
 565 {
 566         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 567         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 568
 569         return sunxi_mmc_set_ios_common(priv, &plat->mmc);
 570 }
 571
 572 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 573                               struct mmc_data *data)
 574 {
 575         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 576         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 577
 578         return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
 579 }
 580
 581 static int sunxi_mmc_getcd(struct udevice *dev)
 582 {
 583         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 584
 585         if (dm_gpio_is_valid(&priv->cd_gpio)) {
 586                 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
 587
 588                 return cd_state ^ priv->cd_inverted;
 589         }
 590         return 1;
 591 }
 592
 593 static const struct dm_mmc_ops sunxi_mmc_ops = {
 594         .send_cmd       = sunxi_mmc_send_cmd,
 595         .set_ios        = sunxi_mmc_set_ios,
 596         .get_cd         = sunxi_mmc_getcd,
 597 };
 598
 599 static unsigned get_mclk_offset(void)
 600 {
 601         if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
 602                 return 0x410;
 603
 604         if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 605                 return 0x830;
 606
 607         return 0x88;
 608 };
 609
 610 static int sunxi_mmc_probe(struct udevice *dev)
 611 {
 612         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 613         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 614         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 615         struct reset_ctl_bulk reset_bulk;
 616         struct clk gate_clk;
 617         struct mmc_config *cfg = &plat->cfg;
 618         struct ofnode_phandle_args args;
 619         u32 *ccu_reg;
 620         int bus_width, ret;
 621
 622         cfg->name = dev->name;
 623         bus_width = dev_read_u32_default(dev, "bus-width", 1);
 624
 625         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 626         cfg->host_caps = 0;
 627         if (bus_width == 8)
 628                 cfg->host_caps |= MMC_MODE_8BIT;
 629         if (bus_width >= 4)
 630                 cfg->host_caps |= MMC_MODE_4BIT;
 631         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 632         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 633
 634         cfg->f_min = 400000;
 635         cfg->f_max = 52000000;
 636
 637         priv->reg = (void *)dev_read_addr(dev);
 638
 639         /* We don't have a sunxi clock driver so find the clock address here */
 640         ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
 641                                           1, &args);
 642         if (ret)
 643                 return ret;
 644         ccu_reg = (u32 *)ofnode_get_addr(args.node);
 645
 646         priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
 647         priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
 648
 649         ret = clk_get_by_name(dev, "ahb", &gate_clk);
 650         if (!ret)
 651                 clk_enable(&gate_clk);
 652
 653         ret = reset_get_bulk(dev, &reset_bulk);
 654         if (!ret)
 655                 reset_deassert_bulk(&reset_bulk);
 656
 657         ret = mmc_set_mod_clk(priv, 24000000);
 658         if (ret)
 659                 return ret;
 660
 661         /* This GPIO is optional */
 662         if (!dev_read_bool(dev, "non-removable") &&
 663             !gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 664                                   GPIOD_IS_IN)) {
 665                 int cd_pin = gpio_get_number(&priv->cd_gpio);
 666
 667                 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
 668         }
 669
 670         /* Check if card detect is inverted */
 671         priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
 672
 673         upriv->mmc = &plat->mmc;
 674
 675         /* Reset controller */
 676         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 677         udelay(1000);
 678
 679         return 0;
 680 }
 681
 682 static int sunxi_mmc_bind(struct udevice *dev)
 683 {
 684         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 685
 686         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 687 }
 688
 689 static const struct udevice_id sunxi_mmc_ids[] = {
 690         { .compatible = "allwinner,sun4i-a10-mmc" },
 691         { .compatible = "allwinner,sun5i-a13-mmc" },
 692         { .compatible = "allwinner,sun7i-a20-mmc" },
 693         { .compatible = "allwinner,sun8i-a83t-emmc" },
 694         { .compatible = "allwinner,sun9i-a80-mmc" },
 695         { .compatible = "allwinner,sun50i-a64-mmc" },
 696         { .compatible = "allwinner,sun50i-a64-emmc" },
 697         { .compatible = "allwinner,sun50i-h6-mmc" },
 698         { .compatible = "allwinner,sun50i-h6-emmc" },
 699         { .compatible = "allwinner,sun50i-a100-mmc" },
 700         { .compatible = "allwinner,sun50i-a100-emmc" },
 701         { /* sentinel */ }
 702 };
 703
 704 U_BOOT_DRIVER(sunxi_mmc_drv) = {
 705         .name           = "sunxi_mmc",
 706         .id             = UCLASS_MMC,
 707         .of_match       = sunxi_mmc_ids,
 708         .bind           = sunxi_mmc_bind,
 709         .probe          = sunxi_mmc_probe,
 710         .ops            = &sunxi_mmc_ops,
 711         .plat_auto      = sizeof(struct sunxi_mmc_plat),
 712         .priv_auto      = sizeof(struct sunxi_mmc_priv),
 713 };
 714 #endif