drivers/mmc/sunxi_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2011
   4  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   5  * Aaron <leafy.myeh@allwinnertech.com>
   6  *
   7  * MMC driver for allwinner sunxi platform.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <clk.h>
  17 #include <reset.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc.h>
  23 #include <asm-generic/gpio.h>
  24 #include <linux/delay.h>
  25
  26 #ifndef CCM_MMC_CTRL_MODE_SEL_NEW
  27 #define CCM_MMC_CTRL_MODE_SEL_NEW       0
  28 #endif
  29
  30 struct sunxi_mmc_plat {
  31         struct mmc_config cfg;
  32         struct mmc mmc;
  33 };
  34
  35 struct sunxi_mmc_priv {
  36         unsigned mmc_no;
  37         uint32_t *mclkreg;
  38         unsigned fatal_err;
  39         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  40         struct sunxi_mmc *reg;
  41         struct mmc_config cfg;
  42 };
  43
  44 #if !CONFIG_IS_ENABLED(DM_MMC)
  45 /* support 4 mmc hosts */
  46 struct sunxi_mmc_priv mmc_host[4];
  47
  48 static int sunxi_mmc_getcd_gpio(int sdc_no)
  49 {
  50         switch (sdc_no) {
  51         case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  52         case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  53         case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  54         case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  55         }
  56         return -EINVAL;
  57 }
  58
  59 static int mmc_resource_init(int sdc_no)
  60 {
  61         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  62         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  63         int cd_pin, ret = 0;
  64
  65         debug("init mmc %d resource\n", sdc_no);
  66
  67         switch (sdc_no) {
  68         case 0:
  69                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  70                 priv->mclkreg = &ccm->sd0_clk_cfg;
  71                 break;
  72         case 1:
  73                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  74                 priv->mclkreg = &ccm->sd1_clk_cfg;
  75                 break;
  76         case 2:
  77                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  78                 priv->mclkreg = &ccm->sd2_clk_cfg;
  79                 break;
  80 #ifdef SUNXI_MMC3_BASE
  81         case 3:
  82                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  83                 priv->mclkreg = &ccm->sd3_clk_cfg;
  84                 break;
  85 #endif
  86         default:
  87                 printf("Wrong mmc number %d\n", sdc_no);
  88                 return -1;
  89         }
  90         priv->mmc_no = sdc_no;
  91
  92         cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  93         if (cd_pin >= 0) {
  94                 ret = gpio_request(cd_pin, "mmc_cd");
  95                 if (!ret) {
  96                         sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  97                         ret = gpio_direction_input(cd_pin);
  98                 }
  99         }
 100
 101         return ret;
 102 }
 103 #endif
 104
 105 /*
 106  * All A64 and later MMC controllers feature auto-calibration. This would
 107  * normally be detected via the compatible string, but we need something
 108  * which works in the SPL as well.
 109  */
 110 static bool sunxi_mmc_can_calibrate(void)
 111 {
 112         return IS_ENABLED(CONFIG_MACH_SUN50I) ||
 113                IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
 114                IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
 115                IS_ENABLED(CONFIG_MACH_SUN8I_R40);
 116 }
 117
 118 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 119 {
 120         unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
 121         bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
 122         u32 val = 0;
 123
 124         /* A83T support new mode only on eMMC */
 125         if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
 126                 new_mode = false;
 127
 128         if (hz <= 24000000) {
 129                 pll = CCM_MMC_CTRL_OSCM24;
 130                 pll_hz = 24000000;
 131         } else {
 132 #ifdef CONFIG_MACH_SUN9I
 133                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
 134                 pll_hz = clock_get_pll4_periph0();
 135 #else
 136                 /*
 137                  * SoCs since the A64 (H5, H6, H616) actually use the doubled
 138                  * rate of PLL6/PERIPH0 as an input clock, but compensate for
 139                  * that with a fixed post-divider of 2 in the mod clock.
 140                  * This cancels each other out, so for simplicity we just
 141                  * pretend it's always PLL6 without a post divider here.
 142                  */
 143                 pll = CCM_MMC_CTRL_PLL6;
 144                 pll_hz = clock_get_pll6();
 145 #endif
 146         }
 147
 148         div = pll_hz / hz;
 149         if (pll_hz % hz)
 150                 div++;
 151
 152         n = 0;
 153         while (div > 16) {
 154                 n++;
 155                 div = (div + 1) / 2;
 156         }
 157
 158         if (n > 3) {
 159                 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
 160                        hz);
 161                 return -1;
 162         }
 163
 164         /* determine delays */
 165         if (hz <= 400000) {
 166                 oclk_dly = 0;
 167                 sclk_dly = 0;
 168         } else if (hz <= 25000000) {
 169                 oclk_dly = 0;
 170                 sclk_dly = 5;
 171         } else {
 172                 if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
 173                         if (hz <= 52000000)
 174                                 oclk_dly = 5;
 175                         else
 176                                 oclk_dly = 2;
 177                 } else {
 178                         if (hz <= 52000000)
 179                                 oclk_dly = 3;
 180                         else
 181                                 oclk_dly = 1;
 182                 }
 183                 sclk_dly = 4;
 184         }
 185
 186         if (new_mode) {
 187                 val |= CCM_MMC_CTRL_MODE_SEL_NEW;
 188                 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 189         }
 190
 191         if (!sunxi_mmc_can_calibrate()) {
 192                 /*
 193                  * Use hardcoded delay values if controller doesn't support
 194                  * calibration
 195                  */
 196                 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 197                         CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
 198         }
 199
 200         writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
 201                CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
 202
 203         debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 204               priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
 205
 206         return 0;
 207 }
 208
 209 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
 210 {
 211         unsigned int cmd;
 212         unsigned timeout_msecs = 2000;
 213         unsigned long start = get_timer(0);
 214
 215         cmd = SUNXI_MMC_CMD_START |
 216               SUNXI_MMC_CMD_UPCLK_ONLY |
 217               SUNXI_MMC_CMD_WAIT_PRE_OVER;
 218
 219         writel(cmd, &priv->reg->cmd);
 220         while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
 221                 if (get_timer(start) > timeout_msecs)
 222                         return -1;
 223         }
 224
 225         /* clock update sets various irq status bits, clear these */
 226         writel(readl(&priv->reg->rint), &priv->reg->rint);
 227
 228         return 0;
 229 }
 230
 231 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
 232 {
 233         unsigned rval = readl(&priv->reg->clkcr);
 234
 235         /* Disable Clock */
 236         rval &= ~SUNXI_MMC_CLK_ENABLE;
 237         writel(rval, &priv->reg->clkcr);
 238         if (mmc_update_clk(priv))
 239                 return -1;
 240
 241         /* Set mod_clk to new rate */
 242         if (mmc_set_mod_clk(priv, mmc->clock))
 243                 return -1;
 244
 245         /* Clear internal divider */
 246         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 247         writel(rval, &priv->reg->clkcr);
 248
 249 #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
 250         /* A64 supports calibration of delays on MMC controller and we
 251          * have to set delay of zero before starting calibration.
 252          * Allwinner BSP driver sets a delay only in the case of
 253          * using HS400 which is not supported by mainline U-Boot or
 254          * Linux at the moment
 255          */
 256         if (sunxi_mmc_can_calibrate())
 257                 writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
 258 #endif
 259
 260         /* Re-enable Clock */
 261         rval |= SUNXI_MMC_CLK_ENABLE;
 262         writel(rval, &priv->reg->clkcr);
 263         if (mmc_update_clk(priv))
 264                 return -1;
 265
 266         return 0;
 267 }
 268
 269 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
 270                                     struct mmc *mmc)
 271 {
 272         debug("set ios: bus_width: %x, clock: %d\n",
 273               mmc->bus_width, mmc->clock);
 274
 275         /* Change clock first */
 276         if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
 277                 priv->fatal_err = 1;
 278                 return -EINVAL;
 279         }
 280
 281         /* Change bus width */
 282         if (mmc->bus_width == 8)
 283                 writel(0x2, &priv->reg->width);
 284         else if (mmc->bus_width == 4)
 285                 writel(0x1, &priv->reg->width);
 286         else
 287                 writel(0x0, &priv->reg->width);
 288
 289         return 0;
 290 }
 291
 292 #if !CONFIG_IS_ENABLED(DM_MMC)
 293 static int sunxi_mmc_core_init(struct mmc *mmc)
 294 {
 295         struct sunxi_mmc_priv *priv = mmc->priv;
 296
 297         /* Reset controller */
 298         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 299         udelay(1000);
 300
 301         return 0;
 302 }
 303 #endif
 304
 305 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 306                                  struct mmc_data *data)
 307 {
 308         const int reading = !!(data->flags & MMC_DATA_READ);
 309         const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
 310                                               SUNXI_MMC_STATUS_FIFO_FULL;
 311         unsigned i;
 312         unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 313         unsigned word_cnt = (data->blocksize * data->blocks) >> 2;
 314         unsigned timeout_msecs = word_cnt >> 6;
 315         uint32_t status;
 316         unsigned long  start;
 317
 318         if (timeout_msecs < 2000)
 319                 timeout_msecs = 2000;
 320
 321         /* Always read / write data through the CPU */
 322         setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 323
 324         start = get_timer(0);
 325
 326         for (i = 0; i < word_cnt;) {
 327                 unsigned int in_fifo;
 328
 329                 while ((status = readl(&priv->reg->status)) & status_bit) {
 330                         if (get_timer(start) > timeout_msecs)
 331                                 return -1;
 332                 }
 333
 334                 /*
 335                  * For writing we do not easily know the FIFO size, so have
 336                  * to check the FIFO status after every word written.
 337                  * TODO: For optimisation we could work out a minimum FIFO
 338                  * size across all SoCs, and use that together with the current
 339                  * fill level to write chunks of words.
 340                  */
 341                 if (!reading) {
 342                         writel(buff[i++], &priv->reg->fifo);
 343                         continue;
 344                 }
 345
 346                 /*
 347                  * The status register holds the current FIFO level, so we
 348                  * can be sure to collect as many words from the FIFO
 349                  * register without checking the status register after every
 350                  * read. That saves half of the costly MMIO reads, effectively
 351                  * doubling the read performance.
 352                  */
 353                 for (in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
 354                      in_fifo > 0;
 355                      in_fifo--)
 356                         buff[i++] = readl_relaxed(&priv->reg->fifo);
 357                 dmb();
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 364                          uint timeout_msecs, uint done_bit, const char *what)
 365 {
 366         unsigned int status;
 367         unsigned long start = get_timer(0);
 368
 369         do {
 370                 status = readl(&priv->reg->rint);
 371                 if ((get_timer(start) > timeout_msecs) ||
 372                     (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
 373                         debug("%s timeout %x\n", what,
 374                               status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
 375                         return -ETIMEDOUT;
 376                 }
 377         } while (!(status & done_bit));
 378
 379         return 0;
 380 }
 381
 382 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
 383                                      struct mmc *mmc, struct mmc_cmd *cmd,
 384                                      struct mmc_data *data)
 385 {
 386         unsigned int cmdval = SUNXI_MMC_CMD_START;
 387         unsigned int timeout_msecs;
 388         int error = 0;
 389         unsigned int status = 0;
 390         unsigned int bytecnt = 0;
 391
 392         if (priv->fatal_err)
 393                 return -1;
 394         if (cmd->resp_type & MMC_RSP_BUSY)
 395                 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
 396         if (cmd->cmdidx == 12)
 397                 return 0;
 398
 399         if (!cmd->cmdidx)
 400                 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 401         if (cmd->resp_type & MMC_RSP_PRESENT)
 402                 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 403         if (cmd->resp_type & MMC_RSP_136)
 404                 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 405         if (cmd->resp_type & MMC_RSP_CRC)
 406                 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 407
 408         if (data) {
 409                 if ((u32)(long)data->dest & 0x3) {
 410                         error = -1;
 411                         goto out;
 412                 }
 413
 414                 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 415                 if (data->flags & MMC_DATA_WRITE)
 416                         cmdval |= SUNXI_MMC_CMD_WRITE;
 417                 if (data->blocks > 1)
 418                         cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 419                 writel(data->blocksize, &priv->reg->blksz);
 420                 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
 421         }
 422
 423         debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
 424               cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 425         writel(cmd->cmdarg, &priv->reg->arg);
 426
 427         if (!data)
 428                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 429
 430         /*
 431          * transfer data and check status
 432          * STATREG[2] : FIFO empty
 433          * STATREG[3] : FIFO full
 434          */
 435         if (data) {
 436                 int ret = 0;
 437
 438                 bytecnt = data->blocksize * data->blocks;
 439                 debug("trans data %d bytes\n", bytecnt);
 440                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 441                 ret = mmc_trans_data_by_cpu(priv, mmc, data);
 442                 if (ret) {
 443                         error = readl(&priv->reg->rint) &
 444                                 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 445                         error = -ETIMEDOUT;
 446                         goto out;
 447                 }
 448         }
 449
 450         error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
 451                               "cmd");
 452         if (error)
 453                 goto out;
 454
 455         if (data) {
 456                 timeout_msecs = 120;
 457                 debug("cacl timeout %x msec\n", timeout_msecs);
 458                 error = mmc_rint_wait(priv, mmc, timeout_msecs,
 459                                       data->blocks > 1 ?
 460                                       SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
 461                                       SUNXI_MMC_RINT_DATA_OVER,
 462                                       "data");
 463                 if (error)
 464                         goto out;
 465         }
 466
 467         if (cmd->resp_type & MMC_RSP_BUSY) {
 468                 unsigned long start = get_timer(0);
 469                 timeout_msecs = 2000;
 470
 471                 do {
 472                         status = readl(&priv->reg->status);
 473                         if (get_timer(start) > timeout_msecs) {
 474                                 debug("busy timeout\n");
 475                                 error = -ETIMEDOUT;
 476                                 goto out;
 477                         }
 478                 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 479         }
 480
 481         if (cmd->resp_type & MMC_RSP_136) {
 482                 cmd->response[0] = readl(&priv->reg->resp3);
 483                 cmd->response[1] = readl(&priv->reg->resp2);
 484                 cmd->response[2] = readl(&priv->reg->resp1);
 485                 cmd->response[3] = readl(&priv->reg->resp0);
 486                 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
 487                       cmd->response[3], cmd->response[2],
 488                       cmd->response[1], cmd->response[0]);
 489         } else {
 490                 cmd->response[0] = readl(&priv->reg->resp0);
 491                 debug("mmc resp 0x%08x\n", cmd->response[0]);
 492         }
 493 out:
 494         if (error < 0) {
 495                 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 496                 mmc_update_clk(priv);
 497         }
 498         writel(0xffffffff, &priv->reg->rint);
 499         writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
 500                &priv->reg->gctrl);
 501
 502         return error;
 503 }
 504
 505 #if !CONFIG_IS_ENABLED(DM_MMC)
 506 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
 507 {
 508         struct sunxi_mmc_priv *priv = mmc->priv;
 509
 510         return sunxi_mmc_set_ios_common(priv, mmc);
 511 }
 512
 513 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
 514                                      struct mmc_data *data)
 515 {
 516         struct sunxi_mmc_priv *priv = mmc->priv;
 517
 518         return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
 519 }
 520
 521 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
 522 {
 523         struct sunxi_mmc_priv *priv = mmc->priv;
 524         int cd_pin;
 525
 526         cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
 527         if (cd_pin < 0)
 528                 return 1;
 529
 530         return !gpio_get_value(cd_pin);
 531 }
 532
 533 static const struct mmc_ops sunxi_mmc_ops = {
 534         .send_cmd       = sunxi_mmc_send_cmd_legacy,
 535         .set_ios        = sunxi_mmc_set_ios_legacy,
 536         .init           = sunxi_mmc_core_init,
 537         .getcd          = sunxi_mmc_getcd_legacy,
 538 };
 539
 540 struct mmc *sunxi_mmc_init(int sdc_no)
 541 {
 542         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 543         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
 544         struct mmc_config *cfg = &priv->cfg;
 545         int ret;
 546
 547         memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
 548
 549         cfg->name = "SUNXI SD/MMC";
 550         cfg->ops  = &sunxi_mmc_ops;
 551
 552         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 553         cfg->host_caps = MMC_MODE_4BIT;
 554
 555         if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) ||
 556             IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2))
 557                 cfg->host_caps = MMC_MODE_8BIT;
 558
 559         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 560         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 561
 562         cfg->f_min = 400000;
 563         cfg->f_max = 52000000;
 564
 565         if (mmc_resource_init(sdc_no) != 0)
 566                 return NULL;
 567
 568         /* config ahb clock */
 569         debug("init mmc %d clock and io\n", sdc_no);
 570 #if !defined(CONFIG_SUN50I_GEN_H6)
 571         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 572
 573 #ifdef CONFIG_SUNXI_GEN_SUN6I
 574         /* unassert reset */
 575         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 576 #endif
 577 #if defined(CONFIG_MACH_SUN9I)
 578         /* sun9i has a mmc-common module, also set the gate and reset there */
 579         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
 580                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
 581 #endif
 582 #else /* CONFIG_SUN50I_GEN_H6 */
 583         setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
 584         /* unassert reset */
 585         setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
 586 #endif
 587         ret = mmc_set_mod_clk(priv, 24000000);
 588         if (ret)
 589                 return NULL;
 590
 591         return mmc_create(cfg, priv);
 592 }
 593 #else
 594
 595 static int sunxi_mmc_set_ios(struct udevice *dev)
 596 {
 597         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 598         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 599
 600         return sunxi_mmc_set_ios_common(priv, &plat->mmc);
 601 }
 602
 603 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 604                               struct mmc_data *data)
 605 {
 606         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 607         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 608
 609         return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
 610 }
 611
 612 static int sunxi_mmc_getcd(struct udevice *dev)
 613 {
 614         struct mmc *mmc = mmc_get_mmc_dev(dev);
 615         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 616
 617         /* If polling, assume that the card is always present. */
 618         if ((mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE) ||
 619             (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL))
 620                 return 1;
 621
 622         if (dm_gpio_is_valid(&priv->cd_gpio)) {
 623                 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
 624
 625                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 626                         return !cd_state;
 627                 else
 628                         return cd_state;
 629         }
 630         return 1;
 631 }
 632
 633 static const struct dm_mmc_ops sunxi_mmc_ops = {
 634         .send_cmd       = sunxi_mmc_send_cmd,
 635         .set_ios        = sunxi_mmc_set_ios,
 636         .get_cd         = sunxi_mmc_getcd,
 637 };
 638
 639 static unsigned get_mclk_offset(void)
 640 {
 641         if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
 642                 return 0x410;
 643
 644         if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 645                 return 0x830;
 646
 647         return 0x88;
 648 };
 649
 650 static int sunxi_mmc_probe(struct udevice *dev)
 651 {
 652         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 653         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 654         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 655         struct reset_ctl_bulk reset_bulk;
 656         struct clk gate_clk;
 657         struct mmc_config *cfg = &plat->cfg;
 658         struct ofnode_phandle_args args;
 659         u32 *ccu_reg;
 660         int ret;
 661
 662         cfg->name = dev->name;
 663
 664         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 665         cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 666         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 667
 668         cfg->f_min = 400000;
 669         cfg->f_max = 52000000;
 670
 671         ret = mmc_of_parse(dev, cfg);
 672         if (ret)
 673                 return ret;
 674
 675         priv->reg = dev_read_addr_ptr(dev);
 676
 677         /* We don't have a sunxi clock driver so find the clock address here */
 678         ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
 679                                           1, &args);
 680         if (ret)
 681                 return ret;
 682         ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
 683
 684         priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
 685         priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
 686
 687         ret = clk_get_by_name(dev, "ahb", &gate_clk);
 688         if (!ret)
 689                 clk_enable(&gate_clk);
 690
 691         ret = reset_get_bulk(dev, &reset_bulk);
 692         if (!ret)
 693                 reset_deassert_bulk(&reset_bulk);
 694
 695         ret = mmc_set_mod_clk(priv, 24000000);
 696         if (ret)
 697                 return ret;
 698
 699         /* This GPIO is optional */
 700         if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 701                                   GPIOD_IS_IN)) {
 702                 int cd_pin = gpio_get_number(&priv->cd_gpio);
 703
 704                 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
 705         }
 706
 707         upriv->mmc = &plat->mmc;
 708
 709         /* Reset controller */
 710         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 711         udelay(1000);
 712
 713         return 0;
 714 }
 715
 716 static int sunxi_mmc_bind(struct udevice *dev)
 717 {
 718         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 719
 720         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 721 }
 722
 723 static const struct udevice_id sunxi_mmc_ids[] = {
 724         { .compatible = "allwinner,sun4i-a10-mmc" },
 725         { .compatible = "allwinner,sun5i-a13-mmc" },
 726         { .compatible = "allwinner,sun7i-a20-mmc" },
 727         { .compatible = "allwinner,sun8i-a83t-emmc" },
 728         { .compatible = "allwinner,sun9i-a80-mmc" },
 729         { .compatible = "allwinner,sun50i-a64-mmc" },
 730         { .compatible = "allwinner,sun50i-a64-emmc" },
 731         { .compatible = "allwinner,sun50i-h6-mmc" },
 732         { .compatible = "allwinner,sun50i-h6-emmc" },
 733         { .compatible = "allwinner,sun50i-a100-mmc" },
 734         { .compatible = "allwinner,sun50i-a100-emmc" },
 735         { /* sentinel */ }
 736 };
 737
 738 U_BOOT_DRIVER(sunxi_mmc_drv) = {
 739         .name           = "sunxi_mmc",
 740         .id             = UCLASS_MMC,
 741         .of_match       = sunxi_mmc_ids,
 742         .bind           = sunxi_mmc_bind,
 743         .probe          = sunxi_mmc_probe,
 744         .ops            = &sunxi_mmc_ops,
 745         .plat_auto      = sizeof(struct sunxi_mmc_plat),
 746         .priv_auto      = sizeof(struct sunxi_mmc_priv),
 747 };
 748 #endif