2 * (C) Copyright 2007-2011
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Aaron <leafy.myeh@allwinnertech.com>
6 * MMC driver for allwinner sunxi platform.
8 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/mmc.h>
20 #include <asm-generic/gpio.h>
22 struct sunxi_mmc_priv {
26 struct sunxi_mmc *reg;
27 struct mmc_config cfg;
30 /* support 4 mmc hosts */
31 struct sunxi_mmc_priv mmc_host[4];
33 static int sunxi_mmc_getcd_gpio(int sdc_no)
36 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
37 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
38 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
39 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
44 static int mmc_resource_init(int sdc_no)
46 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
47 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
50 debug("init mmc %d resource\n", sdc_no);
54 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
55 priv->mclkreg = &ccm->sd0_clk_cfg;
58 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
59 priv->mclkreg = &ccm->sd1_clk_cfg;
62 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
63 priv->mclkreg = &ccm->sd2_clk_cfg;
66 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
67 priv->mclkreg = &ccm->sd3_clk_cfg;
70 printf("Wrong mmc number %d\n", sdc_no);
73 priv->mmc_no = sdc_no;
75 cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
77 ret = gpio_request(cd_pin, "mmc_cd");
79 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
80 ret = gpio_direction_input(cd_pin);
87 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
89 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
92 pll = CCM_MMC_CTRL_OSCM24;
95 #ifdef CONFIG_MACH_SUN9I
96 pll = CCM_MMC_CTRL_PLL_PERIPH0;
97 pll_hz = clock_get_pll4_periph0();
99 pll = CCM_MMC_CTRL_PLL6;
100 pll_hz = clock_get_pll6();
115 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
120 /* determine delays */
124 } else if (hz <= 25000000) {
127 #ifdef CONFIG_MACH_SUN9I
128 } else if (hz <= 50000000) {
136 } else if (hz <= 50000000) {
146 writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
147 CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
148 CCM_MMC_CTRL_M(div), priv->mclkreg);
150 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
151 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
156 static int mmc_clk_io_on(int sdc_no)
158 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
159 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
161 debug("init mmc %d clock and io\n", sdc_no);
163 /* config ahb clock */
164 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
166 #ifdef CONFIG_SUNXI_GEN_SUN6I
168 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
170 #if defined(CONFIG_MACH_SUN9I)
171 /* sun9i has a mmc-common module, also set the gate and reset there */
172 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
173 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
176 return mmc_set_mod_clk(priv, 24000000);
179 static int mmc_update_clk(struct mmc *mmc)
181 struct sunxi_mmc_priv *priv = mmc->priv;
183 unsigned timeout_msecs = 2000;
185 cmd = SUNXI_MMC_CMD_START |
186 SUNXI_MMC_CMD_UPCLK_ONLY |
187 SUNXI_MMC_CMD_WAIT_PRE_OVER;
188 writel(cmd, &priv->reg->cmd);
189 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
190 if (!timeout_msecs--)
195 /* clock update sets various irq status bits, clear these */
196 writel(readl(&priv->reg->rint), &priv->reg->rint);
201 static int mmc_config_clock(struct mmc *mmc)
203 struct sunxi_mmc_priv *priv = mmc->priv;
204 unsigned rval = readl(&priv->reg->clkcr);
207 rval &= ~SUNXI_MMC_CLK_ENABLE;
208 writel(rval, &priv->reg->clkcr);
209 if (mmc_update_clk(mmc))
212 /* Set mod_clk to new rate */
213 if (mmc_set_mod_clk(priv, mmc->clock))
216 /* Clear internal divider */
217 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
218 writel(rval, &priv->reg->clkcr);
220 /* Re-enable Clock */
221 rval |= SUNXI_MMC_CLK_ENABLE;
222 writel(rval, &priv->reg->clkcr);
223 if (mmc_update_clk(mmc))
229 static int sunxi_mmc_set_ios(struct mmc *mmc)
231 struct sunxi_mmc_priv *priv = mmc->priv;
233 debug("set ios: bus_width: %x, clock: %d\n",
234 mmc->bus_width, mmc->clock);
236 /* Change clock first */
237 if (mmc->clock && mmc_config_clock(mmc) != 0) {
242 /* Change bus width */
243 if (mmc->bus_width == 8)
244 writel(0x2, &priv->reg->width);
245 else if (mmc->bus_width == 4)
246 writel(0x1, &priv->reg->width);
248 writel(0x0, &priv->reg->width);
253 static int sunxi_mmc_core_init(struct mmc *mmc)
255 struct sunxi_mmc_priv *priv = mmc->priv;
257 /* Reset controller */
258 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
264 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
266 struct sunxi_mmc_priv *priv = mmc->priv;
267 const int reading = !!(data->flags & MMC_DATA_READ);
268 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
269 SUNXI_MMC_STATUS_FIFO_FULL;
271 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
272 unsigned byte_cnt = data->blocksize * data->blocks;
273 unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
274 if (timeout_usecs < 2000000)
275 timeout_usecs = 2000000;
277 /* Always read / write data through the CPU */
278 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
280 for (i = 0; i < (byte_cnt >> 2); i++) {
281 while (readl(&priv->reg->status) & status_bit) {
282 if (!timeout_usecs--)
288 buff[i] = readl(&priv->reg->fifo);
290 writel(buff[i], &priv->reg->fifo);
296 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
297 unsigned int done_bit, const char *what)
299 struct sunxi_mmc_priv *priv = mmc->priv;
303 status = readl(&priv->reg->rint);
304 if (!timeout_msecs-- ||
305 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
306 debug("%s timeout %x\n", what,
307 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
311 } while (!(status & done_bit));
316 static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
317 struct mmc_data *data)
319 struct sunxi_mmc_priv *priv = mmc->priv;
320 unsigned int cmdval = SUNXI_MMC_CMD_START;
321 unsigned int timeout_msecs;
323 unsigned int status = 0;
324 unsigned int bytecnt = 0;
328 if (cmd->resp_type & MMC_RSP_BUSY)
329 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
330 if (cmd->cmdidx == 12)
334 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
335 if (cmd->resp_type & MMC_RSP_PRESENT)
336 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
337 if (cmd->resp_type & MMC_RSP_136)
338 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
339 if (cmd->resp_type & MMC_RSP_CRC)
340 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
343 if ((u32)(long)data->dest & 0x3) {
348 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
349 if (data->flags & MMC_DATA_WRITE)
350 cmdval |= SUNXI_MMC_CMD_WRITE;
351 if (data->blocks > 1)
352 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
353 writel(data->blocksize, &priv->reg->blksz);
354 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
357 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
358 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
359 writel(cmd->cmdarg, &priv->reg->arg);
362 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
365 * transfer data and check status
366 * STATREG[2] : FIFO empty
367 * STATREG[3] : FIFO full
372 bytecnt = data->blocksize * data->blocks;
373 debug("trans data %d bytes\n", bytecnt);
374 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
375 ret = mmc_trans_data_by_cpu(mmc, data);
377 error = readl(&priv->reg->rint) &
378 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
384 error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
390 debug("cacl timeout %x msec\n", timeout_msecs);
391 error = mmc_rint_wait(mmc, timeout_msecs,
393 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
394 SUNXI_MMC_RINT_DATA_OVER,
400 if (cmd->resp_type & MMC_RSP_BUSY) {
401 timeout_msecs = 2000;
403 status = readl(&priv->reg->status);
404 if (!timeout_msecs--) {
405 debug("busy timeout\n");
410 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
413 if (cmd->resp_type & MMC_RSP_136) {
414 cmd->response[0] = readl(&priv->reg->resp3);
415 cmd->response[1] = readl(&priv->reg->resp2);
416 cmd->response[2] = readl(&priv->reg->resp1);
417 cmd->response[3] = readl(&priv->reg->resp0);
418 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
419 cmd->response[3], cmd->response[2],
420 cmd->response[1], cmd->response[0]);
422 cmd->response[0] = readl(&priv->reg->resp0);
423 debug("mmc resp 0x%08x\n", cmd->response[0]);
427 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
430 writel(0xffffffff, &priv->reg->rint);
431 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
437 static int sunxi_mmc_getcd(struct mmc *mmc)
439 struct sunxi_mmc_priv *priv = mmc->priv;
442 cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
446 return !gpio_get_value(cd_pin);
449 static const struct mmc_ops sunxi_mmc_ops = {
450 .send_cmd = sunxi_mmc_send_cmd,
451 .set_ios = sunxi_mmc_set_ios,
452 .init = sunxi_mmc_core_init,
453 .getcd = sunxi_mmc_getcd,
456 struct mmc *sunxi_mmc_init(int sdc_no)
458 struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
460 memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_priv));
462 cfg->name = "SUNXI SD/MMC";
463 cfg->ops = &sunxi_mmc_ops;
465 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
466 cfg->host_caps = MMC_MODE_4BIT;
467 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
469 cfg->host_caps = MMC_MODE_8BIT;
471 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
472 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
475 cfg->f_max = 52000000;
477 if (mmc_resource_init(sdc_no) != 0)
480 mmc_clk_io_on(sdc_no);
482 return mmc_create(cfg, &mmc_host[sdc_no]);