drivers/mmc/sunxi_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2011
   4  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   5  * Aaron <leafy.myeh@allwinnertech.com>
   6  *
   7  * MMC driver for allwinner sunxi platform.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <clk.h>
  17 #include <reset.h>
  18 #include <asm/gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/cpu.h>
  22 #include <asm/arch/mmc.h>
  23 #include <linux/delay.h>
  24
  25 #ifndef CCM_MMC_CTRL_MODE_SEL_NEW
  26 #define CCM_MMC_CTRL_MODE_SEL_NEW       0
  27 #endif
  28
  29 struct sunxi_mmc_plat {
  30         struct mmc_config cfg;
  31         struct mmc mmc;
  32 };
  33
  34 struct sunxi_mmc_priv {
  35         unsigned mmc_no;
  36         uint32_t *mclkreg;
  37         unsigned fatal_err;
  38         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  39         struct sunxi_mmc *reg;
  40         struct mmc_config cfg;
  41 };
  42
  43 #if !CONFIG_IS_ENABLED(DM_MMC)
  44 /* support 4 mmc hosts */
  45 struct sunxi_mmc_priv mmc_host[4];
  46
  47 static int sunxi_mmc_getcd_gpio(int sdc_no)
  48 {
  49         switch (sdc_no) {
  50         case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  51         case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  52         case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  53         case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  54         }
  55         return -EINVAL;
  56 }
  57
  58 static int mmc_resource_init(int sdc_no)
  59 {
  60         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  61         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  62         int cd_pin, ret = 0;
  63
  64         debug("init mmc %d resource\n", sdc_no);
  65
  66         switch (sdc_no) {
  67         case 0:
  68                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  69                 priv->mclkreg = &ccm->sd0_clk_cfg;
  70                 break;
  71         case 1:
  72                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  73                 priv->mclkreg = &ccm->sd1_clk_cfg;
  74                 break;
  75         case 2:
  76                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  77                 priv->mclkreg = &ccm->sd2_clk_cfg;
  78                 break;
  79 #ifdef SUNXI_MMC3_BASE
  80         case 3:
  81                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  82                 priv->mclkreg = &ccm->sd3_clk_cfg;
  83                 break;
  84 #endif
  85         default:
  86                 printf("Wrong mmc number %d\n", sdc_no);
  87                 return -1;
  88         }
  89         priv->mmc_no = sdc_no;
  90
  91         cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  92         if (cd_pin >= 0) {
  93                 ret = gpio_request(cd_pin, "mmc_cd");
  94                 if (!ret) {
  95                         sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  96                         ret = gpio_direction_input(cd_pin);
  97                 }
  98         }
  99
 100         return ret;
 101 }
 102 #endif
 103
 104 /*
 105  * All A64 and later MMC controllers feature auto-calibration. This would
 106  * normally be detected via the compatible string, but we need something
 107  * which works in the SPL as well.
 108  */
 109 static bool sunxi_mmc_can_calibrate(void)
 110 {
 111         return IS_ENABLED(CONFIG_MACH_SUN50I) ||
 112                IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
 113                IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
 114                IS_ENABLED(CONFIG_MACH_SUN8I_R40);
 115 }
 116
 117 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 118 {
 119         unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
 120         bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
 121         u32 val = 0;
 122
 123         /* A83T support new mode only on eMMC */
 124         if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
 125                 new_mode = false;
 126
 127         if (hz <= 24000000) {
 128                 pll = CCM_MMC_CTRL_OSCM24;
 129                 pll_hz = 24000000;
 130         } else {
 131 #ifdef CONFIG_MACH_SUN9I
 132                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
 133                 pll_hz = clock_get_pll4_periph0();
 134 #else
 135                 /*
 136                  * SoCs since the A64 (H5, H6, H616) actually use the doubled
 137                  * rate of PLL6/PERIPH0 as an input clock, but compensate for
 138                  * that with a fixed post-divider of 2 in the mod clock.
 139                  * This cancels each other out, so for simplicity we just
 140                  * pretend it's always PLL6 without a post divider here.
 141                  */
 142                 pll = CCM_MMC_CTRL_PLL6;
 143                 pll_hz = clock_get_pll6();
 144 #endif
 145         }
 146
 147         div = pll_hz / hz;
 148         if (pll_hz % hz)
 149                 div++;
 150
 151         n = 0;
 152         while (div > 16) {
 153                 n++;
 154                 div = (div + 1) / 2;
 155         }
 156
 157         if (n > 3) {
 158                 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
 159                        hz);
 160                 return -1;
 161         }
 162
 163         /* determine delays */
 164         if (hz <= 400000) {
 165                 oclk_dly = 0;
 166                 sclk_dly = 0;
 167         } else if (hz <= 25000000) {
 168                 oclk_dly = 0;
 169                 sclk_dly = 5;
 170         } else {
 171                 if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
 172                         if (hz <= 52000000)
 173                                 oclk_dly = 5;
 174                         else
 175                                 oclk_dly = 2;
 176                 } else {
 177                         if (hz <= 52000000)
 178                                 oclk_dly = 3;
 179                         else
 180                                 oclk_dly = 1;
 181                 }
 182                 sclk_dly = 4;
 183         }
 184
 185         if (new_mode) {
 186                 val |= CCM_MMC_CTRL_MODE_SEL_NEW;
 187                 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 188         }
 189
 190         if (!sunxi_mmc_can_calibrate()) {
 191                 /*
 192                  * Use hardcoded delay values if controller doesn't support
 193                  * calibration
 194                  */
 195                 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 196                         CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
 197         }
 198
 199         writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
 200                CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
 201
 202         debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 203               priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
 204
 205         return 0;
 206 }
 207
 208 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
 209 {
 210         unsigned int cmd;
 211         unsigned timeout_msecs = 2000;
 212         unsigned long start = get_timer(0);
 213
 214         cmd = SUNXI_MMC_CMD_START |
 215               SUNXI_MMC_CMD_UPCLK_ONLY |
 216               SUNXI_MMC_CMD_WAIT_PRE_OVER;
 217
 218         writel(cmd, &priv->reg->cmd);
 219         while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
 220                 if (get_timer(start) > timeout_msecs)
 221                         return -1;
 222         }
 223
 224         /* clock update sets various irq status bits, clear these */
 225         writel(readl(&priv->reg->rint), &priv->reg->rint);
 226
 227         return 0;
 228 }
 229
 230 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
 231 {
 232         unsigned rval = readl(&priv->reg->clkcr);
 233
 234         /* Disable Clock */
 235         rval &= ~SUNXI_MMC_CLK_ENABLE;
 236         writel(rval, &priv->reg->clkcr);
 237         if (mmc_update_clk(priv))
 238                 return -1;
 239
 240         /* Set mod_clk to new rate */
 241         if (mmc_set_mod_clk(priv, mmc->clock))
 242                 return -1;
 243
 244         /* Clear internal divider */
 245         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 246         writel(rval, &priv->reg->clkcr);
 247
 248 #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
 249         /* A64 supports calibration of delays on MMC controller and we
 250          * have to set delay of zero before starting calibration.
 251          * Allwinner BSP driver sets a delay only in the case of
 252          * using HS400 which is not supported by mainline U-Boot or
 253          * Linux at the moment
 254          */
 255         if (sunxi_mmc_can_calibrate())
 256                 writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
 257 #endif
 258
 259         /* Re-enable Clock */
 260         rval |= SUNXI_MMC_CLK_ENABLE;
 261         writel(rval, &priv->reg->clkcr);
 262         if (mmc_update_clk(priv))
 263                 return -1;
 264
 265         return 0;
 266 }
 267
 268 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
 269                                     struct mmc *mmc)
 270 {
 271         debug("set ios: bus_width: %x, clock: %d\n",
 272               mmc->bus_width, mmc->clock);
 273
 274         /* Change clock first */
 275         if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
 276                 priv->fatal_err = 1;
 277                 return -EINVAL;
 278         }
 279
 280         /* Change bus width */
 281         if (mmc->bus_width == 8)
 282                 writel(0x2, &priv->reg->width);
 283         else if (mmc->bus_width == 4)
 284                 writel(0x1, &priv->reg->width);
 285         else
 286                 writel(0x0, &priv->reg->width);
 287
 288         return 0;
 289 }
 290
 291 #if !CONFIG_IS_ENABLED(DM_MMC)
 292 static int sunxi_mmc_core_init(struct mmc *mmc)
 293 {
 294         struct sunxi_mmc_priv *priv = mmc->priv;
 295
 296         /* Reset controller */
 297         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 298         udelay(1000);
 299
 300         return 0;
 301 }
 302 #endif
 303
 304 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 305                                  struct mmc_data *data)
 306 {
 307         const int reading = !!(data->flags & MMC_DATA_READ);
 308         const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
 309                                               SUNXI_MMC_STATUS_FIFO_FULL;
 310         unsigned i;
 311         unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 312         unsigned word_cnt = (data->blocksize * data->blocks) >> 2;
 313         unsigned timeout_msecs = word_cnt >> 6;
 314         uint32_t status;
 315         unsigned long  start;
 316
 317         if (timeout_msecs < 2000)
 318                 timeout_msecs = 2000;
 319
 320         /* Always read / write data through the CPU */
 321         setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 322
 323         start = get_timer(0);
 324
 325         for (i = 0; i < word_cnt;) {
 326                 unsigned int in_fifo;
 327
 328                 while ((status = readl(&priv->reg->status)) & status_bit) {
 329                         if (get_timer(start) > timeout_msecs)
 330                                 return -1;
 331                 }
 332
 333                 /*
 334                  * For writing we do not easily know the FIFO size, so have
 335                  * to check the FIFO status after every word written.
 336                  * TODO: For optimisation we could work out a minimum FIFO
 337                  * size across all SoCs, and use that together with the current
 338                  * fill level to write chunks of words.
 339                  */
 340                 if (!reading) {
 341                         writel(buff[i++], &priv->reg->fifo);
 342                         continue;
 343                 }
 344
 345                 /*
 346                  * The status register holds the current FIFO level, so we
 347                  * can be sure to collect as many words from the FIFO
 348                  * register without checking the status register after every
 349                  * read. That saves half of the costly MMIO reads, effectively
 350                  * doubling the read performance.
 351                  * Some SoCs (A20) report a level of 0 if the FIFO is
 352                  * completely full (value masked out?). Use a safe minimal
 353                  * FIFO size in this case.
 354                  */
 355                 in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
 356                 if (in_fifo == 0 && (status & SUNXI_MMC_STATUS_FIFO_FULL))
 357                         in_fifo = 32;
 358                 for (; in_fifo > 0; in_fifo--)
 359                         buff[i++] = readl_relaxed(&priv->reg->fifo);
 360                 dmb();
 361         }
 362
 363         return 0;
 364 }
 365
 366 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 367                          uint timeout_msecs, uint done_bit, const char *what)
 368 {
 369         unsigned int status;
 370         unsigned long start = get_timer(0);
 371
 372         do {
 373                 status = readl(&priv->reg->rint);
 374                 if ((get_timer(start) > timeout_msecs) ||
 375                     (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
 376                         debug("%s timeout %x\n", what,
 377                               status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
 378                         return -ETIMEDOUT;
 379                 }
 380         } while (!(status & done_bit));
 381
 382         return 0;
 383 }
 384
 385 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
 386                                      struct mmc *mmc, struct mmc_cmd *cmd,
 387                                      struct mmc_data *data)
 388 {
 389         unsigned int cmdval = SUNXI_MMC_CMD_START;
 390         unsigned int timeout_msecs;
 391         int error = 0;
 392         unsigned int status = 0;
 393         unsigned int bytecnt = 0;
 394
 395         if (priv->fatal_err)
 396                 return -1;
 397         if (cmd->resp_type & MMC_RSP_BUSY)
 398                 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
 399         if (cmd->cmdidx == 12)
 400                 return 0;
 401
 402         if (!cmd->cmdidx)
 403                 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 404         if (cmd->resp_type & MMC_RSP_PRESENT)
 405                 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 406         if (cmd->resp_type & MMC_RSP_136)
 407                 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 408         if (cmd->resp_type & MMC_RSP_CRC)
 409                 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 410
 411         if (data) {
 412                 if ((u32)(long)data->dest & 0x3) {
 413                         error = -1;
 414                         goto out;
 415                 }
 416
 417                 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 418                 if (data->flags & MMC_DATA_WRITE)
 419                         cmdval |= SUNXI_MMC_CMD_WRITE;
 420                 if (data->blocks > 1)
 421                         cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 422                 writel(data->blocksize, &priv->reg->blksz);
 423                 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
 424         }
 425
 426         debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
 427               cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 428         writel(cmd->cmdarg, &priv->reg->arg);
 429
 430         if (!data)
 431                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 432
 433         /*
 434          * transfer data and check status
 435          * STATREG[2] : FIFO empty
 436          * STATREG[3] : FIFO full
 437          */
 438         if (data) {
 439                 int ret = 0;
 440
 441                 bytecnt = data->blocksize * data->blocks;
 442                 debug("trans data %d bytes\n", bytecnt);
 443                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 444                 ret = mmc_trans_data_by_cpu(priv, mmc, data);
 445                 if (ret) {
 446                         error = readl(&priv->reg->rint) &
 447                                 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 448                         error = -ETIMEDOUT;
 449                         goto out;
 450                 }
 451         }
 452
 453         error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
 454                               "cmd");
 455         if (error)
 456                 goto out;
 457
 458         if (data) {
 459                 timeout_msecs = 120;
 460                 debug("cacl timeout %x msec\n", timeout_msecs);
 461                 error = mmc_rint_wait(priv, mmc, timeout_msecs,
 462                                       data->blocks > 1 ?
 463                                       SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
 464                                       SUNXI_MMC_RINT_DATA_OVER,
 465                                       "data");
 466                 if (error)
 467                         goto out;
 468         }
 469
 470         if (cmd->resp_type & MMC_RSP_BUSY) {
 471                 unsigned long start = get_timer(0);
 472                 timeout_msecs = 2000;
 473
 474                 do {
 475                         status = readl(&priv->reg->status);
 476                         if (get_timer(start) > timeout_msecs) {
 477                                 debug("busy timeout\n");
 478                                 error = -ETIMEDOUT;
 479                                 goto out;
 480                         }
 481                 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 482         }
 483
 484         if (cmd->resp_type & MMC_RSP_136) {
 485                 cmd->response[0] = readl(&priv->reg->resp3);
 486                 cmd->response[1] = readl(&priv->reg->resp2);
 487                 cmd->response[2] = readl(&priv->reg->resp1);
 488                 cmd->response[3] = readl(&priv->reg->resp0);
 489                 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
 490                       cmd->response[3], cmd->response[2],
 491                       cmd->response[1], cmd->response[0]);
 492         } else {
 493                 cmd->response[0] = readl(&priv->reg->resp0);
 494                 debug("mmc resp 0x%08x\n", cmd->response[0]);
 495         }
 496 out:
 497         if (error < 0) {
 498                 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 499                 mmc_update_clk(priv);
 500         }
 501         writel(0xffffffff, &priv->reg->rint);
 502         writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
 503                &priv->reg->gctrl);
 504
 505         return error;
 506 }
 507
 508 #if !CONFIG_IS_ENABLED(DM_MMC)
 509 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
 510 {
 511         struct sunxi_mmc_priv *priv = mmc->priv;
 512
 513         return sunxi_mmc_set_ios_common(priv, mmc);
 514 }
 515
 516 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
 517                                      struct mmc_data *data)
 518 {
 519         struct sunxi_mmc_priv *priv = mmc->priv;
 520
 521         return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
 522 }
 523
 524 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
 525 {
 526         struct sunxi_mmc_priv *priv = mmc->priv;
 527         int cd_pin;
 528
 529         cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
 530         if (cd_pin < 0)
 531                 return 1;
 532
 533         return !gpio_get_value(cd_pin);
 534 }
 535
 536 static const struct mmc_ops sunxi_mmc_ops = {
 537         .send_cmd       = sunxi_mmc_send_cmd_legacy,
 538         .set_ios        = sunxi_mmc_set_ios_legacy,
 539         .init           = sunxi_mmc_core_init,
 540         .getcd          = sunxi_mmc_getcd_legacy,
 541 };
 542
 543 struct mmc *sunxi_mmc_init(int sdc_no)
 544 {
 545         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 546         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
 547         struct mmc_config *cfg = &priv->cfg;
 548         int ret;
 549
 550         memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
 551
 552         cfg->name = "SUNXI SD/MMC";
 553         cfg->ops  = &sunxi_mmc_ops;
 554
 555         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 556         cfg->host_caps = MMC_MODE_4BIT;
 557
 558         if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) ||
 559             IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2))
 560                 cfg->host_caps = MMC_MODE_8BIT;
 561
 562         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 563         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 564
 565         cfg->f_min = 400000;
 566         cfg->f_max = 52000000;
 567
 568         if (mmc_resource_init(sdc_no) != 0)
 569                 return NULL;
 570
 571         /* config ahb clock */
 572         debug("init mmc %d clock and io\n", sdc_no);
 573 #if !defined(CONFIG_SUN50I_GEN_H6)
 574         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 575
 576 #ifdef CONFIG_SUNXI_GEN_SUN6I
 577         /* unassert reset */
 578         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 579 #endif
 580 #if defined(CONFIG_MACH_SUN9I)
 581         /* sun9i has a mmc-common module, also set the gate and reset there */
 582         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
 583                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
 584 #endif
 585 #else /* CONFIG_SUN50I_GEN_H6 */
 586         setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
 587         /* unassert reset */
 588         setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
 589 #endif
 590         ret = mmc_set_mod_clk(priv, 24000000);
 591         if (ret)
 592                 return NULL;
 593
 594         return mmc_create(cfg, priv);
 595 }
 596 #else
 597
 598 static int sunxi_mmc_set_ios(struct udevice *dev)
 599 {
 600         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 601         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 602
 603         return sunxi_mmc_set_ios_common(priv, &plat->mmc);
 604 }
 605
 606 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 607                               struct mmc_data *data)
 608 {
 609         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 610         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 611
 612         return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
 613 }
 614
 615 static int sunxi_mmc_getcd(struct udevice *dev)
 616 {
 617         struct mmc *mmc = mmc_get_mmc_dev(dev);
 618         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 619
 620         /* If polling, assume that the card is always present. */
 621         if ((mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE) ||
 622             (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL))
 623                 return 1;
 624
 625         if (dm_gpio_is_valid(&priv->cd_gpio)) {
 626                 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
 627
 628                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 629                         return !cd_state;
 630                 else
 631                         return cd_state;
 632         }
 633         return 1;
 634 }
 635
 636 static const struct dm_mmc_ops sunxi_mmc_ops = {
 637         .send_cmd       = sunxi_mmc_send_cmd,
 638         .set_ios        = sunxi_mmc_set_ios,
 639         .get_cd         = sunxi_mmc_getcd,
 640 };
 641
 642 static unsigned get_mclk_offset(void)
 643 {
 644         if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
 645                 return 0x410;
 646
 647         if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 648                 return 0x830;
 649
 650         return 0x88;
 651 };
 652
 653 static int sunxi_mmc_probe(struct udevice *dev)
 654 {
 655         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 656         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 657         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 658         struct reset_ctl_bulk reset_bulk;
 659         struct clk gate_clk;
 660         struct mmc_config *cfg = &plat->cfg;
 661         struct ofnode_phandle_args args;
 662         u32 *ccu_reg;
 663         int ret;
 664
 665         cfg->name = dev->name;
 666
 667         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 668         cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 669         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 670
 671         cfg->f_min = 400000;
 672         cfg->f_max = 52000000;
 673
 674         ret = mmc_of_parse(dev, cfg);
 675         if (ret)
 676                 return ret;
 677
 678         priv->reg = dev_read_addr_ptr(dev);
 679
 680         /* We don't have a sunxi clock driver so find the clock address here */
 681         ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
 682                                           1, &args);
 683         if (ret)
 684                 return ret;
 685         ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
 686
 687         priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
 688         priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
 689
 690         ret = clk_get_by_name(dev, "ahb", &gate_clk);
 691         if (!ret)
 692                 clk_enable(&gate_clk);
 693
 694         ret = reset_get_bulk(dev, &reset_bulk);
 695         if (!ret)
 696                 reset_deassert_bulk(&reset_bulk);
 697
 698         ret = mmc_set_mod_clk(priv, 24000000);
 699         if (ret)
 700                 return ret;
 701
 702         /* This GPIO is optional */
 703         if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 704                                   GPIOD_IS_IN)) {
 705                 int cd_pin = gpio_get_number(&priv->cd_gpio);
 706
 707                 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
 708         }
 709
 710         upriv->mmc = &plat->mmc;
 711
 712         /* Reset controller */
 713         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 714         udelay(1000);
 715
 716         return 0;
 717 }
 718
 719 static int sunxi_mmc_bind(struct udevice *dev)
 720 {
 721         struct sunxi_mmc_plat *plat = dev_get_plat(dev);
 722
 723         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 724 }
 725
 726 static const struct udevice_id sunxi_mmc_ids[] = {
 727         { .compatible = "allwinner,sun4i-a10-mmc" },
 728         { .compatible = "allwinner,sun5i-a13-mmc" },
 729         { .compatible = "allwinner,sun7i-a20-mmc" },
 730         { .compatible = "allwinner,sun8i-a83t-emmc" },
 731         { .compatible = "allwinner,sun9i-a80-mmc" },
 732         { .compatible = "allwinner,sun50i-a64-mmc" },
 733         { .compatible = "allwinner,sun50i-a64-emmc" },
 734         { .compatible = "allwinner,sun50i-h6-mmc" },
 735         { .compatible = "allwinner,sun50i-h6-emmc" },
 736         { .compatible = "allwinner,sun50i-a100-mmc" },
 737         { .compatible = "allwinner,sun50i-a100-emmc" },
 738         { /* sentinel */ }
 739 };
 740
 741 U_BOOT_DRIVER(sunxi_mmc_drv) = {
 742         .name           = "sunxi_mmc",
 743         .id             = UCLASS_MMC,
 744         .of_match       = sunxi_mmc_ids,
 745         .bind           = sunxi_mmc_bind,
 746         .probe          = sunxi_mmc_probe,
 747         .ops            = &sunxi_mmc_ops,
 748         .plat_auto      = sizeof(struct sunxi_mmc_plat),
 749         .priv_auto      = sizeof(struct sunxi_mmc_priv),
 750 };
 751 #endif