1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2011
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Aaron <leafy.myeh@allwinnertech.com>
7 * MMC driver for allwinner sunxi platform.
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/mmc.h>
20 #include <asm-generic/gpio.h>
22 struct sunxi_mmc_plat {
23 struct mmc_config cfg;
27 struct sunxi_mmc_priv {
31 struct gpio_desc cd_gpio; /* Change Detect GPIO */
32 int cd_inverted; /* Inverted Card Detect */
33 struct sunxi_mmc *reg;
34 struct mmc_config cfg;
37 #if !CONFIG_IS_ENABLED(DM_MMC)
38 /* support 4 mmc hosts */
39 struct sunxi_mmc_priv mmc_host[4];
41 static int sunxi_mmc_getcd_gpio(int sdc_no)
44 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
45 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
46 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
47 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
52 static int mmc_resource_init(int sdc_no)
54 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
55 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
58 debug("init mmc %d resource\n", sdc_no);
62 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
63 priv->mclkreg = &ccm->sd0_clk_cfg;
66 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
67 priv->mclkreg = &ccm->sd1_clk_cfg;
70 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
71 priv->mclkreg = &ccm->sd2_clk_cfg;
73 #ifdef SUNXI_MMC3_BASE
75 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
76 priv->mclkreg = &ccm->sd3_clk_cfg;
80 printf("Wrong mmc number %d\n", sdc_no);
83 priv->mmc_no = sdc_no;
85 cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
87 ret = gpio_request(cd_pin, "mmc_cd");
89 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
90 ret = gpio_direction_input(cd_pin);
98 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
100 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
101 bool new_mode = false;
104 if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
108 * The MMC clock has an extra /2 post-divider when operating in the new
114 if (hz <= 24000000) {
115 pll = CCM_MMC_CTRL_OSCM24;
118 #ifdef CONFIG_MACH_SUN9I
119 pll = CCM_MMC_CTRL_PLL_PERIPH0;
120 pll_hz = clock_get_pll4_periph0();
121 #elif defined(CONFIG_MACH_SUN50I_H6)
122 pll = CCM_MMC_CTRL_PLL6X2;
123 pll_hz = clock_get_pll6() * 2;
125 pll = CCM_MMC_CTRL_PLL6;
126 pll_hz = clock_get_pll6();
141 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
146 /* determine delays */
150 } else if (hz <= 25000000) {
153 #ifdef CONFIG_MACH_SUN9I
154 } else if (hz <= 52000000) {
162 } else if (hz <= 52000000) {
173 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
174 val = CCM_MMC_CTRL_MODE_SEL_NEW;
175 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
178 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
179 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
182 writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
183 CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
185 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
186 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
191 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
194 unsigned timeout_msecs = 2000;
195 unsigned long start = get_timer(0);
197 cmd = SUNXI_MMC_CMD_START |
198 SUNXI_MMC_CMD_UPCLK_ONLY |
199 SUNXI_MMC_CMD_WAIT_PRE_OVER;
201 writel(cmd, &priv->reg->cmd);
202 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
203 if (get_timer(start) > timeout_msecs)
207 /* clock update sets various irq status bits, clear these */
208 writel(readl(&priv->reg->rint), &priv->reg->rint);
213 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
215 unsigned rval = readl(&priv->reg->clkcr);
218 rval &= ~SUNXI_MMC_CLK_ENABLE;
219 writel(rval, &priv->reg->clkcr);
220 if (mmc_update_clk(priv))
223 /* Set mod_clk to new rate */
224 if (mmc_set_mod_clk(priv, mmc->clock))
227 /* Clear internal divider */
228 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
229 writel(rval, &priv->reg->clkcr);
231 /* Re-enable Clock */
232 rval |= SUNXI_MMC_CLK_ENABLE;
233 writel(rval, &priv->reg->clkcr);
234 if (mmc_update_clk(priv))
240 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
243 debug("set ios: bus_width: %x, clock: %d\n",
244 mmc->bus_width, mmc->clock);
246 /* Change clock first */
247 if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
252 /* Change bus width */
253 if (mmc->bus_width == 8)
254 writel(0x2, &priv->reg->width);
255 else if (mmc->bus_width == 4)
256 writel(0x1, &priv->reg->width);
258 writel(0x0, &priv->reg->width);
263 #if !CONFIG_IS_ENABLED(DM_MMC)
264 static int sunxi_mmc_core_init(struct mmc *mmc)
266 struct sunxi_mmc_priv *priv = mmc->priv;
268 /* Reset controller */
269 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
276 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
277 struct mmc_data *data)
279 const int reading = !!(data->flags & MMC_DATA_READ);
280 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
281 SUNXI_MMC_STATUS_FIFO_FULL;
283 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
284 unsigned byte_cnt = data->blocksize * data->blocks;
285 unsigned timeout_msecs = byte_cnt >> 8;
288 if (timeout_msecs < 2000)
289 timeout_msecs = 2000;
291 /* Always read / write data through the CPU */
292 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
294 start = get_timer(0);
296 for (i = 0; i < (byte_cnt >> 2); i++) {
297 while (readl(&priv->reg->status) & status_bit) {
298 if (get_timer(start) > timeout_msecs)
303 buff[i] = readl(&priv->reg->fifo);
305 writel(buff[i], &priv->reg->fifo);
311 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
312 uint timeout_msecs, uint done_bit, const char *what)
315 unsigned long start = get_timer(0);
318 status = readl(&priv->reg->rint);
319 if ((get_timer(start) > timeout_msecs) ||
320 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
321 debug("%s timeout %x\n", what,
322 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
325 } while (!(status & done_bit));
330 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
331 struct mmc *mmc, struct mmc_cmd *cmd,
332 struct mmc_data *data)
334 unsigned int cmdval = SUNXI_MMC_CMD_START;
335 unsigned int timeout_msecs;
337 unsigned int status = 0;
338 unsigned int bytecnt = 0;
342 if (cmd->resp_type & MMC_RSP_BUSY)
343 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
344 if (cmd->cmdidx == 12)
348 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
349 if (cmd->resp_type & MMC_RSP_PRESENT)
350 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
351 if (cmd->resp_type & MMC_RSP_136)
352 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
353 if (cmd->resp_type & MMC_RSP_CRC)
354 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
357 if ((u32)(long)data->dest & 0x3) {
362 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
363 if (data->flags & MMC_DATA_WRITE)
364 cmdval |= SUNXI_MMC_CMD_WRITE;
365 if (data->blocks > 1)
366 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
367 writel(data->blocksize, &priv->reg->blksz);
368 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
371 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
372 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
373 writel(cmd->cmdarg, &priv->reg->arg);
376 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
379 * transfer data and check status
380 * STATREG[2] : FIFO empty
381 * STATREG[3] : FIFO full
386 bytecnt = data->blocksize * data->blocks;
387 debug("trans data %d bytes\n", bytecnt);
388 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
389 ret = mmc_trans_data_by_cpu(priv, mmc, data);
391 error = readl(&priv->reg->rint) &
392 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
398 error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
405 debug("cacl timeout %x msec\n", timeout_msecs);
406 error = mmc_rint_wait(priv, mmc, timeout_msecs,
408 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
409 SUNXI_MMC_RINT_DATA_OVER,
415 if (cmd->resp_type & MMC_RSP_BUSY) {
416 unsigned long start = get_timer(0);
417 timeout_msecs = 2000;
420 status = readl(&priv->reg->status);
421 if (get_timer(start) > timeout_msecs) {
422 debug("busy timeout\n");
426 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
429 if (cmd->resp_type & MMC_RSP_136) {
430 cmd->response[0] = readl(&priv->reg->resp3);
431 cmd->response[1] = readl(&priv->reg->resp2);
432 cmd->response[2] = readl(&priv->reg->resp1);
433 cmd->response[3] = readl(&priv->reg->resp0);
434 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
435 cmd->response[3], cmd->response[2],
436 cmd->response[1], cmd->response[0]);
438 cmd->response[0] = readl(&priv->reg->resp0);
439 debug("mmc resp 0x%08x\n", cmd->response[0]);
443 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
444 mmc_update_clk(priv);
446 writel(0xffffffff, &priv->reg->rint);
447 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
453 #if !CONFIG_IS_ENABLED(DM_MMC)
454 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
456 struct sunxi_mmc_priv *priv = mmc->priv;
458 return sunxi_mmc_set_ios_common(priv, mmc);
461 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
462 struct mmc_data *data)
464 struct sunxi_mmc_priv *priv = mmc->priv;
466 return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
469 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
471 struct sunxi_mmc_priv *priv = mmc->priv;
474 cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
478 return !gpio_get_value(cd_pin);
481 static const struct mmc_ops sunxi_mmc_ops = {
482 .send_cmd = sunxi_mmc_send_cmd_legacy,
483 .set_ios = sunxi_mmc_set_ios_legacy,
484 .init = sunxi_mmc_core_init,
485 .getcd = sunxi_mmc_getcd_legacy,
488 struct mmc *sunxi_mmc_init(int sdc_no)
490 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
491 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
492 struct mmc_config *cfg = &priv->cfg;
495 memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
497 cfg->name = "SUNXI SD/MMC";
498 cfg->ops = &sunxi_mmc_ops;
500 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
501 cfg->host_caps = MMC_MODE_4BIT;
502 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
504 cfg->host_caps = MMC_MODE_8BIT;
506 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
507 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
510 cfg->f_max = 52000000;
512 if (mmc_resource_init(sdc_no) != 0)
515 /* config ahb clock */
516 debug("init mmc %d clock and io\n", sdc_no);
517 #if !defined(CONFIG_MACH_SUN50I_H6)
518 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
520 #ifdef CONFIG_SUNXI_GEN_SUN6I
522 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
524 #if defined(CONFIG_MACH_SUN9I)
525 /* sun9i has a mmc-common module, also set the gate and reset there */
526 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
527 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
529 #else /* CONFIG_MACH_SUN50I_H6 */
530 setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
532 setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
534 ret = mmc_set_mod_clk(priv, 24000000);
538 return mmc_create(cfg, priv);
542 static int sunxi_mmc_set_ios(struct udevice *dev)
544 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
545 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
547 return sunxi_mmc_set_ios_common(priv, &plat->mmc);
550 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
551 struct mmc_data *data)
553 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
554 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
556 return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
559 static int sunxi_mmc_getcd(struct udevice *dev)
561 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
563 if (dm_gpio_is_valid(&priv->cd_gpio)) {
564 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
566 return cd_state ^ priv->cd_inverted;
571 static const struct dm_mmc_ops sunxi_mmc_ops = {
572 .send_cmd = sunxi_mmc_send_cmd,
573 .set_ios = sunxi_mmc_set_ios,
574 .get_cd = sunxi_mmc_getcd,
577 static int sunxi_mmc_probe(struct udevice *dev)
579 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
580 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
581 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
582 struct mmc_config *cfg = &plat->cfg;
583 struct ofnode_phandle_args args;
587 cfg->name = dev->name;
588 bus_width = dev_read_u32_default(dev, "bus-width", 1);
590 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
593 cfg->host_caps |= MMC_MODE_8BIT;
595 cfg->host_caps |= MMC_MODE_4BIT;
596 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
597 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
600 cfg->f_max = 52000000;
602 priv->reg = (void *)dev_read_addr(dev);
604 /* We don't have a sunxi clock driver so find the clock address here */
605 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
609 priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
611 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
615 gate_reg = (u32 *)ofnode_get_addr(args.node);
616 setbits_le32(gate_reg, 1 << args.args[0]);
617 priv->mmc_no = args.args[0] - 8;
619 ret = mmc_set_mod_clk(priv, 24000000);
623 /* This GPIO is optional */
624 if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
626 int cd_pin = gpio_get_number(&priv->cd_gpio);
628 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
631 /* Check if card detect is inverted */
632 priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
634 upriv->mmc = &plat->mmc;
636 /* Reset controller */
637 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
643 static int sunxi_mmc_bind(struct udevice *dev)
645 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
647 return mmc_bind(dev, &plat->mmc, &plat->cfg);
650 static const struct udevice_id sunxi_mmc_ids[] = {
651 { .compatible = "allwinner,sun4i-a10-mmc" },
652 { .compatible = "allwinner,sun5i-a13-mmc" },
653 { .compatible = "allwinner,sun7i-a20-mmc" },
657 U_BOOT_DRIVER(sunxi_mmc_drv) = {
660 .of_match = sunxi_mmc_ids,
661 .bind = sunxi_mmc_bind,
662 .probe = sunxi_mmc_probe,
663 .ops = &sunxi_mmc_ops,
664 .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
665 .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),