1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
11 #include <linux/libfdt.h>
16 #include <linux/iopoll.h>
19 struct stm32_sdmmc2_plat {
20 struct mmc_config cfg;
24 struct stm32_sdmmc2_priv {
27 struct reset_ctl reset_ctl;
28 struct gpio_desc cd_gpio;
33 struct stm32_sdmmc2_ctx {
40 /* SDMMC REGISTERS OFFSET */
41 #define SDMMC_POWER 0x00 /* SDMMC power control */
42 #define SDMMC_CLKCR 0x04 /* SDMMC clock control */
43 #define SDMMC_ARG 0x08 /* SDMMC argument */
44 #define SDMMC_CMD 0x0C /* SDMMC command */
45 #define SDMMC_RESP1 0x14 /* SDMMC response 1 */
46 #define SDMMC_RESP2 0x18 /* SDMMC response 2 */
47 #define SDMMC_RESP3 0x1C /* SDMMC response 3 */
48 #define SDMMC_RESP4 0x20 /* SDMMC response 4 */
49 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
50 #define SDMMC_DLEN 0x28 /* SDMMC data length */
51 #define SDMMC_DCTRL 0x2C /* SDMMC data control */
52 #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
53 #define SDMMC_STA 0x34 /* SDMMC status */
54 #define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
55 #define SDMMC_MASK 0x3C /* SDMMC mask */
56 #define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
57 #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
59 /* SDMMC_POWER register */
60 #define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0)
61 #define SDMMC_POWER_PWRCTRL_OFF 0
62 #define SDMMC_POWER_PWRCTRL_CYCLE 2
63 #define SDMMC_POWER_PWRCTRL_ON 3
64 #define SDMMC_POWER_VSWITCH BIT(2)
65 #define SDMMC_POWER_VSWITCHEN BIT(3)
66 #define SDMMC_POWER_DIRPOL BIT(4)
68 /* SDMMC_CLKCR register */
69 #define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
70 #define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV
71 #define SDMMC_CLKCR_PWRSAV BIT(12)
72 #define SDMMC_CLKCR_WIDBUS_4 BIT(14)
73 #define SDMMC_CLKCR_WIDBUS_8 BIT(15)
74 #define SDMMC_CLKCR_NEGEDGE BIT(16)
75 #define SDMMC_CLKCR_HWFC_EN BIT(17)
76 #define SDMMC_CLKCR_DDR BIT(18)
77 #define SDMMC_CLKCR_BUSSPEED BIT(19)
78 #define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
79 #define SDMMC_CLKCR_SELCLKRX_CK 0
80 #define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20)
81 #define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21)
83 /* SDMMC_CMD register */
84 #define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
85 #define SDMMC_CMD_CMDTRANS BIT(6)
86 #define SDMMC_CMD_CMDSTOP BIT(7)
87 #define SDMMC_CMD_WAITRESP GENMASK(9, 8)
88 #define SDMMC_CMD_WAITRESP_0 BIT(8)
89 #define SDMMC_CMD_WAITRESP_1 BIT(9)
90 #define SDMMC_CMD_WAITINT BIT(10)
91 #define SDMMC_CMD_WAITPEND BIT(11)
92 #define SDMMC_CMD_CPSMEN BIT(12)
93 #define SDMMC_CMD_DTHOLD BIT(13)
94 #define SDMMC_CMD_BOOTMODE BIT(14)
95 #define SDMMC_CMD_BOOTEN BIT(15)
96 #define SDMMC_CMD_CMDSUSPEND BIT(16)
98 /* SDMMC_DCTRL register */
99 #define SDMMC_DCTRL_DTEN BIT(0)
100 #define SDMMC_DCTRL_DTDIR BIT(1)
101 #define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
102 #define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
103 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4
104 #define SDMMC_DCTRL_RWSTART BIT(8)
105 #define SDMMC_DCTRL_RWSTOP BIT(9)
106 #define SDMMC_DCTRL_RWMOD BIT(10)
107 #define SDMMC_DCTRL_SDMMCEN BIT(11)
108 #define SDMMC_DCTRL_BOOTACKEN BIT(12)
109 #define SDMMC_DCTRL_FIFORST BIT(13)
111 /* SDMMC_STA register */
112 #define SDMMC_STA_CCRCFAIL BIT(0)
113 #define SDMMC_STA_DCRCFAIL BIT(1)
114 #define SDMMC_STA_CTIMEOUT BIT(2)
115 #define SDMMC_STA_DTIMEOUT BIT(3)
116 #define SDMMC_STA_TXUNDERR BIT(4)
117 #define SDMMC_STA_RXOVERR BIT(5)
118 #define SDMMC_STA_CMDREND BIT(6)
119 #define SDMMC_STA_CMDSENT BIT(7)
120 #define SDMMC_STA_DATAEND BIT(8)
121 #define SDMMC_STA_DHOLD BIT(9)
122 #define SDMMC_STA_DBCKEND BIT(10)
123 #define SDMMC_STA_DABORT BIT(11)
124 #define SDMMC_STA_DPSMACT BIT(12)
125 #define SDMMC_STA_CPSMACT BIT(13)
126 #define SDMMC_STA_TXFIFOHE BIT(14)
127 #define SDMMC_STA_RXFIFOHF BIT(15)
128 #define SDMMC_STA_TXFIFOF BIT(16)
129 #define SDMMC_STA_RXFIFOF BIT(17)
130 #define SDMMC_STA_TXFIFOE BIT(18)
131 #define SDMMC_STA_RXFIFOE BIT(19)
132 #define SDMMC_STA_BUSYD0 BIT(20)
133 #define SDMMC_STA_BUSYD0END BIT(21)
134 #define SDMMC_STA_SDMMCIT BIT(22)
135 #define SDMMC_STA_ACKFAIL BIT(23)
136 #define SDMMC_STA_ACKTIMEOUT BIT(24)
137 #define SDMMC_STA_VSWEND BIT(25)
138 #define SDMMC_STA_CKSTOP BIT(26)
139 #define SDMMC_STA_IDMATE BIT(27)
140 #define SDMMC_STA_IDMABTC BIT(28)
142 /* SDMMC_ICR register */
143 #define SDMMC_ICR_CCRCFAILC BIT(0)
144 #define SDMMC_ICR_DCRCFAILC BIT(1)
145 #define SDMMC_ICR_CTIMEOUTC BIT(2)
146 #define SDMMC_ICR_DTIMEOUTC BIT(3)
147 #define SDMMC_ICR_TXUNDERRC BIT(4)
148 #define SDMMC_ICR_RXOVERRC BIT(5)
149 #define SDMMC_ICR_CMDRENDC BIT(6)
150 #define SDMMC_ICR_CMDSENTC BIT(7)
151 #define SDMMC_ICR_DATAENDC BIT(8)
152 #define SDMMC_ICR_DHOLDC BIT(9)
153 #define SDMMC_ICR_DBCKENDC BIT(10)
154 #define SDMMC_ICR_DABORTC BIT(11)
155 #define SDMMC_ICR_BUSYD0ENDC BIT(21)
156 #define SDMMC_ICR_SDMMCITC BIT(22)
157 #define SDMMC_ICR_ACKFAILC BIT(23)
158 #define SDMMC_ICR_ACKTIMEOUTC BIT(24)
159 #define SDMMC_ICR_VSWENDC BIT(25)
160 #define SDMMC_ICR_CKSTOPC BIT(26)
161 #define SDMMC_ICR_IDMATEC BIT(27)
162 #define SDMMC_ICR_IDMABTCC BIT(28)
163 #define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
165 /* SDMMC_MASK register */
166 #define SDMMC_MASK_CCRCFAILIE BIT(0)
167 #define SDMMC_MASK_DCRCFAILIE BIT(1)
168 #define SDMMC_MASK_CTIMEOUTIE BIT(2)
169 #define SDMMC_MASK_DTIMEOUTIE BIT(3)
170 #define SDMMC_MASK_TXUNDERRIE BIT(4)
171 #define SDMMC_MASK_RXOVERRIE BIT(5)
172 #define SDMMC_MASK_CMDRENDIE BIT(6)
173 #define SDMMC_MASK_CMDSENTIE BIT(7)
174 #define SDMMC_MASK_DATAENDIE BIT(8)
175 #define SDMMC_MASK_DHOLDIE BIT(9)
176 #define SDMMC_MASK_DBCKENDIE BIT(10)
177 #define SDMMC_MASK_DABORTIE BIT(11)
178 #define SDMMC_MASK_TXFIFOHEIE BIT(14)
179 #define SDMMC_MASK_RXFIFOHFIE BIT(15)
180 #define SDMMC_MASK_RXFIFOFIE BIT(17)
181 #define SDMMC_MASK_TXFIFOEIE BIT(18)
182 #define SDMMC_MASK_BUSYD0ENDIE BIT(21)
183 #define SDMMC_MASK_SDMMCITIE BIT(22)
184 #define SDMMC_MASK_ACKFAILIE BIT(23)
185 #define SDMMC_MASK_ACKTIMEOUTIE BIT(24)
186 #define SDMMC_MASK_VSWENDIE BIT(25)
187 #define SDMMC_MASK_CKSTOPIE BIT(26)
188 #define SDMMC_MASK_IDMABTCIE BIT(28)
190 /* SDMMC_IDMACTRL register */
191 #define SDMMC_IDMACTRL_IDMAEN BIT(0)
193 #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
194 #define SDMMC_BUSYD0END_TIMEOUT_US 2000000
196 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
197 struct mmc_data *data,
198 struct stm32_sdmmc2_ctx *ctx)
200 u32 data_ctrl, idmabase0;
202 /* Configure the SDMMC DPSM (Data Path State Machine) */
203 data_ctrl = (__ilog2(data->blocksize) <<
204 SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
205 SDMMC_DCTRL_DBLOCKSIZE;
207 if (data->flags & MMC_DATA_READ) {
208 data_ctrl |= SDMMC_DCTRL_DTDIR;
209 idmabase0 = (u32)data->dest;
211 idmabase0 = (u32)data->src;
214 /* Set the SDMMC DataLength value */
215 writel(ctx->data_length, priv->base + SDMMC_DLEN);
217 /* Write to SDMMC DCTRL */
218 writel(data_ctrl, priv->base + SDMMC_DCTRL);
221 ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
222 ctx->cache_end = roundup(idmabase0 + ctx->data_length,
226 * Flush data cache before DMA start (clean and invalidate)
227 * Clean also needed for read
228 * Avoid issue on buffer not cached-aligned
230 flush_dcache_range(ctx->cache_start, ctx->cache_end);
232 /* Enable internal DMA */
233 writel(idmabase0, priv->base + SDMMC_IDMABASE0);
234 writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
237 static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
238 struct mmc_cmd *cmd, u32 cmd_param,
239 struct stm32_sdmmc2_ctx *ctx)
243 if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
244 writel(0, priv->base + SDMMC_CMD);
246 cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
247 if (cmd->resp_type & MMC_RSP_PRESENT) {
248 if (cmd->resp_type & MMC_RSP_136)
249 cmd_param |= SDMMC_CMD_WAITRESP;
250 else if (cmd->resp_type & MMC_RSP_CRC)
251 cmd_param |= SDMMC_CMD_WAITRESP_0;
253 cmd_param |= SDMMC_CMD_WAITRESP_1;
257 * SDMMC_DTIME must be set in two case:
258 * - on data transfert.
260 * If not done or too short, the dtimeout flag occurs and DPSM stays
261 * enabled/busy and waits for abort (stop transmission cmd).
262 * Next data command is not possible whereas DPSM is activated.
264 if (ctx->data_length) {
265 timeout = SDMMC_CMD_TIMEOUT;
267 writel(0, priv->base + SDMMC_DCTRL);
269 if (cmd->resp_type & MMC_RSP_BUSY)
270 timeout = SDMMC_CMD_TIMEOUT;
273 /* Set the SDMMC Data TimeOut value */
274 writel(timeout, priv->base + SDMMC_DTIMER);
277 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
279 /* Set SDMMC argument value */
280 writel(cmd->cmdarg, priv->base + SDMMC_ARG);
282 /* Set SDMMC command parameters */
283 writel(cmd_param, priv->base + SDMMC_CMD);
286 static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
288 struct stm32_sdmmc2_ctx *ctx)
290 u32 mask = SDMMC_STA_CTIMEOUT;
294 if (cmd->resp_type & MMC_RSP_PRESENT) {
295 mask |= SDMMC_STA_CMDREND;
296 if (cmd->resp_type & MMC_RSP_CRC)
297 mask |= SDMMC_STA_CCRCFAIL;
299 mask |= SDMMC_STA_CMDSENT;
302 /* Polling status register */
303 ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
307 debug("%s: timeout reading SDMMC_STA register\n", __func__);
308 ctx->dpsm_abort = true;
313 if (status & SDMMC_STA_CTIMEOUT) {
314 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
315 __func__, status, cmd->cmdidx);
316 ctx->dpsm_abort = true;
320 if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
321 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
322 __func__, status, cmd->cmdidx);
323 ctx->dpsm_abort = true;
327 if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
328 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
329 if (cmd->resp_type & MMC_RSP_136) {
330 cmd->response[1] = readl(priv->base + SDMMC_RESP2);
331 cmd->response[2] = readl(priv->base + SDMMC_RESP3);
332 cmd->response[3] = readl(priv->base + SDMMC_RESP4);
335 /* Wait for BUSYD0END flag if busy status is detected */
336 if (cmd->resp_type & MMC_RSP_BUSY &&
337 status & SDMMC_STA_BUSYD0) {
338 mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
340 /* Polling status register */
341 ret = readl_poll_timeout(priv->base + SDMMC_STA,
342 status, status & mask,
343 SDMMC_BUSYD0END_TIMEOUT_US);
346 debug("%s: timeout reading SDMMC_STA\n",
348 ctx->dpsm_abort = true;
352 if (status & SDMMC_STA_DTIMEOUT) {
353 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
355 ctx->dpsm_abort = true;
364 static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
366 struct mmc_data *data,
367 struct stm32_sdmmc2_ctx *ctx)
369 u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
370 SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
373 if (data->flags & MMC_DATA_READ)
374 mask |= SDMMC_STA_RXOVERR;
376 mask |= SDMMC_STA_TXUNDERR;
378 status = readl(priv->base + SDMMC_STA);
379 while (!(status & mask))
380 status = readl(priv->base + SDMMC_STA);
383 * Need invalidate the dcache again to avoid any
384 * cache-refill during the DMA operations (pre-fetching)
386 if (data->flags & MMC_DATA_READ)
387 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
389 if (status & SDMMC_STA_DCRCFAIL) {
390 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
391 __func__, status, cmd->cmdidx);
392 if (readl(priv->base + SDMMC_DCOUNT))
393 ctx->dpsm_abort = true;
397 if (status & SDMMC_STA_DTIMEOUT) {
398 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
399 __func__, status, cmd->cmdidx);
400 ctx->dpsm_abort = true;
404 if (status & SDMMC_STA_TXUNDERR) {
405 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
406 __func__, status, cmd->cmdidx);
407 ctx->dpsm_abort = true;
411 if (status & SDMMC_STA_RXOVERR) {
412 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
413 __func__, status, cmd->cmdidx);
414 ctx->dpsm_abort = true;
418 if (status & SDMMC_STA_IDMATE) {
419 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
420 __func__, status, cmd->cmdidx);
421 ctx->dpsm_abort = true;
428 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
429 struct mmc_data *data)
431 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
432 struct stm32_sdmmc2_ctx ctx;
433 u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
440 ctx.dpsm_abort = false;
443 ctx.data_length = data->blocks * data->blocksize;
444 stm32_sdmmc2_start_data(priv, data, &ctx);
447 stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
449 debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
450 __func__, cmd->cmdidx,
451 data ? ctx.data_length : 0, (unsigned int)data);
453 ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
456 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
459 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
461 writel(0x0, priv->base + SDMMC_IDMACTRL);
464 * To stop Data Path State Machine, a stop_transmission command
465 * shall be send on cmd or data errors.
467 if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
468 struct mmc_cmd stop_cmd;
470 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
472 stop_cmd.resp_type = MMC_RSP_R1b;
474 debug("%s: send STOP command to abort dpsm treatments\n",
479 stm32_sdmmc2_start_cmd(priv, &stop_cmd,
480 SDMMC_CMD_CMDSTOP, &ctx);
481 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
483 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
486 if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
487 printf("%s: cmd %d failed, retrying ...\n",
488 __func__, cmd->cmdidx);
493 debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
499 * Reset the SDMMC with the RCC.SDMMCxRST register bit.
500 * This will reset the SDMMC to the reset state and the CPSM and DPSM
501 * to the Idle state. SDMMC is disabled, Signals Hiz.
503 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
506 reset_assert(&priv->reset_ctl);
508 reset_deassert(&priv->reset_ctl);
510 /* init the needed SDMMC register after reset */
511 writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
515 * Set the SDMMC in power-cycle state.
516 * This will make that the SDMMC_D[7:0],
517 * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
518 * supplied through the signal lines.
520 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
522 if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
523 SDMMC_POWER_PWRCTRL_CYCLE)
526 stm32_sdmmc2_reset(priv);
530 * set the SDMMC state Power-on: the card is clocked
531 * manage the SDMMC state control:
532 * Reset => Power-Cycle => Power-Off => Power
533 * PWRCTRL=10 PWCTRL=00 PWCTRL=11
535 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
538 readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK;
540 if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
543 /* warning: same PWRCTRL value after reset and for power-off state
544 * it is the reset state here = the only managed by the driver
546 if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
547 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
548 priv->base + SDMMC_POWER);
552 * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
553 * switch to Power-Off state: SDMCC disable, signals drive 1
555 writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
556 priv->base + SDMMC_POWER);
558 /* After the 1ms delay set the SDMMC to power-on */
560 writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
561 priv->base + SDMMC_POWER);
563 /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
566 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
567 static int stm32_sdmmc2_set_ios(struct udevice *dev)
569 struct mmc *mmc = mmc_get_mmc_dev(dev);
570 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
571 u32 desired = mmc->clock;
572 u32 sys_clock = clk_get_rate(&priv->clk);
575 debug("%s: bus_with = %d, clock = %d\n", __func__,
576 mmc->bus_width, mmc->clock);
578 if (mmc->clk_disable)
579 stm32_sdmmc2_pwrcycle(priv);
581 stm32_sdmmc2_pwron(priv);
584 * clk_div = 0 => command and data generated on SDMMCCLK falling edge
585 * clk_div > 0 and NEGEDGE = 0 => command and data generated on
586 * SDMMCCLK rising edge
587 * clk_div > 0 and NEGEDGE = 1 => command and data generated on
588 * SDMMCCLK falling edge
590 if (desired && ((sys_clock > desired) ||
591 IS_RISING_EDGE(priv->clk_reg_msk))) {
592 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
593 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
594 clk = SDMMC_CLKCR_CLKDIV_MAX;
597 if (mmc->bus_width == 4)
598 clk |= SDMMC_CLKCR_WIDBUS_4;
599 if (mmc->bus_width == 8)
600 clk |= SDMMC_CLKCR_WIDBUS_8;
602 writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
603 priv->base + SDMMC_CLKCR);
608 static int stm32_sdmmc2_getcd(struct udevice *dev)
610 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
612 debug("stm32_sdmmc2_getcd called\n");
614 if (dm_gpio_is_valid(&priv->cd_gpio))
615 return dm_gpio_get_value(&priv->cd_gpio);
620 static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
622 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
624 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
625 priv->base + SDMMC_POWER);
630 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
631 .send_cmd = stm32_sdmmc2_send_cmd,
632 .set_ios = stm32_sdmmc2_set_ios,
633 .get_cd = stm32_sdmmc2_getcd,
634 .host_power_cycle = stm32_sdmmc2_host_power_cycle,
637 static int stm32_sdmmc2_probe(struct udevice *dev)
639 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
640 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
641 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
642 struct mmc_config *cfg = &plat->cfg;
645 priv->base = dev_read_addr(dev);
646 if (priv->base == FDT_ADDR_T_NONE)
649 if (dev_read_bool(dev, "st,neg-edge"))
650 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
651 if (dev_read_bool(dev, "st,sig-dir"))
652 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
653 if (dev_read_bool(dev, "st,use-ckin"))
654 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
656 ret = clk_get_by_index(dev, 0, &priv->clk);
660 ret = clk_enable(&priv->clk);
664 ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
668 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
672 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
673 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
674 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
675 cfg->name = "STM32 SDMMC2";
678 if (cfg->f_max > 25000000)
679 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
681 switch (dev_read_u32_default(dev, "bus-width", 1)) {
683 cfg->host_caps |= MMC_MODE_8BIT;
686 cfg->host_caps |= MMC_MODE_4BIT;
691 pr_err("invalid \"bus-width\" property, force to 1\n");
694 upriv->mmc = &plat->mmc;
697 stm32_sdmmc2_reset(priv);
701 clk_disable(&priv->clk);
703 clk_free(&priv->clk);
708 static int stm32_sdmmc_bind(struct udevice *dev)
710 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
712 return mmc_bind(dev, &plat->mmc, &plat->cfg);
715 static const struct udevice_id stm32_sdmmc2_ids[] = {
716 { .compatible = "st,stm32-sdmmc2" },
720 U_BOOT_DRIVER(stm32_sdmmc2) = {
721 .name = "stm32_sdmmc2",
723 .of_match = stm32_sdmmc2_ids,
724 .ops = &stm32_sdmmc2_ops,
725 .probe = stm32_sdmmc2_probe,
726 .bind = stm32_sdmmc_bind,
727 .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
728 .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),