drivers/mmc/stm32_sdmmc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <linux/libfdt.h>
  12 #include <mmc.h>
  13 #include <reset.h>
  14 #include <asm/io.h>
  15 #include <asm/gpio.h>
  16 #include <linux/iopoll.h>
  17
  18 struct stm32_sdmmc2_plat {
  19         struct mmc_config cfg;
  20         struct mmc mmc;
  21 };
  22
  23 struct stm32_sdmmc2_priv {
  24         fdt_addr_t base;
  25         struct clk clk;
  26         struct reset_ctl reset_ctl;
  27         struct gpio_desc cd_gpio;
  28         u32 clk_reg_msk;
  29         u32 pwr_reg_msk;
  30 };
  31
  32 struct stm32_sdmmc2_ctx {
  33         u32 cache_start;
  34         u32 cache_end;
  35         u32 data_length;
  36         bool dpsm_abort;
  37 };
  38
  39 /* SDMMC REGISTERS OFFSET */
  40 #define SDMMC_POWER             0x00    /* SDMMC power control             */
  41 #define SDMMC_CLKCR             0x04    /* SDMMC clock control             */
  42 #define SDMMC_ARG               0x08    /* SDMMC argument                  */
  43 #define SDMMC_CMD               0x0C    /* SDMMC command                   */
  44 #define SDMMC_RESP1             0x14    /* SDMMC response 1                */
  45 #define SDMMC_RESP2             0x18    /* SDMMC response 2                */
  46 #define SDMMC_RESP3             0x1C    /* SDMMC response 3                */
  47 #define SDMMC_RESP4             0x20    /* SDMMC response 4                */
  48 #define SDMMC_DTIMER            0x24    /* SDMMC data timer                */
  49 #define SDMMC_DLEN              0x28    /* SDMMC data length               */
  50 #define SDMMC_DCTRL             0x2C    /* SDMMC data control              */
  51 #define SDMMC_DCOUNT            0x30    /* SDMMC data counter              */
  52 #define SDMMC_STA               0x34    /* SDMMC status                    */
  53 #define SDMMC_ICR               0x38    /* SDMMC interrupt clear           */
  54 #define SDMMC_MASK              0x3C    /* SDMMC mask                      */
  55 #define SDMMC_IDMACTRL          0x50    /* SDMMC DMA control               */
  56 #define SDMMC_IDMABASE0         0x58    /* SDMMC DMA buffer 0 base address */
  57
  58 /* SDMMC_POWER register */
  59 #define SDMMC_POWER_PWRCTRL_MASK        GENMASK(1, 0)
  60 #define SDMMC_POWER_PWRCTRL_OFF         0
  61 #define SDMMC_POWER_PWRCTRL_CYCLE       2
  62 #define SDMMC_POWER_PWRCTRL_ON          3
  63 #define SDMMC_POWER_VSWITCH             BIT(2)
  64 #define SDMMC_POWER_VSWITCHEN           BIT(3)
  65 #define SDMMC_POWER_DIRPOL              BIT(4)
  66
  67 /* SDMMC_CLKCR register */
  68 #define SDMMC_CLKCR_CLKDIV              GENMASK(9, 0)
  69 #define SDMMC_CLKCR_CLKDIV_MAX          SDMMC_CLKCR_CLKDIV
  70 #define SDMMC_CLKCR_PWRSAV              BIT(12)
  71 #define SDMMC_CLKCR_WIDBUS_4            BIT(14)
  72 #define SDMMC_CLKCR_WIDBUS_8            BIT(15)
  73 #define SDMMC_CLKCR_NEGEDGE             BIT(16)
  74 #define SDMMC_CLKCR_HWFC_EN             BIT(17)
  75 #define SDMMC_CLKCR_DDR                 BIT(18)
  76 #define SDMMC_CLKCR_BUSSPEED            BIT(19)
  77 #define SDMMC_CLKCR_SELCLKRX_MASK       GENMASK(21, 20)
  78 #define SDMMC_CLKCR_SELCLKRX_CK         0
  79 #define SDMMC_CLKCR_SELCLKRX_CKIN       BIT(20)
  80 #define SDMMC_CLKCR_SELCLKRX_FBCK       BIT(21)
  81
  82 /* SDMMC_CMD register */
  83 #define SDMMC_CMD_CMDINDEX              GENMASK(5, 0)
  84 #define SDMMC_CMD_CMDTRANS              BIT(6)
  85 #define SDMMC_CMD_CMDSTOP               BIT(7)
  86 #define SDMMC_CMD_WAITRESP              GENMASK(9, 8)
  87 #define SDMMC_CMD_WAITRESP_0            BIT(8)
  88 #define SDMMC_CMD_WAITRESP_1            BIT(9)
  89 #define SDMMC_CMD_WAITINT               BIT(10)
  90 #define SDMMC_CMD_WAITPEND              BIT(11)
  91 #define SDMMC_CMD_CPSMEN                BIT(12)
  92 #define SDMMC_CMD_DTHOLD                BIT(13)
  93 #define SDMMC_CMD_BOOTMODE              BIT(14)
  94 #define SDMMC_CMD_BOOTEN                BIT(15)
  95 #define SDMMC_CMD_CMDSUSPEND            BIT(16)
  96
  97 /* SDMMC_DCTRL register */
  98 #define SDMMC_DCTRL_DTEN                BIT(0)
  99 #define SDMMC_DCTRL_DTDIR               BIT(1)
 100 #define SDMMC_DCTRL_DTMODE              GENMASK(3, 2)
 101 #define SDMMC_DCTRL_DBLOCKSIZE          GENMASK(7, 4)
 102 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT    4
 103 #define SDMMC_DCTRL_RWSTART             BIT(8)
 104 #define SDMMC_DCTRL_RWSTOP              BIT(9)
 105 #define SDMMC_DCTRL_RWMOD               BIT(10)
 106 #define SDMMC_DCTRL_SDMMCEN             BIT(11)
 107 #define SDMMC_DCTRL_BOOTACKEN           BIT(12)
 108 #define SDMMC_DCTRL_FIFORST             BIT(13)
 109
 110 /* SDMMC_STA register */
 111 #define SDMMC_STA_CCRCFAIL              BIT(0)
 112 #define SDMMC_STA_DCRCFAIL              BIT(1)
 113 #define SDMMC_STA_CTIMEOUT              BIT(2)
 114 #define SDMMC_STA_DTIMEOUT              BIT(3)
 115 #define SDMMC_STA_TXUNDERR              BIT(4)
 116 #define SDMMC_STA_RXOVERR               BIT(5)
 117 #define SDMMC_STA_CMDREND               BIT(6)
 118 #define SDMMC_STA_CMDSENT               BIT(7)
 119 #define SDMMC_STA_DATAEND               BIT(8)
 120 #define SDMMC_STA_DHOLD                 BIT(9)
 121 #define SDMMC_STA_DBCKEND               BIT(10)
 122 #define SDMMC_STA_DABORT                BIT(11)
 123 #define SDMMC_STA_DPSMACT               BIT(12)
 124 #define SDMMC_STA_CPSMACT               BIT(13)
 125 #define SDMMC_STA_TXFIFOHE              BIT(14)
 126 #define SDMMC_STA_RXFIFOHF              BIT(15)
 127 #define SDMMC_STA_TXFIFOF               BIT(16)
 128 #define SDMMC_STA_RXFIFOF               BIT(17)
 129 #define SDMMC_STA_TXFIFOE               BIT(18)
 130 #define SDMMC_STA_RXFIFOE               BIT(19)
 131 #define SDMMC_STA_BUSYD0                BIT(20)
 132 #define SDMMC_STA_BUSYD0END             BIT(21)
 133 #define SDMMC_STA_SDMMCIT               BIT(22)
 134 #define SDMMC_STA_ACKFAIL               BIT(23)
 135 #define SDMMC_STA_ACKTIMEOUT            BIT(24)
 136 #define SDMMC_STA_VSWEND                BIT(25)
 137 #define SDMMC_STA_CKSTOP                BIT(26)
 138 #define SDMMC_STA_IDMATE                BIT(27)
 139 #define SDMMC_STA_IDMABTC               BIT(28)
 140
 141 /* SDMMC_ICR register */
 142 #define SDMMC_ICR_CCRCFAILC             BIT(0)
 143 #define SDMMC_ICR_DCRCFAILC             BIT(1)
 144 #define SDMMC_ICR_CTIMEOUTC             BIT(2)
 145 #define SDMMC_ICR_DTIMEOUTC             BIT(3)
 146 #define SDMMC_ICR_TXUNDERRC             BIT(4)
 147 #define SDMMC_ICR_RXOVERRC              BIT(5)
 148 #define SDMMC_ICR_CMDRENDC              BIT(6)
 149 #define SDMMC_ICR_CMDSENTC              BIT(7)
 150 #define SDMMC_ICR_DATAENDC              BIT(8)
 151 #define SDMMC_ICR_DHOLDC                BIT(9)
 152 #define SDMMC_ICR_DBCKENDC              BIT(10)
 153 #define SDMMC_ICR_DABORTC               BIT(11)
 154 #define SDMMC_ICR_BUSYD0ENDC            BIT(21)
 155 #define SDMMC_ICR_SDMMCITC              BIT(22)
 156 #define SDMMC_ICR_ACKFAILC              BIT(23)
 157 #define SDMMC_ICR_ACKTIMEOUTC           BIT(24)
 158 #define SDMMC_ICR_VSWENDC               BIT(25)
 159 #define SDMMC_ICR_CKSTOPC               BIT(26)
 160 #define SDMMC_ICR_IDMATEC               BIT(27)
 161 #define SDMMC_ICR_IDMABTCC              BIT(28)
 162 #define SDMMC_ICR_STATIC_FLAGS          ((GENMASK(28, 21)) | (GENMASK(11, 0)))
 163
 164 /* SDMMC_MASK register */
 165 #define SDMMC_MASK_CCRCFAILIE           BIT(0)
 166 #define SDMMC_MASK_DCRCFAILIE           BIT(1)
 167 #define SDMMC_MASK_CTIMEOUTIE           BIT(2)
 168 #define SDMMC_MASK_DTIMEOUTIE           BIT(3)
 169 #define SDMMC_MASK_TXUNDERRIE           BIT(4)
 170 #define SDMMC_MASK_RXOVERRIE            BIT(5)
 171 #define SDMMC_MASK_CMDRENDIE            BIT(6)
 172 #define SDMMC_MASK_CMDSENTIE            BIT(7)
 173 #define SDMMC_MASK_DATAENDIE            BIT(8)
 174 #define SDMMC_MASK_DHOLDIE              BIT(9)
 175 #define SDMMC_MASK_DBCKENDIE            BIT(10)
 176 #define SDMMC_MASK_DABORTIE             BIT(11)
 177 #define SDMMC_MASK_TXFIFOHEIE           BIT(14)
 178 #define SDMMC_MASK_RXFIFOHFIE           BIT(15)
 179 #define SDMMC_MASK_RXFIFOFIE            BIT(17)
 180 #define SDMMC_MASK_TXFIFOEIE            BIT(18)
 181 #define SDMMC_MASK_BUSYD0ENDIE          BIT(21)
 182 #define SDMMC_MASK_SDMMCITIE            BIT(22)
 183 #define SDMMC_MASK_ACKFAILIE            BIT(23)
 184 #define SDMMC_MASK_ACKTIMEOUTIE         BIT(24)
 185 #define SDMMC_MASK_VSWENDIE             BIT(25)
 186 #define SDMMC_MASK_CKSTOPIE             BIT(26)
 187 #define SDMMC_MASK_IDMABTCIE            BIT(28)
 188
 189 /* SDMMC_IDMACTRL register */
 190 #define SDMMC_IDMACTRL_IDMAEN           BIT(0)
 191
 192 #define SDMMC_CMD_TIMEOUT               0xFFFFFFFF
 193 #define SDMMC_BUSYD0END_TIMEOUT_US      1000000
 194
 195 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
 196                                     struct mmc_data *data,
 197                                     struct stm32_sdmmc2_ctx *ctx)
 198 {
 199         u32 data_ctrl, idmabase0;
 200
 201         /* Configure the SDMMC DPSM (Data Path State Machine) */
 202         data_ctrl = (__ilog2(data->blocksize) <<
 203                      SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
 204                     SDMMC_DCTRL_DBLOCKSIZE;
 205
 206         if (data->flags & MMC_DATA_READ) {
 207                 data_ctrl |= SDMMC_DCTRL_DTDIR;
 208                 idmabase0 = (u32)data->dest;
 209         } else {
 210                 idmabase0 = (u32)data->src;
 211         }
 212
 213         /* Set the SDMMC DataLength value */
 214         writel(ctx->data_length, priv->base + SDMMC_DLEN);
 215
 216         /* Write to SDMMC DCTRL */
 217         writel(data_ctrl, priv->base + SDMMC_DCTRL);
 218
 219         /* Cache align */
 220         ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
 221         ctx->cache_end = roundup(idmabase0 + ctx->data_length,
 222                                  ARCH_DMA_MINALIGN);
 223
 224         /*
 225          * Flush data cache before DMA start (clean and invalidate)
 226          * Clean also needed for read
 227          * Avoid issue on buffer not cached-aligned
 228          */
 229         flush_dcache_range(ctx->cache_start, ctx->cache_end);
 230
 231         /* Enable internal DMA */
 232         writel(idmabase0, priv->base + SDMMC_IDMABASE0);
 233         writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
 234 }
 235
 236 static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
 237                                    struct mmc_cmd *cmd, u32 cmd_param,
 238                                    struct stm32_sdmmc2_ctx *ctx)
 239 {
 240         u32 timeout = 0;
 241
 242         if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
 243                 writel(0, priv->base + SDMMC_CMD);
 244
 245         cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
 246         if (cmd->resp_type & MMC_RSP_PRESENT) {
 247                 if (cmd->resp_type & MMC_RSP_136)
 248                         cmd_param |= SDMMC_CMD_WAITRESP;
 249                 else if (cmd->resp_type & MMC_RSP_CRC)
 250                         cmd_param |= SDMMC_CMD_WAITRESP_0;
 251                 else
 252                         cmd_param |= SDMMC_CMD_WAITRESP_1;
 253         }
 254
 255         /*
 256          * SDMMC_DTIME must be set in two case:
 257          * - on data transfert.
 258          * - on busy request.
 259          * If not done or too short, the dtimeout flag occurs and DPSM stays
 260          * enabled/busy and waits for abort (stop transmission cmd).
 261          * Next data command is not possible whereas DPSM is activated.
 262          */
 263         if (ctx->data_length) {
 264                 timeout = SDMMC_CMD_TIMEOUT;
 265         } else {
 266                 writel(0, priv->base + SDMMC_DCTRL);
 267
 268                 if (cmd->resp_type & MMC_RSP_BUSY)
 269                         timeout = SDMMC_CMD_TIMEOUT;
 270         }
 271
 272         /* Set the SDMMC Data TimeOut value */
 273         writel(timeout, priv->base + SDMMC_DTIMER);
 274
 275         /* Clear flags */
 276         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 277
 278         /* Set SDMMC argument value */
 279         writel(cmd->cmdarg, priv->base + SDMMC_ARG);
 280
 281         /* Set SDMMC command parameters */
 282         writel(cmd_param, priv->base + SDMMC_CMD);
 283 }
 284
 285 static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
 286                                 struct mmc_cmd *cmd,
 287                                 struct stm32_sdmmc2_ctx *ctx)
 288 {
 289         u32 mask = SDMMC_STA_CTIMEOUT;
 290         u32 status;
 291         int ret;
 292
 293         if (cmd->resp_type & MMC_RSP_PRESENT) {
 294                 mask |= SDMMC_STA_CMDREND;
 295                 if (cmd->resp_type & MMC_RSP_CRC)
 296                         mask |= SDMMC_STA_CCRCFAIL;
 297         } else {
 298                 mask |= SDMMC_STA_CMDSENT;
 299         }
 300
 301         /* Polling status register */
 302         ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
 303                                  10000);
 304
 305         if (ret < 0) {
 306                 debug("%s: timeout reading SDMMC_STA register\n", __func__);
 307                 ctx->dpsm_abort = true;
 308                 return ret;
 309         }
 310
 311         /* Check status */
 312         if (status & SDMMC_STA_CTIMEOUT) {
 313                 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
 314                       __func__, status, cmd->cmdidx);
 315                 ctx->dpsm_abort = true;
 316                 return -ETIMEDOUT;
 317         }
 318
 319         if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
 320                 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
 321                       __func__, status, cmd->cmdidx);
 322                 ctx->dpsm_abort = true;
 323                 return -EILSEQ;
 324         }
 325
 326         if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
 327                 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
 328                 if (cmd->resp_type & MMC_RSP_136) {
 329                         cmd->response[1] = readl(priv->base + SDMMC_RESP2);
 330                         cmd->response[2] = readl(priv->base + SDMMC_RESP3);
 331                         cmd->response[3] = readl(priv->base + SDMMC_RESP4);
 332                 }
 333
 334                 /* Wait for BUSYD0END flag if busy status is detected */
 335                 if (cmd->resp_type & MMC_RSP_BUSY &&
 336                     status & SDMMC_STA_BUSYD0) {
 337                         mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
 338
 339                         /* Polling status register */
 340                         ret = readl_poll_timeout(priv->base + SDMMC_STA,
 341                                                  status, status & mask,
 342                                                  SDMMC_BUSYD0END_TIMEOUT_US);
 343
 344                         if (ret < 0) {
 345                                 debug("%s: timeout reading SDMMC_STA\n",
 346                                       __func__);
 347                                 ctx->dpsm_abort = true;
 348                                 return ret;
 349                         }
 350
 351                         if (status & SDMMC_STA_DTIMEOUT) {
 352                                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
 353                                       __func__, status);
 354                                 ctx->dpsm_abort = true;
 355                                 return -ETIMEDOUT;
 356                         }
 357                 }
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
 364                                  struct mmc_cmd *cmd,
 365                                  struct mmc_data *data,
 366                                  struct stm32_sdmmc2_ctx *ctx)
 367 {
 368         u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 369                    SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 370         u32 status;
 371
 372         if (data->flags & MMC_DATA_READ)
 373                 mask |= SDMMC_STA_RXOVERR;
 374         else
 375                 mask |= SDMMC_STA_TXUNDERR;
 376
 377         status = readl(priv->base + SDMMC_STA);
 378         while (!(status & mask))
 379                 status = readl(priv->base + SDMMC_STA);
 380
 381         /*
 382          * Need invalidate the dcache again to avoid any
 383          * cache-refill during the DMA operations (pre-fetching)
 384          */
 385         if (data->flags & MMC_DATA_READ)
 386                 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
 387
 388         if (status & SDMMC_STA_DCRCFAIL) {
 389                 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
 390                       __func__, status, cmd->cmdidx);
 391                 if (readl(priv->base + SDMMC_DCOUNT))
 392                         ctx->dpsm_abort = true;
 393                 return -EILSEQ;
 394         }
 395
 396         if (status & SDMMC_STA_DTIMEOUT) {
 397                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
 398                       __func__, status, cmd->cmdidx);
 399                 ctx->dpsm_abort = true;
 400                 return -ETIMEDOUT;
 401         }
 402
 403         if (status & SDMMC_STA_TXUNDERR) {
 404                 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
 405                       __func__, status, cmd->cmdidx);
 406                 ctx->dpsm_abort = true;
 407                 return -EIO;
 408         }
 409
 410         if (status & SDMMC_STA_RXOVERR) {
 411                 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
 412                       __func__, status, cmd->cmdidx);
 413                 ctx->dpsm_abort = true;
 414                 return -EIO;
 415         }
 416
 417         if (status & SDMMC_STA_IDMATE) {
 418                 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
 419                       __func__, status, cmd->cmdidx);
 420                 ctx->dpsm_abort = true;
 421                 return -EIO;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 428                                  struct mmc_data *data)
 429 {
 430         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 431         struct stm32_sdmmc2_ctx ctx;
 432         u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
 433         int ret, retry = 3;
 434
 435 retry_cmd:
 436         ctx.data_length = 0;
 437         ctx.dpsm_abort = false;
 438
 439         if (data) {
 440                 ctx.data_length = data->blocks * data->blocksize;
 441                 stm32_sdmmc2_start_data(priv, data, &ctx);
 442         }
 443
 444         stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
 445
 446         debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
 447               __func__, cmd->cmdidx,
 448               data ? ctx.data_length : 0, (unsigned int)data);
 449
 450         ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
 451
 452         if (data && !ret)
 453                 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
 454
 455         /* Clear flags */
 456         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 457         if (data)
 458                 writel(0x0, priv->base + SDMMC_IDMACTRL);
 459
 460         /*
 461          * To stop Data Path State Machine, a stop_transmission command
 462          * shall be send on cmd or data errors.
 463          */
 464         if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
 465                 struct mmc_cmd stop_cmd;
 466
 467                 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 468                 stop_cmd.cmdarg = 0;
 469                 stop_cmd.resp_type = MMC_RSP_R1b;
 470
 471                 debug("%s: send STOP command to abort dpsm treatments\n",
 472                       __func__);
 473
 474                 ctx.data_length = 0;
 475
 476                 stm32_sdmmc2_start_cmd(priv, &stop_cmd,
 477                                        SDMMC_CMD_CMDSTOP, &ctx);
 478                 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
 479
 480                 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 481         }
 482
 483         if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
 484                 printf("%s: cmd %d failed, retrying ...\n",
 485                        __func__, cmd->cmdidx);
 486                 retry--;
 487                 goto retry_cmd;
 488         }
 489
 490         debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
 491
 492         return ret;
 493 }
 494
 495 /*
 496  * Reset the SDMMC with the RCC.SDMMCxRST register bit.
 497  * This will reset the SDMMC to the reset state and the CPSM and DPSM
 498  * to the Idle state. SDMMC is disabled, Signals Hiz.
 499  */
 500 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
 501 {
 502         /* Reset */
 503         reset_assert(&priv->reset_ctl);
 504         udelay(2);
 505         reset_deassert(&priv->reset_ctl);
 506
 507         /* init the needed SDMMC register after reset */
 508         writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
 509 }
 510
 511 /*
 512  * Set the SDMMC in power-cycle state.
 513  * This will make that the SDMMC_D[7:0],
 514  * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
 515  * supplied through the signal lines.
 516  */
 517 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
 518 {
 519         if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
 520             SDMMC_POWER_PWRCTRL_CYCLE)
 521                 return;
 522
 523         stm32_sdmmc2_reset(priv);
 524         writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 525                priv->base + SDMMC_POWER);
 526 }
 527
 528 /*
 529  * set the SDMMC state Power-on: the card is clocked
 530  * manage the SDMMC state control:
 531  * Reset => Power-Cycle => Power-Off => Power
 532  *    PWRCTRL=10     PWCTRL=00    PWCTRL=11
 533  */
 534 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
 535 {
 536         u32 pwrctrl =
 537                 readl(priv->base + SDMMC_POWER) &  SDMMC_POWER_PWRCTRL_MASK;
 538
 539         if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
 540                 return;
 541
 542         /* warning: same PWRCTRL value after reset and for power-off state
 543          * it is the reset state here = the only managed by the driver
 544          */
 545         if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
 546                 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 547                        priv->base + SDMMC_POWER);
 548         }
 549
 550         /*
 551          * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
 552          * switch to Power-Off state: SDMCC disable, signals drive 1
 553          */
 554         writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
 555                priv->base + SDMMC_POWER);
 556
 557         /* After the 1ms delay set the SDMMC to power-on */
 558         mdelay(1);
 559         writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
 560                priv->base + SDMMC_POWER);
 561
 562         /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
 563 }
 564
 565 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
 566 static int stm32_sdmmc2_set_ios(struct udevice *dev)
 567 {
 568         struct mmc *mmc = mmc_get_mmc_dev(dev);
 569         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 570         u32 desired = mmc->clock;
 571         u32 sys_clock = clk_get_rate(&priv->clk);
 572         u32 clk = 0;
 573
 574         debug("%s: bus_with = %d, clock = %d\n", __func__,
 575               mmc->bus_width, mmc->clock);
 576
 577         if (mmc->clk_disable)
 578                 stm32_sdmmc2_pwrcycle(priv);
 579         else
 580                 stm32_sdmmc2_pwron(priv);
 581
 582         /*
 583          * clk_div = 0 => command and data generated on SDMMCCLK falling edge
 584          * clk_div > 0 and NEGEDGE = 0 => command and data generated on
 585          * SDMMCCLK rising edge
 586          * clk_div > 0 and NEGEDGE = 1 => command and data generated on
 587          * SDMMCCLK falling edge
 588          */
 589         if (desired && ((sys_clock > desired) ||
 590                         IS_RISING_EDGE(priv->clk_reg_msk))) {
 591                 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
 592                 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
 593                         clk = SDMMC_CLKCR_CLKDIV_MAX;
 594         }
 595
 596         if (mmc->bus_width == 4)
 597                 clk |= SDMMC_CLKCR_WIDBUS_4;
 598         if (mmc->bus_width == 8)
 599                 clk |= SDMMC_CLKCR_WIDBUS_8;
 600
 601         writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
 602                priv->base + SDMMC_CLKCR);
 603
 604         return 0;
 605 }
 606
 607 static int stm32_sdmmc2_getcd(struct udevice *dev)
 608 {
 609         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 610
 611         debug("stm32_sdmmc2_getcd called\n");
 612
 613         if (dm_gpio_is_valid(&priv->cd_gpio))
 614                 return dm_gpio_get_value(&priv->cd_gpio);
 615
 616         return 1;
 617 }
 618
 619 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
 620         .send_cmd = stm32_sdmmc2_send_cmd,
 621         .set_ios = stm32_sdmmc2_set_ios,
 622         .get_cd = stm32_sdmmc2_getcd,
 623 };
 624
 625 static int stm32_sdmmc2_probe(struct udevice *dev)
 626 {
 627         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 628         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 629         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 630         struct mmc_config *cfg = &plat->cfg;
 631         int ret;
 632
 633         priv->base = dev_read_addr(dev);
 634         if (priv->base == FDT_ADDR_T_NONE)
 635                 return -EINVAL;
 636
 637         if (dev_read_bool(dev, "st,neg-edge"))
 638                 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
 639         if (dev_read_bool(dev, "st,sig-dir"))
 640                 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
 641         if (dev_read_bool(dev, "st,use-ckin"))
 642                 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
 643
 644         ret = clk_get_by_index(dev, 0, &priv->clk);
 645         if (ret)
 646                 return ret;
 647
 648         ret = clk_enable(&priv->clk);
 649         if (ret)
 650                 goto clk_free;
 651
 652         ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
 653         if (ret)
 654                 goto clk_disable;
 655
 656         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 657                              GPIOD_IS_IN);
 658
 659         cfg->f_min = 400000;
 660         cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
 661         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 662         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 663         cfg->name = "STM32 SDMMC2";
 664
 665         cfg->host_caps = 0;
 666         if (cfg->f_max > 25000000)
 667                 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 668
 669         switch (dev_read_u32_default(dev, "bus-width", 1)) {
 670         case 8:
 671                 cfg->host_caps |= MMC_MODE_8BIT;
 672                 /* fall through */
 673         case 4:
 674                 cfg->host_caps |= MMC_MODE_4BIT;
 675                 break;
 676         case 1:
 677                 break;
 678         default:
 679                 pr_err("invalid \"bus-width\" property, force to 1\n");
 680         }
 681
 682         upriv->mmc = &plat->mmc;
 683
 684         /* SDMMC init */
 685         stm32_sdmmc2_reset(priv);
 686         return 0;
 687
 688 clk_disable:
 689         clk_disable(&priv->clk);
 690 clk_free:
 691         clk_free(&priv->clk);
 692
 693         return ret;
 694 }
 695
 696 static int stm32_sdmmc_bind(struct udevice *dev)
 697 {
 698         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 699
 700         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 701 }
 702
 703 static const struct udevice_id stm32_sdmmc2_ids[] = {
 704         { .compatible = "st,stm32-sdmmc2" },
 705         { }
 706 };
 707
 708 U_BOOT_DRIVER(stm32_sdmmc2) = {
 709         .name = "stm32_sdmmc2",
 710         .id = UCLASS_MMC,
 711         .of_match = stm32_sdmmc2_ids,
 712         .ops = &stm32_sdmmc2_ops,
 713         .probe = stm32_sdmmc2_probe,
 714         .bind = stm32_sdmmc_bind,
 715         .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
 716         .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
 717 };