drivers/mmc/stm32_sdmmc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
   5  */
   6
   7 #define LOG_CATEGORY UCLASS_MMC
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <fdtdec.h>
  14 #include <log.h>
  15 #include <malloc.h>
  16 #include <asm/bitops.h>
  17 #include <asm/cache.h>
  18 #include <dm/device_compat.h>
  19 #include <dm/pinctrl.h>
  20 #include <linux/bitops.h>
  21 #include <linux/delay.h>
  22 #include <linux/libfdt.h>
  23 #include <mmc.h>
  24 #include <reset.h>
  25 #include <asm/io.h>
  26 #include <asm/gpio.h>
  27 #include <linux/iopoll.h>
  28 #include <watchdog.h>
  29
  30 struct stm32_sdmmc2_plat {
  31         struct mmc_config cfg;
  32         struct mmc mmc;
  33 };
  34
  35 struct stm32_sdmmc2_priv {
  36         fdt_addr_t base;
  37         struct clk clk;
  38         struct reset_ctl reset_ctl;
  39         struct gpio_desc cd_gpio;
  40         u32 clk_reg_msk;
  41         u32 pwr_reg_msk;
  42 };
  43
  44 struct stm32_sdmmc2_ctx {
  45         u32 cache_start;
  46         u32 cache_end;
  47         u32 data_length;
  48         bool dpsm_abort;
  49 };
  50
  51 /* SDMMC REGISTERS OFFSET */
  52 #define SDMMC_POWER             0x00    /* SDMMC power control             */
  53 #define SDMMC_CLKCR             0x04    /* SDMMC clock control             */
  54 #define SDMMC_ARG               0x08    /* SDMMC argument                  */
  55 #define SDMMC_CMD               0x0C    /* SDMMC command                   */
  56 #define SDMMC_RESP1             0x14    /* SDMMC response 1                */
  57 #define SDMMC_RESP2             0x18    /* SDMMC response 2                */
  58 #define SDMMC_RESP3             0x1C    /* SDMMC response 3                */
  59 #define SDMMC_RESP4             0x20    /* SDMMC response 4                */
  60 #define SDMMC_DTIMER            0x24    /* SDMMC data timer                */
  61 #define SDMMC_DLEN              0x28    /* SDMMC data length               */
  62 #define SDMMC_DCTRL             0x2C    /* SDMMC data control              */
  63 #define SDMMC_DCOUNT            0x30    /* SDMMC data counter              */
  64 #define SDMMC_STA               0x34    /* SDMMC status                    */
  65 #define SDMMC_ICR               0x38    /* SDMMC interrupt clear           */
  66 #define SDMMC_MASK              0x3C    /* SDMMC mask                      */
  67 #define SDMMC_IDMACTRL          0x50    /* SDMMC DMA control               */
  68 #define SDMMC_IDMABASE0         0x58    /* SDMMC DMA buffer 0 base address */
  69
  70 /* SDMMC_POWER register */
  71 #define SDMMC_POWER_PWRCTRL_MASK        GENMASK(1, 0)
  72 #define SDMMC_POWER_PWRCTRL_OFF         0
  73 #define SDMMC_POWER_PWRCTRL_CYCLE       2
  74 #define SDMMC_POWER_PWRCTRL_ON          3
  75 #define SDMMC_POWER_VSWITCH             BIT(2)
  76 #define SDMMC_POWER_VSWITCHEN           BIT(3)
  77 #define SDMMC_POWER_DIRPOL              BIT(4)
  78
  79 /* SDMMC_CLKCR register */
  80 #define SDMMC_CLKCR_CLKDIV              GENMASK(9, 0)
  81 #define SDMMC_CLKCR_CLKDIV_MAX          SDMMC_CLKCR_CLKDIV
  82 #define SDMMC_CLKCR_PWRSAV              BIT(12)
  83 #define SDMMC_CLKCR_WIDBUS_4            BIT(14)
  84 #define SDMMC_CLKCR_WIDBUS_8            BIT(15)
  85 #define SDMMC_CLKCR_NEGEDGE             BIT(16)
  86 #define SDMMC_CLKCR_HWFC_EN             BIT(17)
  87 #define SDMMC_CLKCR_DDR                 BIT(18)
  88 #define SDMMC_CLKCR_BUSSPEED            BIT(19)
  89 #define SDMMC_CLKCR_SELCLKRX_MASK       GENMASK(21, 20)
  90 #define SDMMC_CLKCR_SELCLKRX_CK         0
  91 #define SDMMC_CLKCR_SELCLKRX_CKIN       BIT(20)
  92 #define SDMMC_CLKCR_SELCLKRX_FBCK       BIT(21)
  93
  94 /* SDMMC_CMD register */
  95 #define SDMMC_CMD_CMDINDEX              GENMASK(5, 0)
  96 #define SDMMC_CMD_CMDTRANS              BIT(6)
  97 #define SDMMC_CMD_CMDSTOP               BIT(7)
  98 #define SDMMC_CMD_WAITRESP              GENMASK(9, 8)
  99 #define SDMMC_CMD_WAITRESP_0            BIT(8)
 100 #define SDMMC_CMD_WAITRESP_1            BIT(9)
 101 #define SDMMC_CMD_WAITINT               BIT(10)
 102 #define SDMMC_CMD_WAITPEND              BIT(11)
 103 #define SDMMC_CMD_CPSMEN                BIT(12)
 104 #define SDMMC_CMD_DTHOLD                BIT(13)
 105 #define SDMMC_CMD_BOOTMODE              BIT(14)
 106 #define SDMMC_CMD_BOOTEN                BIT(15)
 107 #define SDMMC_CMD_CMDSUSPEND            BIT(16)
 108
 109 /* SDMMC_DCTRL register */
 110 #define SDMMC_DCTRL_DTEN                BIT(0)
 111 #define SDMMC_DCTRL_DTDIR               BIT(1)
 112 #define SDMMC_DCTRL_DTMODE              GENMASK(3, 2)
 113 #define SDMMC_DCTRL_DBLOCKSIZE          GENMASK(7, 4)
 114 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT    4
 115 #define SDMMC_DCTRL_RWSTART             BIT(8)
 116 #define SDMMC_DCTRL_RWSTOP              BIT(9)
 117 #define SDMMC_DCTRL_RWMOD               BIT(10)
 118 #define SDMMC_DCTRL_SDMMCEN             BIT(11)
 119 #define SDMMC_DCTRL_BOOTACKEN           BIT(12)
 120 #define SDMMC_DCTRL_FIFORST             BIT(13)
 121
 122 /* SDMMC_STA register */
 123 #define SDMMC_STA_CCRCFAIL              BIT(0)
 124 #define SDMMC_STA_DCRCFAIL              BIT(1)
 125 #define SDMMC_STA_CTIMEOUT              BIT(2)
 126 #define SDMMC_STA_DTIMEOUT              BIT(3)
 127 #define SDMMC_STA_TXUNDERR              BIT(4)
 128 #define SDMMC_STA_RXOVERR               BIT(5)
 129 #define SDMMC_STA_CMDREND               BIT(6)
 130 #define SDMMC_STA_CMDSENT               BIT(7)
 131 #define SDMMC_STA_DATAEND               BIT(8)
 132 #define SDMMC_STA_DHOLD                 BIT(9)
 133 #define SDMMC_STA_DBCKEND               BIT(10)
 134 #define SDMMC_STA_DABORT                BIT(11)
 135 #define SDMMC_STA_DPSMACT               BIT(12)
 136 #define SDMMC_STA_CPSMACT               BIT(13)
 137 #define SDMMC_STA_TXFIFOHE              BIT(14)
 138 #define SDMMC_STA_RXFIFOHF              BIT(15)
 139 #define SDMMC_STA_TXFIFOF               BIT(16)
 140 #define SDMMC_STA_RXFIFOF               BIT(17)
 141 #define SDMMC_STA_TXFIFOE               BIT(18)
 142 #define SDMMC_STA_RXFIFOE               BIT(19)
 143 #define SDMMC_STA_BUSYD0                BIT(20)
 144 #define SDMMC_STA_BUSYD0END             BIT(21)
 145 #define SDMMC_STA_SDMMCIT               BIT(22)
 146 #define SDMMC_STA_ACKFAIL               BIT(23)
 147 #define SDMMC_STA_ACKTIMEOUT            BIT(24)
 148 #define SDMMC_STA_VSWEND                BIT(25)
 149 #define SDMMC_STA_CKSTOP                BIT(26)
 150 #define SDMMC_STA_IDMATE                BIT(27)
 151 #define SDMMC_STA_IDMABTC               BIT(28)
 152
 153 /* SDMMC_ICR register */
 154 #define SDMMC_ICR_CCRCFAILC             BIT(0)
 155 #define SDMMC_ICR_DCRCFAILC             BIT(1)
 156 #define SDMMC_ICR_CTIMEOUTC             BIT(2)
 157 #define SDMMC_ICR_DTIMEOUTC             BIT(3)
 158 #define SDMMC_ICR_TXUNDERRC             BIT(4)
 159 #define SDMMC_ICR_RXOVERRC              BIT(5)
 160 #define SDMMC_ICR_CMDRENDC              BIT(6)
 161 #define SDMMC_ICR_CMDSENTC              BIT(7)
 162 #define SDMMC_ICR_DATAENDC              BIT(8)
 163 #define SDMMC_ICR_DHOLDC                BIT(9)
 164 #define SDMMC_ICR_DBCKENDC              BIT(10)
 165 #define SDMMC_ICR_DABORTC               BIT(11)
 166 #define SDMMC_ICR_BUSYD0ENDC            BIT(21)
 167 #define SDMMC_ICR_SDMMCITC              BIT(22)
 168 #define SDMMC_ICR_ACKFAILC              BIT(23)
 169 #define SDMMC_ICR_ACKTIMEOUTC           BIT(24)
 170 #define SDMMC_ICR_VSWENDC               BIT(25)
 171 #define SDMMC_ICR_CKSTOPC               BIT(26)
 172 #define SDMMC_ICR_IDMATEC               BIT(27)
 173 #define SDMMC_ICR_IDMABTCC              BIT(28)
 174 #define SDMMC_ICR_STATIC_FLAGS          ((GENMASK(28, 21)) | (GENMASK(11, 0)))
 175
 176 /* SDMMC_MASK register */
 177 #define SDMMC_MASK_CCRCFAILIE           BIT(0)
 178 #define SDMMC_MASK_DCRCFAILIE           BIT(1)
 179 #define SDMMC_MASK_CTIMEOUTIE           BIT(2)
 180 #define SDMMC_MASK_DTIMEOUTIE           BIT(3)
 181 #define SDMMC_MASK_TXUNDERRIE           BIT(4)
 182 #define SDMMC_MASK_RXOVERRIE            BIT(5)
 183 #define SDMMC_MASK_CMDRENDIE            BIT(6)
 184 #define SDMMC_MASK_CMDSENTIE            BIT(7)
 185 #define SDMMC_MASK_DATAENDIE            BIT(8)
 186 #define SDMMC_MASK_DHOLDIE              BIT(9)
 187 #define SDMMC_MASK_DBCKENDIE            BIT(10)
 188 #define SDMMC_MASK_DABORTIE             BIT(11)
 189 #define SDMMC_MASK_TXFIFOHEIE           BIT(14)
 190 #define SDMMC_MASK_RXFIFOHFIE           BIT(15)
 191 #define SDMMC_MASK_RXFIFOFIE            BIT(17)
 192 #define SDMMC_MASK_TXFIFOEIE            BIT(18)
 193 #define SDMMC_MASK_BUSYD0ENDIE          BIT(21)
 194 #define SDMMC_MASK_SDMMCITIE            BIT(22)
 195 #define SDMMC_MASK_ACKFAILIE            BIT(23)
 196 #define SDMMC_MASK_ACKTIMEOUTIE         BIT(24)
 197 #define SDMMC_MASK_VSWENDIE             BIT(25)
 198 #define SDMMC_MASK_CKSTOPIE             BIT(26)
 199 #define SDMMC_MASK_IDMABTCIE            BIT(28)
 200
 201 /* SDMMC_IDMACTRL register */
 202 #define SDMMC_IDMACTRL_IDMAEN           BIT(0)
 203
 204 #define SDMMC_CMD_TIMEOUT               0xFFFFFFFF
 205 #define SDMMC_BUSYD0END_TIMEOUT_US      2000000
 206
 207 static void stm32_sdmmc2_start_data(struct udevice *dev,
 208                                     struct mmc_data *data,
 209                                     struct stm32_sdmmc2_ctx *ctx)
 210 {
 211         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 212         u32 data_ctrl, idmabase0;
 213
 214         /* Configure the SDMMC DPSM (Data Path State Machine) */
 215         data_ctrl = (__ilog2(data->blocksize) <<
 216                      SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
 217                     SDMMC_DCTRL_DBLOCKSIZE;
 218
 219         if (data->flags & MMC_DATA_READ) {
 220                 data_ctrl |= SDMMC_DCTRL_DTDIR;
 221                 idmabase0 = (u32)data->dest;
 222         } else {
 223                 idmabase0 = (u32)data->src;
 224         }
 225
 226         /* Set the SDMMC DataLength value */
 227         writel(ctx->data_length, priv->base + SDMMC_DLEN);
 228
 229         /* Write to SDMMC DCTRL */
 230         writel(data_ctrl, priv->base + SDMMC_DCTRL);
 231
 232         /* Cache align */
 233         ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
 234         ctx->cache_end = roundup(idmabase0 + ctx->data_length,
 235                                  ARCH_DMA_MINALIGN);
 236
 237         /*
 238          * Flush data cache before DMA start (clean and invalidate)
 239          * Clean also needed for read
 240          * Avoid issue on buffer not cached-aligned
 241          */
 242         flush_dcache_range(ctx->cache_start, ctx->cache_end);
 243
 244         /* Enable internal DMA */
 245         writel(idmabase0, priv->base + SDMMC_IDMABASE0);
 246         writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
 247 }
 248
 249 static void stm32_sdmmc2_start_cmd(struct udevice *dev,
 250                                    struct mmc_cmd *cmd, u32 cmd_param,
 251                                    struct stm32_sdmmc2_ctx *ctx)
 252 {
 253         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 254         u32 timeout = 0;
 255
 256         if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
 257                 writel(0, priv->base + SDMMC_CMD);
 258
 259         cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
 260         if (cmd->resp_type & MMC_RSP_PRESENT) {
 261                 if (cmd->resp_type & MMC_RSP_136)
 262                         cmd_param |= SDMMC_CMD_WAITRESP;
 263                 else if (cmd->resp_type & MMC_RSP_CRC)
 264                         cmd_param |= SDMMC_CMD_WAITRESP_0;
 265                 else
 266                         cmd_param |= SDMMC_CMD_WAITRESP_1;
 267         }
 268
 269         /*
 270          * SDMMC_DTIME must be set in two case:
 271          * - on data transfert.
 272          * - on busy request.
 273          * If not done or too short, the dtimeout flag occurs and DPSM stays
 274          * enabled/busy and waits for abort (stop transmission cmd).
 275          * Next data command is not possible whereas DPSM is activated.
 276          */
 277         if (ctx->data_length) {
 278                 timeout = SDMMC_CMD_TIMEOUT;
 279         } else {
 280                 writel(0, priv->base + SDMMC_DCTRL);
 281
 282                 if (cmd->resp_type & MMC_RSP_BUSY)
 283                         timeout = SDMMC_CMD_TIMEOUT;
 284         }
 285
 286         /* Set the SDMMC Data TimeOut value */
 287         writel(timeout, priv->base + SDMMC_DTIMER);
 288
 289         /* Clear flags */
 290         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 291
 292         /* Set SDMMC argument value */
 293         writel(cmd->cmdarg, priv->base + SDMMC_ARG);
 294
 295         /* Set SDMMC command parameters */
 296         writel(cmd_param, priv->base + SDMMC_CMD);
 297 }
 298
 299 static int stm32_sdmmc2_end_cmd(struct udevice *dev,
 300                                 struct mmc_cmd *cmd,
 301                                 struct stm32_sdmmc2_ctx *ctx)
 302 {
 303         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 304         u32 mask = SDMMC_STA_CTIMEOUT;
 305         u32 status;
 306         int ret;
 307
 308         if (cmd->resp_type & MMC_RSP_PRESENT) {
 309                 mask |= SDMMC_STA_CMDREND;
 310                 if (cmd->resp_type & MMC_RSP_CRC)
 311                         mask |= SDMMC_STA_CCRCFAIL;
 312         } else {
 313                 mask |= SDMMC_STA_CMDSENT;
 314         }
 315
 316         /* Polling status register */
 317         ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
 318                                  10000);
 319
 320         if (ret < 0) {
 321                 dev_dbg(dev, "timeout reading SDMMC_STA register\n");
 322                 ctx->dpsm_abort = true;
 323                 return ret;
 324         }
 325
 326         /* Check status */
 327         if (status & SDMMC_STA_CTIMEOUT) {
 328                 dev_dbg(dev, "error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
 329                         status, cmd->cmdidx);
 330                 ctx->dpsm_abort = true;
 331                 return -ETIMEDOUT;
 332         }
 333
 334         if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
 335                 dev_dbg(dev, "error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
 336                         status, cmd->cmdidx);
 337                 ctx->dpsm_abort = true;
 338                 return -EILSEQ;
 339         }
 340
 341         if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
 342                 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
 343                 if (cmd->resp_type & MMC_RSP_136) {
 344                         cmd->response[1] = readl(priv->base + SDMMC_RESP2);
 345                         cmd->response[2] = readl(priv->base + SDMMC_RESP3);
 346                         cmd->response[3] = readl(priv->base + SDMMC_RESP4);
 347                 }
 348
 349                 /* Wait for BUSYD0END flag if busy status is detected */
 350                 if (cmd->resp_type & MMC_RSP_BUSY &&
 351                     status & SDMMC_STA_BUSYD0) {
 352                         mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
 353
 354                         /* Polling status register */
 355                         ret = readl_poll_timeout(priv->base + SDMMC_STA,
 356                                                  status, status & mask,
 357                                                  SDMMC_BUSYD0END_TIMEOUT_US);
 358
 359                         if (ret < 0) {
 360                                 dev_dbg(dev, "timeout reading SDMMC_STA\n");
 361                                 ctx->dpsm_abort = true;
 362                                 return ret;
 363                         }
 364
 365                         if (status & SDMMC_STA_DTIMEOUT) {
 366                                 dev_dbg(dev,
 367                                         "error SDMMC_STA_DTIMEOUT (0x%x)\n",
 368                                         status);
 369                                 ctx->dpsm_abort = true;
 370                                 return -ETIMEDOUT;
 371                         }
 372                 }
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int stm32_sdmmc2_end_data(struct udevice *dev,
 379                                  struct mmc_cmd *cmd,
 380                                  struct mmc_data *data,
 381                                  struct stm32_sdmmc2_ctx *ctx)
 382 {
 383         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 384         u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 385                    SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 386         u32 status;
 387
 388         if (data->flags & MMC_DATA_READ)
 389                 mask |= SDMMC_STA_RXOVERR;
 390         else
 391                 mask |= SDMMC_STA_TXUNDERR;
 392
 393         status = readl(priv->base + SDMMC_STA);
 394         while (!(status & mask))
 395                 status = readl(priv->base + SDMMC_STA);
 396
 397         /*
 398          * Need invalidate the dcache again to avoid any
 399          * cache-refill during the DMA operations (pre-fetching)
 400          */
 401         if (data->flags & MMC_DATA_READ)
 402                 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
 403
 404         if (status & SDMMC_STA_DCRCFAIL) {
 405                 dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
 406                         status, cmd->cmdidx);
 407                 if (readl(priv->base + SDMMC_DCOUNT))
 408                         ctx->dpsm_abort = true;
 409                 return -EILSEQ;
 410         }
 411
 412         if (status & SDMMC_STA_DTIMEOUT) {
 413                 dev_dbg(dev, "error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
 414                         status, cmd->cmdidx);
 415                 ctx->dpsm_abort = true;
 416                 return -ETIMEDOUT;
 417         }
 418
 419         if (status & SDMMC_STA_TXUNDERR) {
 420                 dev_dbg(dev, "error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
 421                         status, cmd->cmdidx);
 422                 ctx->dpsm_abort = true;
 423                 return -EIO;
 424         }
 425
 426         if (status & SDMMC_STA_RXOVERR) {
 427                 dev_dbg(dev, "error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
 428                         status, cmd->cmdidx);
 429                 ctx->dpsm_abort = true;
 430                 return -EIO;
 431         }
 432
 433         if (status & SDMMC_STA_IDMATE) {
 434                 dev_dbg(dev, "error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
 435                         status, cmd->cmdidx);
 436                 ctx->dpsm_abort = true;
 437                 return -EIO;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 444                                  struct mmc_data *data)
 445 {
 446         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 447         struct stm32_sdmmc2_ctx ctx;
 448         u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
 449         int ret, retry = 3;
 450
 451         WATCHDOG_RESET();
 452
 453 retry_cmd:
 454         ctx.data_length = 0;
 455         ctx.dpsm_abort = false;
 456
 457         if (data) {
 458                 ctx.data_length = data->blocks * data->blocksize;
 459                 stm32_sdmmc2_start_data(dev, data, &ctx);
 460         }
 461
 462         stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx);
 463
 464         dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%x\n",
 465                 cmd->cmdidx, data ? ctx.data_length : 0, (unsigned int)data);
 466
 467         ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx);
 468
 469         if (data && !ret)
 470                 ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx);
 471
 472         /* Clear flags */
 473         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 474         if (data)
 475                 writel(0x0, priv->base + SDMMC_IDMACTRL);
 476
 477         /*
 478          * To stop Data Path State Machine, a stop_transmission command
 479          * shall be send on cmd or data errors.
 480          */
 481         if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
 482                 struct mmc_cmd stop_cmd;
 483
 484                 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 485                 stop_cmd.cmdarg = 0;
 486                 stop_cmd.resp_type = MMC_RSP_R1b;
 487
 488                 dev_dbg(dev, "send STOP command to abort dpsm treatments\n");
 489
 490                 ctx.data_length = 0;
 491
 492                 stm32_sdmmc2_start_cmd(dev, &stop_cmd,
 493                                        SDMMC_CMD_CMDSTOP, &ctx);
 494                 stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx);
 495
 496                 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 497         }
 498
 499         if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
 500                 dev_err(dev, "cmd %d failed, retrying ...\n", cmd->cmdidx);
 501                 retry--;
 502                 goto retry_cmd;
 503         }
 504
 505         dev_dbg(dev, "end for CMD %d, ret = %d\n", cmd->cmdidx, ret);
 506
 507         return ret;
 508 }
 509
 510 /*
 511  * Reset the SDMMC with the RCC.SDMMCxRST register bit.
 512  * This will reset the SDMMC to the reset state and the CPSM and DPSM
 513  * to the Idle state. SDMMC is disabled, Signals Hiz.
 514  */
 515 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
 516 {
 517         if (reset_valid(&priv->reset_ctl)) {
 518                 /* Reset */
 519                 reset_assert(&priv->reset_ctl);
 520                 udelay(2);
 521                 reset_deassert(&priv->reset_ctl);
 522         }
 523
 524         /* init the needed SDMMC register after reset */
 525         writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
 526 }
 527
 528 /*
 529  * Set the SDMMC in power-cycle state.
 530  * This will make that the SDMMC_D[7:0],
 531  * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
 532  * supplied through the signal lines.
 533  */
 534 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
 535 {
 536         if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
 537             SDMMC_POWER_PWRCTRL_CYCLE)
 538                 return;
 539
 540         stm32_sdmmc2_reset(priv);
 541 }
 542
 543 /*
 544  * set the SDMMC state Power-on: the card is clocked
 545  * manage the SDMMC state control:
 546  * Reset => Power-Cycle => Power-Off => Power
 547  *    PWRCTRL=10     PWCTRL=00    PWCTRL=11
 548  */
 549 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
 550 {
 551         u32 pwrctrl =
 552                 readl(priv->base + SDMMC_POWER) &  SDMMC_POWER_PWRCTRL_MASK;
 553
 554         if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
 555                 return;
 556
 557         /* warning: same PWRCTRL value after reset and for power-off state
 558          * it is the reset state here = the only managed by the driver
 559          */
 560         if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
 561                 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 562                        priv->base + SDMMC_POWER);
 563         }
 564
 565         /*
 566          * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
 567          * switch to Power-Off state: SDMCC disable, signals drive 1
 568          */
 569         writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
 570                priv->base + SDMMC_POWER);
 571
 572         /* After the 1ms delay set the SDMMC to power-on */
 573         mdelay(1);
 574         writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
 575                priv->base + SDMMC_POWER);
 576
 577         /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
 578 }
 579
 580 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
 581 static int stm32_sdmmc2_set_ios(struct udevice *dev)
 582 {
 583         struct mmc *mmc = mmc_get_mmc_dev(dev);
 584         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 585         u32 desired = mmc->clock;
 586         u32 sys_clock = clk_get_rate(&priv->clk);
 587         u32 clk = 0;
 588
 589         dev_dbg(dev, "bus_with = %d, clock = %d\n",
 590                 mmc->bus_width, mmc->clock);
 591
 592         if (mmc->clk_disable)
 593                 stm32_sdmmc2_pwrcycle(priv);
 594         else
 595                 stm32_sdmmc2_pwron(priv);
 596
 597         /*
 598          * clk_div = 0 => command and data generated on SDMMCCLK falling edge
 599          * clk_div > 0 and NEGEDGE = 0 => command and data generated on
 600          * SDMMCCLK rising edge
 601          * clk_div > 0 and NEGEDGE = 1 => command and data generated on
 602          * SDMMCCLK falling edge
 603          */
 604         if (desired && ((sys_clock > desired) ||
 605                         IS_RISING_EDGE(priv->clk_reg_msk))) {
 606                 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
 607                 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
 608                         clk = SDMMC_CLKCR_CLKDIV_MAX;
 609         }
 610
 611         if (mmc->bus_width == 4)
 612                 clk |= SDMMC_CLKCR_WIDBUS_4;
 613         if (mmc->bus_width == 8)
 614                 clk |= SDMMC_CLKCR_WIDBUS_8;
 615
 616         writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
 617                priv->base + SDMMC_CLKCR);
 618
 619         return 0;
 620 }
 621
 622 static int stm32_sdmmc2_getcd(struct udevice *dev)
 623 {
 624         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 625
 626         dev_dbg(dev, "%s called\n", __func__);
 627
 628         if (dm_gpio_is_valid(&priv->cd_gpio))
 629                 return dm_gpio_get_value(&priv->cd_gpio);
 630
 631         return 1;
 632 }
 633
 634 static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
 635 {
 636         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 637
 638         writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 639                priv->base + SDMMC_POWER);
 640
 641         return 0;
 642 }
 643
 644 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
 645         .send_cmd = stm32_sdmmc2_send_cmd,
 646         .set_ios = stm32_sdmmc2_set_ios,
 647         .get_cd = stm32_sdmmc2_getcd,
 648         .host_power_cycle = stm32_sdmmc2_host_power_cycle,
 649 };
 650
 651 static int stm32_sdmmc2_probe_level_translator(struct udevice *dev)
 652 {
 653         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 654         struct gpio_desc cmd_gpio;
 655         struct gpio_desc ck_gpio;
 656         struct gpio_desc ckin_gpio;
 657         int clk_hi, clk_lo, ret;
 658
 659         /*
 660          * Assume the level translator is present if st,use-ckin is set.
 661          * This is to cater for DTs which do not implement this test.
 662          */
 663         priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
 664
 665         ret = gpio_request_by_name(dev, "st,cmd-gpios", 0, &cmd_gpio,
 666                                    GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 667         if (ret)
 668                 goto exit_cmd;
 669
 670         ret = gpio_request_by_name(dev, "st,ck-gpios", 0, &ck_gpio,
 671                                    GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 672         if (ret)
 673                 goto exit_ck;
 674
 675         ret = gpio_request_by_name(dev, "st,ckin-gpios", 0, &ckin_gpio,
 676                                    GPIOD_IS_IN);
 677         if (ret)
 678                 goto exit_ckin;
 679
 680         /* All GPIOs are valid, test whether level translator works */
 681
 682         /* Sample CKIN */
 683         clk_hi = !!dm_gpio_get_value(&ckin_gpio);
 684
 685         /* Set CK low */
 686         dm_gpio_set_value(&ck_gpio, 0);
 687
 688         /* Sample CKIN */
 689         clk_lo = !!dm_gpio_get_value(&ckin_gpio);
 690
 691         /* Tristate all */
 692         dm_gpio_set_dir_flags(&cmd_gpio, GPIOD_IS_IN);
 693         dm_gpio_set_dir_flags(&ck_gpio, GPIOD_IS_IN);
 694
 695         /* Level translator is present if CK signal is propagated to CKIN */
 696         if (!clk_hi || clk_lo)
 697                 priv->clk_reg_msk &= ~SDMMC_CLKCR_SELCLKRX_CKIN;
 698
 699         dm_gpio_free(dev, &ckin_gpio);
 700
 701 exit_ckin:
 702         dm_gpio_free(dev, &ck_gpio);
 703 exit_ck:
 704         dm_gpio_free(dev, &cmd_gpio);
 705 exit_cmd:
 706         pinctrl_select_state(dev, "default");
 707
 708         return 0;
 709 }
 710
 711 static int stm32_sdmmc2_probe(struct udevice *dev)
 712 {
 713         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 714         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 715         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 716         struct mmc_config *cfg = &plat->cfg;
 717         int ret;
 718
 719         priv->base = dev_read_addr(dev);
 720         if (priv->base == FDT_ADDR_T_NONE)
 721                 return -EINVAL;
 722
 723         if (dev_read_bool(dev, "st,neg-edge"))
 724                 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
 725         if (dev_read_bool(dev, "st,sig-dir"))
 726                 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
 727         if (dev_read_bool(dev, "st,use-ckin"))
 728                 stm32_sdmmc2_probe_level_translator(dev);
 729
 730         ret = clk_get_by_index(dev, 0, &priv->clk);
 731         if (ret)
 732                 return ret;
 733
 734         ret = clk_enable(&priv->clk);
 735         if (ret)
 736                 goto clk_free;
 737
 738         ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
 739         if (ret)
 740                 dev_dbg(dev, "No reset provided\n");
 741
 742         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 743                              GPIOD_IS_IN);
 744
 745         cfg->f_min = 400000;
 746         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 747         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 748         cfg->name = "STM32 SD/MMC";
 749
 750         cfg->host_caps = 0;
 751         cfg->f_max = 52000000;
 752         mmc_of_parse(dev, cfg);
 753
 754         upriv->mmc = &plat->mmc;
 755
 756         /* SDMMC init */
 757         stm32_sdmmc2_reset(priv);
 758         return 0;
 759
 760 clk_free:
 761         clk_free(&priv->clk);
 762
 763         return ret;
 764 }
 765
 766 static int stm32_sdmmc_bind(struct udevice *dev)
 767 {
 768         struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 769
 770         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 771 }
 772
 773 static const struct udevice_id stm32_sdmmc2_ids[] = {
 774         { .compatible = "st,stm32-sdmmc2" },
 775         { }
 776 };
 777
 778 U_BOOT_DRIVER(stm32_sdmmc2) = {
 779         .name = "stm32_sdmmc2",
 780         .id = UCLASS_MMC,
 781         .of_match = stm32_sdmmc2_ids,
 782         .ops = &stm32_sdmmc2_ops,
 783         .probe = stm32_sdmmc2_probe,
 784         .bind = stm32_sdmmc_bind,
 785         .priv_auto      = sizeof(struct stm32_sdmmc2_priv),
 786         .plat_auto      = sizeof(struct stm32_sdmmc2_plat),
 787 };