1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
13 #include <asm/cache.h>
14 #include <linux/libfdt.h>
19 #include <linux/iopoll.h>
22 struct stm32_sdmmc2_plat {
23 struct mmc_config cfg;
27 struct stm32_sdmmc2_priv {
30 struct reset_ctl reset_ctl;
31 struct gpio_desc cd_gpio;
36 struct stm32_sdmmc2_ctx {
43 /* SDMMC REGISTERS OFFSET */
44 #define SDMMC_POWER 0x00 /* SDMMC power control */
45 #define SDMMC_CLKCR 0x04 /* SDMMC clock control */
46 #define SDMMC_ARG 0x08 /* SDMMC argument */
47 #define SDMMC_CMD 0x0C /* SDMMC command */
48 #define SDMMC_RESP1 0x14 /* SDMMC response 1 */
49 #define SDMMC_RESP2 0x18 /* SDMMC response 2 */
50 #define SDMMC_RESP3 0x1C /* SDMMC response 3 */
51 #define SDMMC_RESP4 0x20 /* SDMMC response 4 */
52 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
53 #define SDMMC_DLEN 0x28 /* SDMMC data length */
54 #define SDMMC_DCTRL 0x2C /* SDMMC data control */
55 #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
56 #define SDMMC_STA 0x34 /* SDMMC status */
57 #define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
58 #define SDMMC_MASK 0x3C /* SDMMC mask */
59 #define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
60 #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
62 /* SDMMC_POWER register */
63 #define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0)
64 #define SDMMC_POWER_PWRCTRL_OFF 0
65 #define SDMMC_POWER_PWRCTRL_CYCLE 2
66 #define SDMMC_POWER_PWRCTRL_ON 3
67 #define SDMMC_POWER_VSWITCH BIT(2)
68 #define SDMMC_POWER_VSWITCHEN BIT(3)
69 #define SDMMC_POWER_DIRPOL BIT(4)
71 /* SDMMC_CLKCR register */
72 #define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
73 #define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV
74 #define SDMMC_CLKCR_PWRSAV BIT(12)
75 #define SDMMC_CLKCR_WIDBUS_4 BIT(14)
76 #define SDMMC_CLKCR_WIDBUS_8 BIT(15)
77 #define SDMMC_CLKCR_NEGEDGE BIT(16)
78 #define SDMMC_CLKCR_HWFC_EN BIT(17)
79 #define SDMMC_CLKCR_DDR BIT(18)
80 #define SDMMC_CLKCR_BUSSPEED BIT(19)
81 #define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
82 #define SDMMC_CLKCR_SELCLKRX_CK 0
83 #define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20)
84 #define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21)
86 /* SDMMC_CMD register */
87 #define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
88 #define SDMMC_CMD_CMDTRANS BIT(6)
89 #define SDMMC_CMD_CMDSTOP BIT(7)
90 #define SDMMC_CMD_WAITRESP GENMASK(9, 8)
91 #define SDMMC_CMD_WAITRESP_0 BIT(8)
92 #define SDMMC_CMD_WAITRESP_1 BIT(9)
93 #define SDMMC_CMD_WAITINT BIT(10)
94 #define SDMMC_CMD_WAITPEND BIT(11)
95 #define SDMMC_CMD_CPSMEN BIT(12)
96 #define SDMMC_CMD_DTHOLD BIT(13)
97 #define SDMMC_CMD_BOOTMODE BIT(14)
98 #define SDMMC_CMD_BOOTEN BIT(15)
99 #define SDMMC_CMD_CMDSUSPEND BIT(16)
101 /* SDMMC_DCTRL register */
102 #define SDMMC_DCTRL_DTEN BIT(0)
103 #define SDMMC_DCTRL_DTDIR BIT(1)
104 #define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
105 #define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
106 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4
107 #define SDMMC_DCTRL_RWSTART BIT(8)
108 #define SDMMC_DCTRL_RWSTOP BIT(9)
109 #define SDMMC_DCTRL_RWMOD BIT(10)
110 #define SDMMC_DCTRL_SDMMCEN BIT(11)
111 #define SDMMC_DCTRL_BOOTACKEN BIT(12)
112 #define SDMMC_DCTRL_FIFORST BIT(13)
114 /* SDMMC_STA register */
115 #define SDMMC_STA_CCRCFAIL BIT(0)
116 #define SDMMC_STA_DCRCFAIL BIT(1)
117 #define SDMMC_STA_CTIMEOUT BIT(2)
118 #define SDMMC_STA_DTIMEOUT BIT(3)
119 #define SDMMC_STA_TXUNDERR BIT(4)
120 #define SDMMC_STA_RXOVERR BIT(5)
121 #define SDMMC_STA_CMDREND BIT(6)
122 #define SDMMC_STA_CMDSENT BIT(7)
123 #define SDMMC_STA_DATAEND BIT(8)
124 #define SDMMC_STA_DHOLD BIT(9)
125 #define SDMMC_STA_DBCKEND BIT(10)
126 #define SDMMC_STA_DABORT BIT(11)
127 #define SDMMC_STA_DPSMACT BIT(12)
128 #define SDMMC_STA_CPSMACT BIT(13)
129 #define SDMMC_STA_TXFIFOHE BIT(14)
130 #define SDMMC_STA_RXFIFOHF BIT(15)
131 #define SDMMC_STA_TXFIFOF BIT(16)
132 #define SDMMC_STA_RXFIFOF BIT(17)
133 #define SDMMC_STA_TXFIFOE BIT(18)
134 #define SDMMC_STA_RXFIFOE BIT(19)
135 #define SDMMC_STA_BUSYD0 BIT(20)
136 #define SDMMC_STA_BUSYD0END BIT(21)
137 #define SDMMC_STA_SDMMCIT BIT(22)
138 #define SDMMC_STA_ACKFAIL BIT(23)
139 #define SDMMC_STA_ACKTIMEOUT BIT(24)
140 #define SDMMC_STA_VSWEND BIT(25)
141 #define SDMMC_STA_CKSTOP BIT(26)
142 #define SDMMC_STA_IDMATE BIT(27)
143 #define SDMMC_STA_IDMABTC BIT(28)
145 /* SDMMC_ICR register */
146 #define SDMMC_ICR_CCRCFAILC BIT(0)
147 #define SDMMC_ICR_DCRCFAILC BIT(1)
148 #define SDMMC_ICR_CTIMEOUTC BIT(2)
149 #define SDMMC_ICR_DTIMEOUTC BIT(3)
150 #define SDMMC_ICR_TXUNDERRC BIT(4)
151 #define SDMMC_ICR_RXOVERRC BIT(5)
152 #define SDMMC_ICR_CMDRENDC BIT(6)
153 #define SDMMC_ICR_CMDSENTC BIT(7)
154 #define SDMMC_ICR_DATAENDC BIT(8)
155 #define SDMMC_ICR_DHOLDC BIT(9)
156 #define SDMMC_ICR_DBCKENDC BIT(10)
157 #define SDMMC_ICR_DABORTC BIT(11)
158 #define SDMMC_ICR_BUSYD0ENDC BIT(21)
159 #define SDMMC_ICR_SDMMCITC BIT(22)
160 #define SDMMC_ICR_ACKFAILC BIT(23)
161 #define SDMMC_ICR_ACKTIMEOUTC BIT(24)
162 #define SDMMC_ICR_VSWENDC BIT(25)
163 #define SDMMC_ICR_CKSTOPC BIT(26)
164 #define SDMMC_ICR_IDMATEC BIT(27)
165 #define SDMMC_ICR_IDMABTCC BIT(28)
166 #define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
168 /* SDMMC_MASK register */
169 #define SDMMC_MASK_CCRCFAILIE BIT(0)
170 #define SDMMC_MASK_DCRCFAILIE BIT(1)
171 #define SDMMC_MASK_CTIMEOUTIE BIT(2)
172 #define SDMMC_MASK_DTIMEOUTIE BIT(3)
173 #define SDMMC_MASK_TXUNDERRIE BIT(4)
174 #define SDMMC_MASK_RXOVERRIE BIT(5)
175 #define SDMMC_MASK_CMDRENDIE BIT(6)
176 #define SDMMC_MASK_CMDSENTIE BIT(7)
177 #define SDMMC_MASK_DATAENDIE BIT(8)
178 #define SDMMC_MASK_DHOLDIE BIT(9)
179 #define SDMMC_MASK_DBCKENDIE BIT(10)
180 #define SDMMC_MASK_DABORTIE BIT(11)
181 #define SDMMC_MASK_TXFIFOHEIE BIT(14)
182 #define SDMMC_MASK_RXFIFOHFIE BIT(15)
183 #define SDMMC_MASK_RXFIFOFIE BIT(17)
184 #define SDMMC_MASK_TXFIFOEIE BIT(18)
185 #define SDMMC_MASK_BUSYD0ENDIE BIT(21)
186 #define SDMMC_MASK_SDMMCITIE BIT(22)
187 #define SDMMC_MASK_ACKFAILIE BIT(23)
188 #define SDMMC_MASK_ACKTIMEOUTIE BIT(24)
189 #define SDMMC_MASK_VSWENDIE BIT(25)
190 #define SDMMC_MASK_CKSTOPIE BIT(26)
191 #define SDMMC_MASK_IDMABTCIE BIT(28)
193 /* SDMMC_IDMACTRL register */
194 #define SDMMC_IDMACTRL_IDMAEN BIT(0)
196 #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
197 #define SDMMC_BUSYD0END_TIMEOUT_US 2000000
199 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
200 struct mmc_data *data,
201 struct stm32_sdmmc2_ctx *ctx)
203 u32 data_ctrl, idmabase0;
205 /* Configure the SDMMC DPSM (Data Path State Machine) */
206 data_ctrl = (__ilog2(data->blocksize) <<
207 SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
208 SDMMC_DCTRL_DBLOCKSIZE;
210 if (data->flags & MMC_DATA_READ) {
211 data_ctrl |= SDMMC_DCTRL_DTDIR;
212 idmabase0 = (u32)data->dest;
214 idmabase0 = (u32)data->src;
217 /* Set the SDMMC DataLength value */
218 writel(ctx->data_length, priv->base + SDMMC_DLEN);
220 /* Write to SDMMC DCTRL */
221 writel(data_ctrl, priv->base + SDMMC_DCTRL);
224 ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
225 ctx->cache_end = roundup(idmabase0 + ctx->data_length,
229 * Flush data cache before DMA start (clean and invalidate)
230 * Clean also needed for read
231 * Avoid issue on buffer not cached-aligned
233 flush_dcache_range(ctx->cache_start, ctx->cache_end);
235 /* Enable internal DMA */
236 writel(idmabase0, priv->base + SDMMC_IDMABASE0);
237 writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
240 static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
241 struct mmc_cmd *cmd, u32 cmd_param,
242 struct stm32_sdmmc2_ctx *ctx)
246 if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
247 writel(0, priv->base + SDMMC_CMD);
249 cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
250 if (cmd->resp_type & MMC_RSP_PRESENT) {
251 if (cmd->resp_type & MMC_RSP_136)
252 cmd_param |= SDMMC_CMD_WAITRESP;
253 else if (cmd->resp_type & MMC_RSP_CRC)
254 cmd_param |= SDMMC_CMD_WAITRESP_0;
256 cmd_param |= SDMMC_CMD_WAITRESP_1;
260 * SDMMC_DTIME must be set in two case:
261 * - on data transfert.
263 * If not done or too short, the dtimeout flag occurs and DPSM stays
264 * enabled/busy and waits for abort (stop transmission cmd).
265 * Next data command is not possible whereas DPSM is activated.
267 if (ctx->data_length) {
268 timeout = SDMMC_CMD_TIMEOUT;
270 writel(0, priv->base + SDMMC_DCTRL);
272 if (cmd->resp_type & MMC_RSP_BUSY)
273 timeout = SDMMC_CMD_TIMEOUT;
276 /* Set the SDMMC Data TimeOut value */
277 writel(timeout, priv->base + SDMMC_DTIMER);
280 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
282 /* Set SDMMC argument value */
283 writel(cmd->cmdarg, priv->base + SDMMC_ARG);
285 /* Set SDMMC command parameters */
286 writel(cmd_param, priv->base + SDMMC_CMD);
289 static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
291 struct stm32_sdmmc2_ctx *ctx)
293 u32 mask = SDMMC_STA_CTIMEOUT;
297 if (cmd->resp_type & MMC_RSP_PRESENT) {
298 mask |= SDMMC_STA_CMDREND;
299 if (cmd->resp_type & MMC_RSP_CRC)
300 mask |= SDMMC_STA_CCRCFAIL;
302 mask |= SDMMC_STA_CMDSENT;
305 /* Polling status register */
306 ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
310 debug("%s: timeout reading SDMMC_STA register\n", __func__);
311 ctx->dpsm_abort = true;
316 if (status & SDMMC_STA_CTIMEOUT) {
317 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
318 __func__, status, cmd->cmdidx);
319 ctx->dpsm_abort = true;
323 if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
324 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
325 __func__, status, cmd->cmdidx);
326 ctx->dpsm_abort = true;
330 if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
331 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
332 if (cmd->resp_type & MMC_RSP_136) {
333 cmd->response[1] = readl(priv->base + SDMMC_RESP2);
334 cmd->response[2] = readl(priv->base + SDMMC_RESP3);
335 cmd->response[3] = readl(priv->base + SDMMC_RESP4);
338 /* Wait for BUSYD0END flag if busy status is detected */
339 if (cmd->resp_type & MMC_RSP_BUSY &&
340 status & SDMMC_STA_BUSYD0) {
341 mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
343 /* Polling status register */
344 ret = readl_poll_timeout(priv->base + SDMMC_STA,
345 status, status & mask,
346 SDMMC_BUSYD0END_TIMEOUT_US);
349 debug("%s: timeout reading SDMMC_STA\n",
351 ctx->dpsm_abort = true;
355 if (status & SDMMC_STA_DTIMEOUT) {
356 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
358 ctx->dpsm_abort = true;
367 static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
369 struct mmc_data *data,
370 struct stm32_sdmmc2_ctx *ctx)
372 u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
373 SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
376 if (data->flags & MMC_DATA_READ)
377 mask |= SDMMC_STA_RXOVERR;
379 mask |= SDMMC_STA_TXUNDERR;
381 status = readl(priv->base + SDMMC_STA);
382 while (!(status & mask))
383 status = readl(priv->base + SDMMC_STA);
386 * Need invalidate the dcache again to avoid any
387 * cache-refill during the DMA operations (pre-fetching)
389 if (data->flags & MMC_DATA_READ)
390 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
392 if (status & SDMMC_STA_DCRCFAIL) {
393 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
394 __func__, status, cmd->cmdidx);
395 if (readl(priv->base + SDMMC_DCOUNT))
396 ctx->dpsm_abort = true;
400 if (status & SDMMC_STA_DTIMEOUT) {
401 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
402 __func__, status, cmd->cmdidx);
403 ctx->dpsm_abort = true;
407 if (status & SDMMC_STA_TXUNDERR) {
408 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
409 __func__, status, cmd->cmdidx);
410 ctx->dpsm_abort = true;
414 if (status & SDMMC_STA_RXOVERR) {
415 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
416 __func__, status, cmd->cmdidx);
417 ctx->dpsm_abort = true;
421 if (status & SDMMC_STA_IDMATE) {
422 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
423 __func__, status, cmd->cmdidx);
424 ctx->dpsm_abort = true;
431 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
432 struct mmc_data *data)
434 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
435 struct stm32_sdmmc2_ctx ctx;
436 u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
443 ctx.dpsm_abort = false;
446 ctx.data_length = data->blocks * data->blocksize;
447 stm32_sdmmc2_start_data(priv, data, &ctx);
450 stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
452 debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
453 __func__, cmd->cmdidx,
454 data ? ctx.data_length : 0, (unsigned int)data);
456 ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
459 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
462 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
464 writel(0x0, priv->base + SDMMC_IDMACTRL);
467 * To stop Data Path State Machine, a stop_transmission command
468 * shall be send on cmd or data errors.
470 if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
471 struct mmc_cmd stop_cmd;
473 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
475 stop_cmd.resp_type = MMC_RSP_R1b;
477 debug("%s: send STOP command to abort dpsm treatments\n",
482 stm32_sdmmc2_start_cmd(priv, &stop_cmd,
483 SDMMC_CMD_CMDSTOP, &ctx);
484 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
486 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
489 if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
490 printf("%s: cmd %d failed, retrying ...\n",
491 __func__, cmd->cmdidx);
496 debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
502 * Reset the SDMMC with the RCC.SDMMCxRST register bit.
503 * This will reset the SDMMC to the reset state and the CPSM and DPSM
504 * to the Idle state. SDMMC is disabled, Signals Hiz.
506 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
509 reset_assert(&priv->reset_ctl);
511 reset_deassert(&priv->reset_ctl);
513 /* init the needed SDMMC register after reset */
514 writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
518 * Set the SDMMC in power-cycle state.
519 * This will make that the SDMMC_D[7:0],
520 * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
521 * supplied through the signal lines.
523 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
525 if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
526 SDMMC_POWER_PWRCTRL_CYCLE)
529 stm32_sdmmc2_reset(priv);
533 * set the SDMMC state Power-on: the card is clocked
534 * manage the SDMMC state control:
535 * Reset => Power-Cycle => Power-Off => Power
536 * PWRCTRL=10 PWCTRL=00 PWCTRL=11
538 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
541 readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK;
543 if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
546 /* warning: same PWRCTRL value after reset and for power-off state
547 * it is the reset state here = the only managed by the driver
549 if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
550 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
551 priv->base + SDMMC_POWER);
555 * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
556 * switch to Power-Off state: SDMCC disable, signals drive 1
558 writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
559 priv->base + SDMMC_POWER);
561 /* After the 1ms delay set the SDMMC to power-on */
563 writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
564 priv->base + SDMMC_POWER);
566 /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
569 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
570 static int stm32_sdmmc2_set_ios(struct udevice *dev)
572 struct mmc *mmc = mmc_get_mmc_dev(dev);
573 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
574 u32 desired = mmc->clock;
575 u32 sys_clock = clk_get_rate(&priv->clk);
578 debug("%s: bus_with = %d, clock = %d\n", __func__,
579 mmc->bus_width, mmc->clock);
581 if (mmc->clk_disable)
582 stm32_sdmmc2_pwrcycle(priv);
584 stm32_sdmmc2_pwron(priv);
587 * clk_div = 0 => command and data generated on SDMMCCLK falling edge
588 * clk_div > 0 and NEGEDGE = 0 => command and data generated on
589 * SDMMCCLK rising edge
590 * clk_div > 0 and NEGEDGE = 1 => command and data generated on
591 * SDMMCCLK falling edge
593 if (desired && ((sys_clock > desired) ||
594 IS_RISING_EDGE(priv->clk_reg_msk))) {
595 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
596 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
597 clk = SDMMC_CLKCR_CLKDIV_MAX;
600 if (mmc->bus_width == 4)
601 clk |= SDMMC_CLKCR_WIDBUS_4;
602 if (mmc->bus_width == 8)
603 clk |= SDMMC_CLKCR_WIDBUS_8;
605 writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
606 priv->base + SDMMC_CLKCR);
611 static int stm32_sdmmc2_getcd(struct udevice *dev)
613 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
615 debug("stm32_sdmmc2_getcd called\n");
617 if (dm_gpio_is_valid(&priv->cd_gpio))
618 return dm_gpio_get_value(&priv->cd_gpio);
623 static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
625 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
627 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
628 priv->base + SDMMC_POWER);
633 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
634 .send_cmd = stm32_sdmmc2_send_cmd,
635 .set_ios = stm32_sdmmc2_set_ios,
636 .get_cd = stm32_sdmmc2_getcd,
637 .host_power_cycle = stm32_sdmmc2_host_power_cycle,
640 static int stm32_sdmmc2_probe(struct udevice *dev)
642 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
643 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
644 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
645 struct mmc_config *cfg = &plat->cfg;
648 priv->base = dev_read_addr(dev);
649 if (priv->base == FDT_ADDR_T_NONE)
652 if (dev_read_bool(dev, "st,neg-edge"))
653 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
654 if (dev_read_bool(dev, "st,sig-dir"))
655 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
656 if (dev_read_bool(dev, "st,use-ckin"))
657 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
659 ret = clk_get_by_index(dev, 0, &priv->clk);
663 ret = clk_enable(&priv->clk);
667 ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
671 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
675 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
676 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
677 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
678 cfg->name = "STM32 SD/MMC";
681 if (cfg->f_max > 25000000)
682 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
684 switch (dev_read_u32_default(dev, "bus-width", 1)) {
686 cfg->host_caps |= MMC_MODE_8BIT;
689 cfg->host_caps |= MMC_MODE_4BIT;
694 pr_err("invalid \"bus-width\" property, force to 1\n");
697 upriv->mmc = &plat->mmc;
700 stm32_sdmmc2_reset(priv);
704 clk_disable(&priv->clk);
706 clk_free(&priv->clk);
711 static int stm32_sdmmc_bind(struct udevice *dev)
713 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
715 return mmc_bind(dev, &plat->mmc, &plat->cfg);
718 static const struct udevice_id stm32_sdmmc2_ids[] = {
719 { .compatible = "st,stm32-sdmmc2" },
723 U_BOOT_DRIVER(stm32_sdmmc2) = {
724 .name = "stm32_sdmmc2",
726 .of_match = stm32_sdmmc2_ids,
727 .ops = &stm32_sdmmc2_ops,
728 .probe = stm32_sdmmc2_probe,
729 .bind = stm32_sdmmc_bind,
730 .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
731 .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),