drivers/mmc/socfpga_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch/clock_manager.h>
   8 #include <asm/arch/system_manager.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dwmmc.h>
  12 #include <errno.h>
  13 #include <fdtdec.h>
  14 #include <linux/libfdt.h>
  15 #include <linux/err.h>
  16 #include <malloc.h>
  17 #include <reset.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static const struct socfpga_clock_manager *clock_manager_base =
  22                 (void *)SOCFPGA_CLKMGR_ADDRESS;
  23
  24 struct socfpga_dwmci_plat {
  25         struct mmc_config cfg;
  26         struct mmc mmc;
  27 };
  28
  29 /* socfpga implmentation specific driver private data */
  30 struct dwmci_socfpga_priv_data {
  31         struct dwmci_host       host;
  32         unsigned int            drvsel;
  33         unsigned int            smplsel;
  34 };
  35
  36 static void socfpga_dwmci_reset(struct udevice *dev)
  37 {
  38         struct reset_ctl_bulk reset_bulk;
  39         int ret;
  40
  41         ret = reset_get_bulk(dev, &reset_bulk);
  42         if (ret) {
  43                 dev_warn(dev, "Can't get reset: %d\n", ret);
  44                 return;
  45         }
  46
  47         reset_deassert_bulk(&reset_bulk);
  48 }
  49
  50 static void socfpga_dwmci_clksel(struct dwmci_host *host)
  51 {
  52         struct dwmci_socfpga_priv_data *priv = host->priv;
  53         u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
  54                          ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
  55
  56         /* Disable SDMMC clock. */
  57         clrbits_le32(&clock_manager_base->per_pll.en,
  58                 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  59
  60         debug("%s: drvsel %d smplsel %d\n", __func__,
  61               priv->drvsel, priv->smplsel);
  62         writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
  63
  64         debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
  65                 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
  66
  67         /* Enable SDMMC clock */
  68         setbits_le32(&clock_manager_base->per_pll.en,
  69                 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  70 }
  71
  72 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
  73 {
  74         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  75         struct dwmci_host *host = &priv->host;
  76 #if CONFIG_IS_ENABLED(CLK)
  77         struct clk clk;
  78         int ret;
  79
  80         ret = clk_get_by_index(dev, 1, &clk);
  81         if (ret)
  82                 return ret;
  83
  84         host->bus_hz = clk_get_rate(&clk);
  85
  86         clk_free(&clk);
  87 #else
  88         /* Fixed clock divide by 4 which due to the SDMMC wrapper */
  89         host->bus_hz = cm_get_mmc_controller_clk_hz();
  90 #endif
  91         if (host->bus_hz == 0) {
  92                 printf("DWMMC: MMC clock is zero!");
  93                 return -EINVAL;
  94         }
  95
  96         return 0;
  97 }
  98
  99 static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
 100 {
 101         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
 102         struct dwmci_host *host = &priv->host;
 103         int fifo_depth;
 104
 105         fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 106                                     "fifo-depth", 0);
 107         if (fifo_depth < 0) {
 108                 printf("DWMMC: Can't get FIFO depth\n");
 109                 return -EINVAL;
 110         }
 111
 112         host->name = dev->name;
 113         host->ioaddr = (void *)devfdt_get_addr(dev);
 114         host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 115                                         "bus-width", 4);
 116         host->clksel = socfpga_dwmci_clksel;
 117
 118         /*
 119          * TODO(sjg@chromium.org): Remove the need for this hack.
 120          * We only have one dwmmc block on gen5 SoCFPGA.
 121          */
 122         host->dev_index = 0;
 123         host->fifoth_val = MSIZE(0x2) |
 124                 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
 125         priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 126                                        "drvsel", 3);
 127         priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 128                                         "smplsel", 0);
 129         host->priv = priv;
 130
 131         return 0;
 132 }
 133
 134 static int socfpga_dwmmc_probe(struct udevice *dev)
 135 {
 136 #ifdef CONFIG_BLK
 137         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 138 #endif
 139         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 140         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
 141         struct dwmci_host *host = &priv->host;
 142         int ret;
 143
 144         ret = socfpga_dwmmc_get_clk_rate(dev);
 145         if (ret)
 146                 return ret;
 147
 148         socfpga_dwmci_reset(dev);
 149
 150 #ifdef CONFIG_BLK
 151         dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
 152         host->mmc = &plat->mmc;
 153 #else
 154
 155         ret = add_dwmci(host, host->bus_hz, 400000);
 156         if (ret)
 157                 return ret;
 158 #endif
 159         host->mmc->priv = &priv->host;
 160         upriv->mmc = host->mmc;
 161         host->mmc->dev = dev;
 162
 163         return dwmci_probe(dev);
 164 }
 165
 166 static int socfpga_dwmmc_bind(struct udevice *dev)
 167 {
 168 #ifdef CONFIG_BLK
 169         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 170         int ret;
 171
 172         ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
 173         if (ret)
 174                 return ret;
 175 #endif
 176
 177         return 0;
 178 }
 179
 180 static const struct udevice_id socfpga_dwmmc_ids[] = {
 181         { .compatible = "altr,socfpga-dw-mshc" },
 182         { }
 183 };
 184
 185 U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
 186         .name           = "socfpga_dwmmc",
 187         .id             = UCLASS_MMC,
 188         .of_match       = socfpga_dwmmc_ids,
 189         .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
 190         .ops            = &dm_dwmci_ops,
 191         .bind           = socfpga_dwmmc_bind,
 192         .probe          = socfpga_dwmmc_probe,
 193         .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
 194         .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
 195 };