1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Altera Corporation <www.altera.com>
7 #include <asm/arch/clock_manager.h>
8 #include <asm/arch/system_manager.h>
14 #include <linux/libfdt.h>
15 #include <linux/err.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static const struct socfpga_clock_manager *clock_manager_base =
22 (void *)SOCFPGA_CLKMGR_ADDRESS;
23 static const struct socfpga_system_manager *system_manager_base =
24 (void *)SOCFPGA_SYSMGR_ADDRESS;
26 struct socfpga_dwmci_plat {
27 struct mmc_config cfg;
31 /* socfpga implmentation specific driver private data */
32 struct dwmci_socfpga_priv_data {
33 struct dwmci_host host;
38 static void socfpga_dwmci_reset(struct udevice *dev)
40 struct reset_ctl_bulk reset_bulk;
43 ret = reset_get_bulk(dev, &reset_bulk);
45 dev_warn(dev, "Can't get reset: %d\n", ret);
49 reset_deassert_bulk(&reset_bulk);
52 static void socfpga_dwmci_clksel(struct dwmci_host *host)
54 struct dwmci_socfpga_priv_data *priv = host->priv;
55 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
56 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
58 /* Disable SDMMC clock. */
59 clrbits_le32(&clock_manager_base->per_pll.en,
60 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
62 debug("%s: drvsel %d smplsel %d\n", __func__,
63 priv->drvsel, priv->smplsel);
64 writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
66 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
67 readl(&system_manager_base->sdmmcgrp_ctrl));
69 /* Enable SDMMC clock */
70 setbits_le32(&clock_manager_base->per_pll.en,
71 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
74 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
76 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
77 struct dwmci_host *host = &priv->host;
78 #if CONFIG_IS_ENABLED(CLK)
82 ret = clk_get_by_index(dev, 1, &clk);
86 host->bus_hz = clk_get_rate(&clk);
90 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
91 host->bus_hz = cm_get_mmc_controller_clk_hz();
93 if (host->bus_hz == 0) {
94 printf("DWMMC: MMC clock is zero!");
101 static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
103 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
104 struct dwmci_host *host = &priv->host;
107 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
109 if (fifo_depth < 0) {
110 printf("DWMMC: Can't get FIFO depth\n");
114 host->name = dev->name;
115 host->ioaddr = (void *)devfdt_get_addr(dev);
116 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
118 host->clksel = socfpga_dwmci_clksel;
121 * TODO(sjg@chromium.org): Remove the need for this hack.
122 * We only have one dwmmc block on gen5 SoCFPGA.
125 host->fifoth_val = MSIZE(0x2) |
126 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
127 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
129 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
136 static int socfpga_dwmmc_probe(struct udevice *dev)
139 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
141 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
142 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
143 struct dwmci_host *host = &priv->host;
146 ret = socfpga_dwmmc_get_clk_rate(dev);
150 socfpga_dwmci_reset(dev);
153 dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
154 host->mmc = &plat->mmc;
157 ret = add_dwmci(host, host->bus_hz, 400000);
161 host->mmc->priv = &priv->host;
162 upriv->mmc = host->mmc;
163 host->mmc->dev = dev;
165 return dwmci_probe(dev);
168 static int socfpga_dwmmc_bind(struct udevice *dev)
171 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
174 ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
182 static const struct udevice_id socfpga_dwmmc_ids[] = {
183 { .compatible = "altr,socfpga-dw-mshc" },
187 U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
188 .name = "socfpga_dwmmc",
190 .of_match = socfpga_dwmmc_ids,
191 .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
192 .ops = &dm_dwmci_ops,
193 .bind = socfpga_dwmmc_bind,
194 .probe = socfpga_dwmmc_probe,
195 .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
196 .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),