1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Altera Corporation <www.altera.com>
8 #include <asm/arch/clock_manager.h>
9 #include <asm/arch/system_manager.h>
15 #include <dm/device_compat.h>
16 #include <linux/libfdt.h>
17 #include <linux/err.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 struct socfpga_dwmci_plat {
24 struct mmc_config cfg;
28 /* socfpga implmentation specific driver private data */
29 struct dwmci_socfpga_priv_data {
30 struct dwmci_host host;
35 static void socfpga_dwmci_reset(struct udevice *dev)
37 struct reset_ctl_bulk reset_bulk;
40 ret = reset_get_bulk(dev, &reset_bulk);
42 dev_warn(dev, "Can't get reset: %d\n", ret);
46 reset_deassert_bulk(&reset_bulk);
49 static void socfpga_dwmci_clksel(struct dwmci_host *host)
51 struct dwmci_socfpga_priv_data *priv = host->priv;
52 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
53 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
55 /* Disable SDMMC clock. */
56 clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
57 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
59 debug("%s: drvsel %d smplsel %d\n", __func__,
60 priv->drvsel, priv->smplsel);
61 writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
63 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
64 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
66 /* Enable SDMMC clock */
67 setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
68 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
71 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
73 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
74 struct dwmci_host *host = &priv->host;
75 #if CONFIG_IS_ENABLED(CLK)
79 ret = clk_get_by_index(dev, 1, &clk);
83 host->bus_hz = clk_get_rate(&clk);
87 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
88 host->bus_hz = cm_get_mmc_controller_clk_hz();
90 if (host->bus_hz == 0) {
91 printf("DWMMC: MMC clock is zero!");
98 static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
100 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
101 struct dwmci_host *host = &priv->host;
104 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
106 if (fifo_depth < 0) {
107 printf("DWMMC: Can't get FIFO depth\n");
111 host->name = dev->name;
112 host->ioaddr = dev_read_addr_ptr(dev);
113 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
115 host->clksel = socfpga_dwmci_clksel;
118 * TODO(sjg@chromium.org): Remove the need for this hack.
119 * We only have one dwmmc block on gen5 SoCFPGA.
122 host->fifoth_val = MSIZE(0x2) |
123 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
124 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
126 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
133 static int socfpga_dwmmc_probe(struct udevice *dev)
136 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
138 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
139 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
140 struct dwmci_host *host = &priv->host;
143 ret = socfpga_dwmmc_get_clk_rate(dev);
147 socfpga_dwmci_reset(dev);
150 dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
151 host->mmc = &plat->mmc;
154 ret = add_dwmci(host, host->bus_hz, 400000);
158 host->mmc->priv = &priv->host;
159 upriv->mmc = host->mmc;
160 host->mmc->dev = dev;
162 return dwmci_probe(dev);
165 static int socfpga_dwmmc_bind(struct udevice *dev)
168 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
171 ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
179 static const struct udevice_id socfpga_dwmmc_ids[] = {
180 { .compatible = "altr,socfpga-dw-mshc" },
184 U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
185 .name = "socfpga_dwmmc",
187 .of_match = socfpga_dwmmc_ids,
188 .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
189 .ops = &dm_dwmci_ops,
190 .bind = socfpga_dwmmc_bind,
191 .probe = socfpga_dwmmc_probe,
192 .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
193 .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),