4 * Copyright (C) 2011 Renesas Solutions Corp.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
17 #include <asm/errno.h>
21 #define DRIVER_NAME "sh_mmcif"
23 static int sh_mmcif_intr(void *dev_id)
25 struct sh_mmcif_host *host = dev_id;
28 state = sh_mmcif_read(&host->regs->ce_int);
29 state &= sh_mmcif_read(&host->regs->ce_int_mask);
31 if (state & INT_RBSYE) {
32 sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
33 sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
35 } else if (state & INT_CRSPE) {
36 sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
37 sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
38 /* one more interrupt (INT_RBSYE) */
39 if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
42 } else if (state & INT_BUFREN) {
43 sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
44 sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
46 } else if (state & INT_BUFWEN) {
47 sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
48 sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
50 } else if (state & INT_CMD12DRE) {
51 sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
52 INT_BUFRE), &host->regs->ce_int);
53 sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
55 } else if (state & INT_BUFRE) {
56 sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
57 sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
59 } else if (state & INT_DTRANE) {
60 sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
61 sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
63 } else if (state & INT_CMD12RBE) {
64 sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
66 sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
68 } else if (state & INT_ERR_STS) {
70 sh_mmcif_write(~state, &host->regs->ce_int);
71 sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
78 debug("%s: int err state = %08x\n", DRIVER_NAME, state);
84 static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
86 int timeout = 10000000;
95 if (!sh_mmcif_intr(host))
98 udelay(1); /* 1 usec */
101 return 1; /* Return value: NOT 0 = complete waiting */
104 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
106 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
107 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
112 if (clk == CLKDEV_EMMC_DATA)
113 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
115 sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
116 clk) - 1) - 1) << 16,
117 &host->regs->ce_clk_ctrl);
118 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
121 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
125 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
128 sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
129 sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
130 sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
131 &host->regs->ce_clk_ctrl);
133 sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
136 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
139 int ret, timeout = 10000000;
144 state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
145 state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
146 debug("%s: ERR HOST_STS1 = %08x\n", \
147 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
148 debug("%s: ERR HOST_STS2 = %08x\n", \
149 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
151 if (state1 & STS1_CMDSEQ) {
152 debug("%s: Forced end of command sequence\n", DRIVER_NAME);
153 sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
154 sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
158 printf(DRIVER_NAME": Forceed end of " \
159 "command sequence timeout err\n");
162 if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
166 sh_mmcif_sync_reset(host);
170 if (state2 & STS2_CRC_ERR)
172 else if (state2 & STS2_TIMEOUT_ERR)
179 static int sh_mmcif_single_read(struct sh_mmcif_host *host,
180 struct mmc_data *data)
184 unsigned long *p = (unsigned long *)data->dest;
186 if ((unsigned long)p & 0x00000001) {
187 printf("%s: The data pointer is unaligned.", __func__);
193 /* buf read enable */
194 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
195 time = mmcif_wait_interrupt_flag(host);
196 if (time == 0 || host->sd_error != 0)
197 return sh_mmcif_error_manage(host);
200 blocksize = (BLOCK_SIZE_MASK &
201 sh_mmcif_read(&host->regs->ce_block_set)) + 3;
202 for (i = 0; i < blocksize / 4; i++)
203 *p++ = sh_mmcif_read(&host->regs->ce_data);
205 /* buffer read end */
206 sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
207 time = mmcif_wait_interrupt_flag(host);
208 if (time == 0 || host->sd_error != 0)
209 return sh_mmcif_error_manage(host);
215 static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
216 struct mmc_data *data)
220 unsigned long *p = (unsigned long *)data->dest;
222 if ((unsigned long)p & 0x00000001) {
223 printf("%s: The data pointer is unaligned.", __func__);
228 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
229 for (j = 0; j < data->blocks; j++) {
230 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
231 time = mmcif_wait_interrupt_flag(host);
232 if (time == 0 || host->sd_error != 0)
233 return sh_mmcif_error_manage(host);
236 for (i = 0; i < blocksize / 4; i++)
237 *p++ = sh_mmcif_read(&host->regs->ce_data);
244 static int sh_mmcif_single_write(struct sh_mmcif_host *host,
245 struct mmc_data *data)
249 const unsigned long *p = (unsigned long *)data->dest;
251 if ((unsigned long)p & 0x00000001) {
252 printf("%s: The data pointer is unaligned.", __func__);
257 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
259 time = mmcif_wait_interrupt_flag(host);
260 if (time == 0 || host->sd_error != 0)
261 return sh_mmcif_error_manage(host);
264 blocksize = (BLOCK_SIZE_MASK &
265 sh_mmcif_read(&host->regs->ce_block_set)) + 3;
266 for (i = 0; i < blocksize / 4; i++)
267 sh_mmcif_write(*p++, &host->regs->ce_data);
269 /* buffer write end */
270 sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
272 time = mmcif_wait_interrupt_flag(host);
273 if (time == 0 || host->sd_error != 0)
274 return sh_mmcif_error_manage(host);
280 static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
281 struct mmc_data *data)
285 const unsigned long *p = (unsigned long *)data->dest;
287 if ((unsigned long)p & 0x00000001) {
288 printf("%s: The data pointer is unaligned.", __func__);
293 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
294 for (j = 0; j < data->blocks; j++) {
295 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
297 time = mmcif_wait_interrupt_flag(host);
299 if (time == 0 || host->sd_error != 0)
300 return sh_mmcif_error_manage(host);
303 for (i = 0; i < blocksize / 4; i++)
304 sh_mmcif_write(*p++, &host->regs->ce_data);
311 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
314 if (cmd->resp_type & MMC_RSP_136) {
315 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
316 cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
317 cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
318 cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
319 debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
320 cmd->response[1], cmd->response[2], cmd->response[3]);
322 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
326 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
329 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
332 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
333 struct mmc_data *data, struct mmc_cmd *cmd)
336 u32 opc = cmd->cmdidx;
338 /* Response Type check */
339 switch (cmd->resp_type) {
341 tmp |= CMD_SET_RTYP_NO;
346 tmp |= CMD_SET_RTYP_6B;
349 tmp |= CMD_SET_RTYP_17B;
352 printf(DRIVER_NAME": Not support type response.\n");
357 if (opc == MMC_CMD_SWITCH)
363 switch (host->bus_width) {
364 case MMC_BUS_WIDTH_1:
365 tmp |= CMD_SET_DATW_1;
367 case MMC_BUS_WIDTH_4:
368 tmp |= CMD_SET_DATW_4;
370 case MMC_BUS_WIDTH_8:
371 tmp |= CMD_SET_DATW_8;
374 printf(DRIVER_NAME": Not support bus width.\n");
379 if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
380 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
383 if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
384 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
385 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
386 sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
388 /* RIDXC[1:0] check bits */
389 if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
390 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
391 tmp |= CMD_SET_RIDXC_BITS;
392 /* RCRC7C[1:0] check bits */
393 if (opc == MMC_CMD_SEND_OP_COND)
394 tmp |= CMD_SET_CRC7C_BITS;
395 /* RCRC7C[1:0] internal CRC7 */
396 if (opc == MMC_CMD_ALL_SEND_CID ||
397 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
398 tmp |= CMD_SET_CRC7C_INTERNAL;
400 return opc = ((opc << 24) | tmp);
403 static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
404 struct mmc_data *data, u16 opc)
409 case MMC_CMD_READ_MULTIPLE_BLOCK:
410 ret = sh_mmcif_multi_read(host, data);
412 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
413 ret = sh_mmcif_multi_write(host, data);
415 case MMC_CMD_WRITE_SINGLE_BLOCK:
416 ret = sh_mmcif_single_write(host, data);
418 case MMC_CMD_READ_SINGLE_BLOCK:
419 case MMC_CMD_SEND_EXT_CSD:
420 ret = sh_mmcif_single_read(host, data);
423 printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
430 static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
431 struct mmc_data *data, struct mmc_cmd *cmd)
434 int ret = 0, mask = 0;
435 u32 opc = cmd->cmdidx;
437 if (opc == MMC_CMD_STOP_TRANSMISSION) {
438 /* MMCIF sends the STOP command automatically */
439 if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
440 sh_mmcif_bitset(MASK_MCMD12DRE,
441 &host->regs->ce_int_mask);
443 sh_mmcif_bitset(MASK_MCMD12RBE,
444 &host->regs->ce_int_mask);
446 time = mmcif_wait_interrupt_flag(host);
447 if (time == 0 || host->sd_error != 0)
448 return sh_mmcif_error_manage(host);
450 sh_mmcif_get_cmd12response(host, cmd);
453 if (opc == MMC_CMD_SWITCH)
458 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
459 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
460 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
461 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
464 sh_mmcif_write(0, &host->regs->ce_block_set);
465 sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
467 opc = sh_mmcif_set_cmd(host, data, cmd);
469 sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
470 sh_mmcif_write(mask, &host->regs->ce_int_mask);
472 debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
474 sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
477 sh_mmcif_write(opc, &host->regs->ce_cmd_set);
479 time = mmcif_wait_interrupt_flag(host);
481 return sh_mmcif_error_manage(host);
483 if (host->sd_error) {
484 switch (cmd->cmdidx) {
485 case MMC_CMD_ALL_SEND_CID:
486 case MMC_CMD_SELECT_CARD:
487 case MMC_CMD_APP_CMD:
491 printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
492 ret = sh_mmcif_error_manage(host);
501 if (!(opc & 0x00C00000))
504 if (host->wait_int == 1) {
505 sh_mmcif_get_response(host, cmd);
509 ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
510 host->last_cmd = cmd->cmdidx;
515 static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
516 struct mmc_data *data)
518 struct sh_mmcif_host *host = mmc->priv;
523 switch (cmd->cmdidx) {
524 case MMC_CMD_APP_CMD:
526 case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
531 /* send_if_cond cmd (not support) */
538 ret = sh_mmcif_start_cmd(host, data, cmd);
544 static void sh_mmcif_set_ios(struct mmc *mmc)
546 struct sh_mmcif_host *host = mmc->priv;
549 sh_mmcif_clock_control(host, mmc->clock);
551 if (mmc->bus_width == 8)
552 host->bus_width = MMC_BUS_WIDTH_8;
553 else if (mmc->bus_width == 4)
554 host->bus_width = MMC_BUS_WIDTH_4;
556 host->bus_width = MMC_BUS_WIDTH_1;
558 debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
561 static int sh_mmcif_init(struct mmc *mmc)
563 struct sh_mmcif_host *host = mmc->priv;
565 sh_mmcif_sync_reset(host);
566 sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
570 static const struct mmc_ops sh_mmcif_ops = {
571 .send_cmd = sh_mmcif_request,
572 .set_ios = sh_mmcif_set_ios,
573 .init = sh_mmcif_init,
576 static struct mmc_config sh_mmcif_cfg = {
578 .ops = &sh_mmcif_ops,
579 .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
580 MMC_MODE_8BIT | MMC_MODE_HC,
581 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
582 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
585 int mmcif_mmc_init(void)
588 struct sh_mmcif_host *host = NULL;
590 host = malloc(sizeof(struct sh_mmcif_host));
593 memset(host, 0, sizeof(*host));
595 host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
596 host->clk = CONFIG_SH_MMCIF_CLK;
598 sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
599 sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
601 mmc = mmc_create(&sh_mmcif_cfg, host);