1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011 Renesas Solutions Corp.
16 #include <linux/errno.h>
17 #include <linux/compat.h>
19 #include <linux/sizes.h>
22 #define DRIVER_NAME "sh_mmcif"
24 static int sh_mmcif_intr(void *dev_id)
26 struct sh_mmcif_host *host = dev_id;
29 state = sh_mmcif_read(&host->regs->ce_int);
30 state &= sh_mmcif_read(&host->regs->ce_int_mask);
32 if (state & INT_RBSYE) {
33 sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
34 sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
36 } else if (state & INT_CRSPE) {
37 sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
38 sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
39 /* one more interrupt (INT_RBSYE) */
40 if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
43 } else if (state & INT_BUFREN) {
44 sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
45 sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
47 } else if (state & INT_BUFWEN) {
48 sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
49 sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
51 } else if (state & INT_CMD12DRE) {
52 sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
53 INT_BUFRE), &host->regs->ce_int);
54 sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
56 } else if (state & INT_BUFRE) {
57 sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
58 sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
60 } else if (state & INT_DTRANE) {
61 sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
62 sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
64 } else if (state & INT_CMD12RBE) {
65 sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
67 sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
69 } else if (state & INT_ERR_STS) {
71 sh_mmcif_write(~state, &host->regs->ce_int);
72 sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
79 debug("%s: int err state = %08x\n", DRIVER_NAME, state);
85 static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
87 int timeout = 10000000;
96 if (!sh_mmcif_intr(host))
99 udelay(1); /* 1 usec */
102 return 1; /* Return value: NOT 0 = complete waiting */
105 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
107 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
108 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
113 if (clk == CLKDEV_EMMC_DATA)
114 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
116 sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
117 clk) - 1) - 1) << 16,
118 &host->regs->ce_clk_ctrl);
119 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
122 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
126 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
129 sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
130 sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
131 sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
132 &host->regs->ce_clk_ctrl);
134 sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
137 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
140 int ret, timeout = 10000000;
145 state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
146 state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
147 debug("%s: ERR HOST_STS1 = %08x\n", \
148 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
149 debug("%s: ERR HOST_STS2 = %08x\n", \
150 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
152 if (state1 & STS1_CMDSEQ) {
153 debug("%s: Forced end of command sequence\n", DRIVER_NAME);
154 sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
155 sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
159 printf(DRIVER_NAME": Forceed end of " \
160 "command sequence timeout err\n");
163 if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
167 sh_mmcif_sync_reset(host);
171 if (state2 & STS2_CRC_ERR)
173 else if (state2 & STS2_TIMEOUT_ERR)
180 static int sh_mmcif_single_read(struct sh_mmcif_host *host,
181 struct mmc_data *data)
185 unsigned long *p = (unsigned long *)data->dest;
187 if ((unsigned long)p & 0x00000001) {
188 printf("%s: The data pointer is unaligned.", __func__);
194 /* buf read enable */
195 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
196 time = mmcif_wait_interrupt_flag(host);
197 if (time == 0 || host->sd_error != 0)
198 return sh_mmcif_error_manage(host);
201 blocksize = (BLOCK_SIZE_MASK &
202 sh_mmcif_read(&host->regs->ce_block_set)) + 3;
203 for (i = 0; i < blocksize / 4; i++)
204 *p++ = sh_mmcif_read(&host->regs->ce_data);
206 /* buffer read end */
207 sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
208 time = mmcif_wait_interrupt_flag(host);
209 if (time == 0 || host->sd_error != 0)
210 return sh_mmcif_error_manage(host);
216 static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
217 struct mmc_data *data)
221 unsigned long *p = (unsigned long *)data->dest;
223 if ((unsigned long)p & 0x00000001) {
224 printf("%s: The data pointer is unaligned.", __func__);
229 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
230 for (j = 0; j < data->blocks; j++) {
231 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
232 time = mmcif_wait_interrupt_flag(host);
233 if (time == 0 || host->sd_error != 0)
234 return sh_mmcif_error_manage(host);
237 for (i = 0; i < blocksize / 4; i++)
238 *p++ = sh_mmcif_read(&host->regs->ce_data);
245 static int sh_mmcif_single_write(struct sh_mmcif_host *host,
246 struct mmc_data *data)
250 const unsigned long *p = (unsigned long *)data->dest;
252 if ((unsigned long)p & 0x00000001) {
253 printf("%s: The data pointer is unaligned.", __func__);
258 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
260 time = mmcif_wait_interrupt_flag(host);
261 if (time == 0 || host->sd_error != 0)
262 return sh_mmcif_error_manage(host);
265 blocksize = (BLOCK_SIZE_MASK &
266 sh_mmcif_read(&host->regs->ce_block_set)) + 3;
267 for (i = 0; i < blocksize / 4; i++)
268 sh_mmcif_write(*p++, &host->regs->ce_data);
270 /* buffer write end */
271 sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
273 time = mmcif_wait_interrupt_flag(host);
274 if (time == 0 || host->sd_error != 0)
275 return sh_mmcif_error_manage(host);
281 static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
282 struct mmc_data *data)
286 const unsigned long *p = (unsigned long *)data->dest;
288 if ((unsigned long)p & 0x00000001) {
289 printf("%s: The data pointer is unaligned.", __func__);
294 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
295 for (j = 0; j < data->blocks; j++) {
296 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
298 time = mmcif_wait_interrupt_flag(host);
300 if (time == 0 || host->sd_error != 0)
301 return sh_mmcif_error_manage(host);
304 for (i = 0; i < blocksize / 4; i++)
305 sh_mmcif_write(*p++, &host->regs->ce_data);
312 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
315 if (cmd->resp_type & MMC_RSP_136) {
316 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
317 cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
318 cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
319 cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
320 debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
321 cmd->response[1], cmd->response[2], cmd->response[3]);
323 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
327 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
330 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
333 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
334 struct mmc_data *data, struct mmc_cmd *cmd)
337 u32 opc = cmd->cmdidx;
339 /* Response Type check */
340 switch (cmd->resp_type) {
342 tmp |= CMD_SET_RTYP_NO;
347 tmp |= CMD_SET_RTYP_6B;
350 tmp |= CMD_SET_RTYP_17B;
353 printf(DRIVER_NAME": Not support type response.\n");
358 if (opc == MMC_CMD_SWITCH)
364 switch (host->bus_width) {
365 case MMC_BUS_WIDTH_1:
366 tmp |= CMD_SET_DATW_1;
368 case MMC_BUS_WIDTH_4:
369 tmp |= CMD_SET_DATW_4;
371 case MMC_BUS_WIDTH_8:
372 tmp |= CMD_SET_DATW_8;
375 printf(DRIVER_NAME": Not support bus width.\n");
380 if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
381 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
384 if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
385 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
386 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
387 sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
389 /* RIDXC[1:0] check bits */
390 if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
391 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
392 tmp |= CMD_SET_RIDXC_BITS;
393 /* RCRC7C[1:0] check bits */
394 if (opc == MMC_CMD_SEND_OP_COND)
395 tmp |= CMD_SET_CRC7C_BITS;
396 /* RCRC7C[1:0] internal CRC7 */
397 if (opc == MMC_CMD_ALL_SEND_CID ||
398 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
399 tmp |= CMD_SET_CRC7C_INTERNAL;
401 return opc = ((opc << 24) | tmp);
404 static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
405 struct mmc_data *data, u16 opc)
410 case MMC_CMD_READ_MULTIPLE_BLOCK:
411 ret = sh_mmcif_multi_read(host, data);
413 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
414 ret = sh_mmcif_multi_write(host, data);
416 case MMC_CMD_WRITE_SINGLE_BLOCK:
417 ret = sh_mmcif_single_write(host, data);
419 case MMC_CMD_READ_SINGLE_BLOCK:
420 case MMC_CMD_SEND_EXT_CSD:
421 ret = sh_mmcif_single_read(host, data);
424 printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
431 static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
432 struct mmc_data *data, struct mmc_cmd *cmd)
435 int ret = 0, mask = 0;
436 u32 opc = cmd->cmdidx;
438 if (opc == MMC_CMD_STOP_TRANSMISSION) {
439 /* MMCIF sends the STOP command automatically */
440 if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
441 sh_mmcif_bitset(MASK_MCMD12DRE,
442 &host->regs->ce_int_mask);
444 sh_mmcif_bitset(MASK_MCMD12RBE,
445 &host->regs->ce_int_mask);
447 time = mmcif_wait_interrupt_flag(host);
448 if (time == 0 || host->sd_error != 0)
449 return sh_mmcif_error_manage(host);
451 sh_mmcif_get_cmd12response(host, cmd);
454 if (opc == MMC_CMD_SWITCH)
459 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
460 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
461 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
462 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
465 sh_mmcif_write(0, &host->regs->ce_block_set);
466 sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
468 opc = sh_mmcif_set_cmd(host, data, cmd);
470 sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
471 sh_mmcif_write(mask, &host->regs->ce_int_mask);
473 debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
475 sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
478 sh_mmcif_write(opc, &host->regs->ce_cmd_set);
480 time = mmcif_wait_interrupt_flag(host);
482 return sh_mmcif_error_manage(host);
484 if (host->sd_error) {
485 switch (cmd->cmdidx) {
486 case MMC_CMD_ALL_SEND_CID:
487 case MMC_CMD_SELECT_CARD:
488 case MMC_CMD_APP_CMD:
492 printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
493 ret = sh_mmcif_error_manage(host);
502 if (!(opc & 0x00C00000))
505 if (host->wait_int == 1) {
506 sh_mmcif_get_response(host, cmd);
510 ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
511 host->last_cmd = cmd->cmdidx;
516 static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
517 struct mmc_cmd *cmd, struct mmc_data *data)
523 switch (cmd->cmdidx) {
524 case MMC_CMD_APP_CMD:
526 case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
531 /* send_if_cond cmd (not support) */
538 ret = sh_mmcif_start_cmd(host, data, cmd);
544 static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
547 sh_mmcif_clock_control(host, mmc->clock);
549 if (mmc->bus_width == 8)
550 host->bus_width = MMC_BUS_WIDTH_8;
551 else if (mmc->bus_width == 4)
552 host->bus_width = MMC_BUS_WIDTH_4;
554 host->bus_width = MMC_BUS_WIDTH_1;
556 debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
561 static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
563 sh_mmcif_sync_reset(host);
564 sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
568 #ifndef CONFIG_DM_MMC
569 static void *mmc_priv(struct mmc *mmc)
571 return (void *)mmc->priv;
574 static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
575 struct mmc_data *data)
577 struct sh_mmcif_host *host = mmc_priv(mmc);
579 return sh_mmcif_send_cmd_common(host, cmd, data);
582 static int sh_mmcif_set_ios(struct mmc *mmc)
584 struct sh_mmcif_host *host = mmc_priv(mmc);
586 return sh_mmcif_set_ios_common(host, mmc);
589 static int sh_mmcif_initialize(struct mmc *mmc)
591 struct sh_mmcif_host *host = mmc_priv(mmc);
593 return sh_mmcif_initialize_common(host);
596 static const struct mmc_ops sh_mmcif_ops = {
597 .send_cmd = sh_mmcif_send_cmd,
598 .set_ios = sh_mmcif_set_ios,
599 .init = sh_mmcif_initialize,
602 static struct mmc_config sh_mmcif_cfg = {
604 .ops = &sh_mmcif_ops,
605 .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
607 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
608 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
611 int mmcif_mmc_init(void)
614 struct sh_mmcif_host *host = NULL;
616 host = malloc(sizeof(struct sh_mmcif_host));
619 memset(host, 0, sizeof(*host));
621 host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
622 host->clk = CONFIG_SH_MMCIF_CLK;
624 sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
625 sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
627 mmc = mmc_create(&sh_mmcif_cfg, host);
637 struct sh_mmcif_plat {
638 struct mmc_config cfg;
642 int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
643 struct mmc_data *data)
645 struct sh_mmcif_host *host = dev_get_priv(dev);
647 return sh_mmcif_send_cmd_common(host, cmd, data);
650 int sh_mmcif_dm_set_ios(struct udevice *dev)
652 struct sh_mmcif_host *host = dev_get_priv(dev);
653 struct mmc *mmc = mmc_get_mmc_dev(dev);
655 return sh_mmcif_set_ios_common(host, mmc);
658 static const struct dm_mmc_ops sh_mmcif_dm_ops = {
659 .send_cmd = sh_mmcif_dm_send_cmd,
660 .set_ios = sh_mmcif_dm_set_ios,
663 static int sh_mmcif_dm_bind(struct udevice *dev)
665 struct sh_mmcif_plat *plat = dev_get_platdata(dev);
667 return mmc_bind(dev, &plat->mmc, &plat->cfg);
670 static int sh_mmcif_dm_probe(struct udevice *dev)
672 struct sh_mmcif_plat *plat = dev_get_platdata(dev);
673 struct sh_mmcif_host *host = dev_get_priv(dev);
674 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
675 struct clk sh_mmcif_clk;
679 base = devfdt_get_addr(dev);
680 if (base == FDT_ADDR_T_NONE)
683 host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
687 ret = clk_get_by_index(dev, 0, &sh_mmcif_clk);
689 debug("failed to get clock, ret=%d\n", ret);
693 ret = clk_enable(&sh_mmcif_clk);
695 debug("failed to enable clock, ret=%d\n", ret);
699 host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
701 plat->cfg.name = dev->name;
702 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
704 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
707 plat->cfg.host_caps |= MMC_MODE_8BIT;
710 plat->cfg.host_caps |= MMC_MODE_4BIT;
715 dev_err(dev, "Invalid \"bus-width\" value\n");
719 sh_mmcif_initialize_common(host);
721 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
722 plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
723 plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
724 plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
726 upriv->mmc = &plat->mmc;
731 static const struct udevice_id sh_mmcif_sd_match[] = {
732 { .compatible = "renesas,sh-mmcif" },
736 U_BOOT_DRIVER(sh_mmcif_mmc) = {
739 .of_match = sh_mmcif_sd_match,
740 .bind = sh_mmcif_dm_bind,
741 .probe = sh_mmcif_dm_probe,
742 .priv_auto_alloc_size = sizeof(struct sh_mmcif_host),
743 .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat),
744 .ops = &sh_mmcif_dm_ops,