1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011 Renesas Solutions Corp.
16 #include <dm/device_compat.h>
17 #include <linux/errno.h>
18 #include <linux/compat.h>
20 #include <linux/sizes.h>
23 #define DRIVER_NAME "sh_mmcif"
25 static int sh_mmcif_intr(void *dev_id)
27 struct sh_mmcif_host *host = dev_id;
30 state = sh_mmcif_read(&host->regs->ce_int);
31 state &= sh_mmcif_read(&host->regs->ce_int_mask);
33 if (state & INT_RBSYE) {
34 sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
35 sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
37 } else if (state & INT_CRSPE) {
38 sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
39 sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
40 /* one more interrupt (INT_RBSYE) */
41 if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
44 } else if (state & INT_BUFREN) {
45 sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
46 sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
48 } else if (state & INT_BUFWEN) {
49 sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
50 sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
52 } else if (state & INT_CMD12DRE) {
53 sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
54 INT_BUFRE), &host->regs->ce_int);
55 sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
57 } else if (state & INT_BUFRE) {
58 sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
59 sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
61 } else if (state & INT_DTRANE) {
62 sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
63 sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
65 } else if (state & INT_CMD12RBE) {
66 sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
68 sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
70 } else if (state & INT_ERR_STS) {
72 sh_mmcif_write(~state, &host->regs->ce_int);
73 sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
80 debug("%s: int err state = %08x\n", DRIVER_NAME, state);
86 static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
88 int timeout = 10000000;
97 if (!sh_mmcif_intr(host))
100 udelay(1); /* 1 usec */
103 return 1; /* Return value: NOT 0 = complete waiting */
106 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
108 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
109 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
114 if (clk == CLKDEV_EMMC_DATA)
115 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
117 sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
118 clk) - 1) - 1) << 16,
119 &host->regs->ce_clk_ctrl);
120 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
123 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
127 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
130 sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
131 sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
132 sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
133 &host->regs->ce_clk_ctrl);
135 sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
138 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
141 int ret, timeout = 10000000;
146 state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
147 state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
148 debug("%s: ERR HOST_STS1 = %08x\n", \
149 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
150 debug("%s: ERR HOST_STS2 = %08x\n", \
151 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
153 if (state1 & STS1_CMDSEQ) {
154 debug("%s: Forced end of command sequence\n", DRIVER_NAME);
155 sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
156 sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
160 printf(DRIVER_NAME": Forceed end of " \
161 "command sequence timeout err\n");
164 if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
168 sh_mmcif_sync_reset(host);
172 if (state2 & STS2_CRC_ERR)
174 else if (state2 & STS2_TIMEOUT_ERR)
181 static int sh_mmcif_single_read(struct sh_mmcif_host *host,
182 struct mmc_data *data)
186 unsigned long *p = (unsigned long *)data->dest;
188 if ((unsigned long)p & 0x00000001) {
189 printf("%s: The data pointer is unaligned.", __func__);
195 /* buf read enable */
196 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
197 time = mmcif_wait_interrupt_flag(host);
198 if (time == 0 || host->sd_error != 0)
199 return sh_mmcif_error_manage(host);
202 blocksize = (BLOCK_SIZE_MASK &
203 sh_mmcif_read(&host->regs->ce_block_set)) + 3;
204 for (i = 0; i < blocksize / 4; i++)
205 *p++ = sh_mmcif_read(&host->regs->ce_data);
207 /* buffer read end */
208 sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
209 time = mmcif_wait_interrupt_flag(host);
210 if (time == 0 || host->sd_error != 0)
211 return sh_mmcif_error_manage(host);
217 static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
218 struct mmc_data *data)
222 unsigned long *p = (unsigned long *)data->dest;
224 if ((unsigned long)p & 0x00000001) {
225 printf("%s: The data pointer is unaligned.", __func__);
230 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
231 for (j = 0; j < data->blocks; j++) {
232 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
233 time = mmcif_wait_interrupt_flag(host);
234 if (time == 0 || host->sd_error != 0)
235 return sh_mmcif_error_manage(host);
238 for (i = 0; i < blocksize / 4; i++)
239 *p++ = sh_mmcif_read(&host->regs->ce_data);
246 static int sh_mmcif_single_write(struct sh_mmcif_host *host,
247 struct mmc_data *data)
251 const unsigned long *p = (unsigned long *)data->dest;
253 if ((unsigned long)p & 0x00000001) {
254 printf("%s: The data pointer is unaligned.", __func__);
259 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
261 time = mmcif_wait_interrupt_flag(host);
262 if (time == 0 || host->sd_error != 0)
263 return sh_mmcif_error_manage(host);
266 blocksize = (BLOCK_SIZE_MASK &
267 sh_mmcif_read(&host->regs->ce_block_set)) + 3;
268 for (i = 0; i < blocksize / 4; i++)
269 sh_mmcif_write(*p++, &host->regs->ce_data);
271 /* buffer write end */
272 sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
274 time = mmcif_wait_interrupt_flag(host);
275 if (time == 0 || host->sd_error != 0)
276 return sh_mmcif_error_manage(host);
282 static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
283 struct mmc_data *data)
287 const unsigned long *p = (unsigned long *)data->dest;
289 if ((unsigned long)p & 0x00000001) {
290 printf("%s: The data pointer is unaligned.", __func__);
295 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
296 for (j = 0; j < data->blocks; j++) {
297 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
299 time = mmcif_wait_interrupt_flag(host);
301 if (time == 0 || host->sd_error != 0)
302 return sh_mmcif_error_manage(host);
305 for (i = 0; i < blocksize / 4; i++)
306 sh_mmcif_write(*p++, &host->regs->ce_data);
313 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
316 if (cmd->resp_type & MMC_RSP_136) {
317 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
318 cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
319 cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
320 cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
321 debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
322 cmd->response[1], cmd->response[2], cmd->response[3]);
324 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
328 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
331 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
334 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
335 struct mmc_data *data, struct mmc_cmd *cmd)
338 u32 opc = cmd->cmdidx;
340 /* Response Type check */
341 switch (cmd->resp_type) {
343 tmp |= CMD_SET_RTYP_NO;
348 tmp |= CMD_SET_RTYP_6B;
351 tmp |= CMD_SET_RTYP_17B;
354 printf(DRIVER_NAME": Not support type response.\n");
359 if (opc == MMC_CMD_SWITCH)
365 switch (host->bus_width) {
366 case MMC_BUS_WIDTH_1:
367 tmp |= CMD_SET_DATW_1;
369 case MMC_BUS_WIDTH_4:
370 tmp |= CMD_SET_DATW_4;
372 case MMC_BUS_WIDTH_8:
373 tmp |= CMD_SET_DATW_8;
376 printf(DRIVER_NAME": Not support bus width.\n");
381 if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
382 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
385 if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
386 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
387 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
388 sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
390 /* RIDXC[1:0] check bits */
391 if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
392 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
393 tmp |= CMD_SET_RIDXC_BITS;
394 /* RCRC7C[1:0] check bits */
395 if (opc == MMC_CMD_SEND_OP_COND)
396 tmp |= CMD_SET_CRC7C_BITS;
397 /* RCRC7C[1:0] internal CRC7 */
398 if (opc == MMC_CMD_ALL_SEND_CID ||
399 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
400 tmp |= CMD_SET_CRC7C_INTERNAL;
402 return opc = ((opc << 24) | tmp);
405 static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
406 struct mmc_data *data, u16 opc)
411 case MMC_CMD_READ_MULTIPLE_BLOCK:
412 ret = sh_mmcif_multi_read(host, data);
414 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
415 ret = sh_mmcif_multi_write(host, data);
417 case MMC_CMD_WRITE_SINGLE_BLOCK:
418 ret = sh_mmcif_single_write(host, data);
420 case MMC_CMD_READ_SINGLE_BLOCK:
421 case MMC_CMD_SEND_EXT_CSD:
422 ret = sh_mmcif_single_read(host, data);
425 printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
432 static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
433 struct mmc_data *data, struct mmc_cmd *cmd)
436 int ret = 0, mask = 0;
437 u32 opc = cmd->cmdidx;
439 if (opc == MMC_CMD_STOP_TRANSMISSION) {
440 /* MMCIF sends the STOP command automatically */
441 if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
442 sh_mmcif_bitset(MASK_MCMD12DRE,
443 &host->regs->ce_int_mask);
445 sh_mmcif_bitset(MASK_MCMD12RBE,
446 &host->regs->ce_int_mask);
448 time = mmcif_wait_interrupt_flag(host);
449 if (time == 0 || host->sd_error != 0)
450 return sh_mmcif_error_manage(host);
452 sh_mmcif_get_cmd12response(host, cmd);
455 if (opc == MMC_CMD_SWITCH)
460 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
461 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
462 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
463 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
466 sh_mmcif_write(0, &host->regs->ce_block_set);
467 sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
469 opc = sh_mmcif_set_cmd(host, data, cmd);
471 sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
472 sh_mmcif_write(mask, &host->regs->ce_int_mask);
474 debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
476 sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
479 sh_mmcif_write(opc, &host->regs->ce_cmd_set);
481 time = mmcif_wait_interrupt_flag(host);
483 return sh_mmcif_error_manage(host);
485 if (host->sd_error) {
486 switch (cmd->cmdidx) {
487 case MMC_CMD_ALL_SEND_CID:
488 case MMC_CMD_SELECT_CARD:
489 case MMC_CMD_APP_CMD:
493 printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
494 ret = sh_mmcif_error_manage(host);
503 if (!(opc & 0x00C00000))
506 if (host->wait_int == 1) {
507 sh_mmcif_get_response(host, cmd);
511 ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
512 host->last_cmd = cmd->cmdidx;
517 static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
518 struct mmc_cmd *cmd, struct mmc_data *data)
524 switch (cmd->cmdidx) {
525 case MMC_CMD_APP_CMD:
527 case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
532 /* send_if_cond cmd (not support) */
539 ret = sh_mmcif_start_cmd(host, data, cmd);
545 static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
548 sh_mmcif_clock_control(host, mmc->clock);
550 if (mmc->bus_width == 8)
551 host->bus_width = MMC_BUS_WIDTH_8;
552 else if (mmc->bus_width == 4)
553 host->bus_width = MMC_BUS_WIDTH_4;
555 host->bus_width = MMC_BUS_WIDTH_1;
557 debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
562 static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
564 sh_mmcif_sync_reset(host);
565 sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
569 #ifndef CONFIG_DM_MMC
570 static void *mmc_priv(struct mmc *mmc)
572 return (void *)mmc->priv;
575 static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
576 struct mmc_data *data)
578 struct sh_mmcif_host *host = mmc_priv(mmc);
580 return sh_mmcif_send_cmd_common(host, cmd, data);
583 static int sh_mmcif_set_ios(struct mmc *mmc)
585 struct sh_mmcif_host *host = mmc_priv(mmc);
587 return sh_mmcif_set_ios_common(host, mmc);
590 static int sh_mmcif_initialize(struct mmc *mmc)
592 struct sh_mmcif_host *host = mmc_priv(mmc);
594 return sh_mmcif_initialize_common(host);
597 static const struct mmc_ops sh_mmcif_ops = {
598 .send_cmd = sh_mmcif_send_cmd,
599 .set_ios = sh_mmcif_set_ios,
600 .init = sh_mmcif_initialize,
603 static struct mmc_config sh_mmcif_cfg = {
605 .ops = &sh_mmcif_ops,
606 .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
608 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
609 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
612 int mmcif_mmc_init(void)
615 struct sh_mmcif_host *host = NULL;
617 host = malloc(sizeof(struct sh_mmcif_host));
620 memset(host, 0, sizeof(*host));
622 host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
623 host->clk = CONFIG_SH_MMCIF_CLK;
625 sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
626 sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
628 mmc = mmc_create(&sh_mmcif_cfg, host);
638 struct sh_mmcif_plat {
639 struct mmc_config cfg;
643 int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
644 struct mmc_data *data)
646 struct sh_mmcif_host *host = dev_get_priv(dev);
648 return sh_mmcif_send_cmd_common(host, cmd, data);
651 int sh_mmcif_dm_set_ios(struct udevice *dev)
653 struct sh_mmcif_host *host = dev_get_priv(dev);
654 struct mmc *mmc = mmc_get_mmc_dev(dev);
656 return sh_mmcif_set_ios_common(host, mmc);
659 static const struct dm_mmc_ops sh_mmcif_dm_ops = {
660 .send_cmd = sh_mmcif_dm_send_cmd,
661 .set_ios = sh_mmcif_dm_set_ios,
664 static int sh_mmcif_dm_bind(struct udevice *dev)
666 struct sh_mmcif_plat *plat = dev_get_platdata(dev);
668 return mmc_bind(dev, &plat->mmc, &plat->cfg);
671 static int sh_mmcif_dm_probe(struct udevice *dev)
673 struct sh_mmcif_plat *plat = dev_get_platdata(dev);
674 struct sh_mmcif_host *host = dev_get_priv(dev);
675 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
676 struct clk sh_mmcif_clk;
680 base = devfdt_get_addr(dev);
681 if (base == FDT_ADDR_T_NONE)
684 host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
688 ret = clk_get_by_index(dev, 0, &sh_mmcif_clk);
690 debug("failed to get clock, ret=%d\n", ret);
694 ret = clk_enable(&sh_mmcif_clk);
696 debug("failed to enable clock, ret=%d\n", ret);
700 host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
702 plat->cfg.name = dev->name;
703 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
705 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
708 plat->cfg.host_caps |= MMC_MODE_8BIT;
711 plat->cfg.host_caps |= MMC_MODE_4BIT;
716 dev_err(dev, "Invalid \"bus-width\" value\n");
720 sh_mmcif_initialize_common(host);
722 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
723 plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
724 plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
725 plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
727 upriv->mmc = &plat->mmc;
732 static const struct udevice_id sh_mmcif_sd_match[] = {
733 { .compatible = "renesas,sh-mmcif" },
737 U_BOOT_DRIVER(sh_mmcif_mmc) = {
740 .of_match = sh_mmcif_sd_match,
741 .bind = sh_mmcif_dm_bind,
742 .probe = sh_mmcif_dm_probe,
743 .priv_auto_alloc_size = sizeof(struct sh_mmcif_host),
744 .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat),
745 .ops = &sh_mmcif_dm_ops,