drivers/mmc/sdhost_phy.c

   1 /******************************************************************************
   2  ** File Name:      sdhost_drv.c
   3  ** Author:         Jason.wu
   4  ** DATE:           09/17/2007
   5  ** Copyright:      2004 Spreadtrum, Incoporated. All Rights Reserved.
   6  ** Description:    This file describe operation of SD host.
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION
  13  ** 09/17/2007     Jason.wu        Create.
  14  ******************************************************************************/
  15
  16 /**---------------------------------------------------------------------------*
  17  **                         Dependencies                                      *
  18  **---------------------------------------------------------------------------*/
  19 #include "asm/arch/sci_types.h"
  20 #include "asm/arch/os_api.h"
  21 #include "asm/arch/chip_plf_export.h"
  22 #include "sdhost_drv.h"
  23
  24 #if   defined(CONFIG_SC8825) || defined (CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
  25 #include <asm/arch/sdio_reg_v3.h>
  26 //#include <asm/arch/int_reg_v3.h>
  27 #include <asm/arch/sys_timer_reg_v0.h>
  28 #endif
  29
  30 #if   defined(CONFIG_SC8825) || defined (CONFIG_SC7710G2)
  31 #include <asm/arch/sc8810_module_config.h>
  32 #elif defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
  33 #include <asm/arch/sprd_module_config.h>
  34 #include <asm/arch/regs_ahb.h>
  35 #include <asm/arch/isr_drvapi.h>
  36 #include <asm/arch/pinmap.h>
  37 #endif
  38
  39 #include "asm/arch/ldo.h"
  40
  41 #ifdef CONFIG_SC8825
  42 #include <asm/arch/pin_reg_v3.h>
  43 #endif
  44
  45 #if defined (CONFIG_SC8810) || defined (CONFIG_SC8825) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
  46 #define PLATFORM_SC8800G
  47 #endif
  48 #if defined CONFIG_SC8825 && defined CONFIG_UBOOT_DEBUG
  49 #define SDHOST_PRINT(x) printf x
  50 #else
  51 #define SDHOST_PRINT(x) SCI_TRACE_LOW x
  52 #endif
  53
  54 #ifndef __maybe_unused
  55 #define __maybe_unused          __attribute__((unused))
  56 #endif
  57
  58 /*****************************************************************************/
  59 //  Description:   Handle of sdhost
  60 //  Author: Jason.wu
  61 //  Param
  62 //      host_cfg: start register of host controller
  63 //      open_flag: Indicate whether this port has be used by other application
  64 //      baseClock: the basic frequence that host work on
  65 //      sdClock: the frequence that card work on
  66 //      capbility: the function that canbe supported by host
  67 //      err_filter: the error code that application want to watched
  68 //      sigCallBack: the point of application that used to anounce that some signal happened
  69 //  Note:
  70 /*****************************************************************************/
  71 typedef struct SDHOST_PORT_T_TAG
  72 {
  73     volatile SDIO_REG_CFG *host_cfg;
  74     BOOLEAN open_flag;
  75         uint32 slotNo;
  76     uint32 baseClock;
  77     uint32 sdClock;
  78     SDHOST_CAPBILIT_T capbility;
  79     uint32 err_filter;
  80     SDIO_CALLBACK sigCallBack;
  81     uint32 IntEnabled;
  82     uint32 SigEnabled;
  83 } SDHOST_PORT_T;
  84
  85 typedef struct
  86 {
  87     uint32 msg;
  88     uint32 errCode;
  89     SDHOST_SLOT_NO slotNum;
  90     SDHOST_HANDLE pSdhost_handler;
  91
  92 } ISR_Buffer_T;
  93
  94 //INPUT_BUFFER_INIT (ISR_Buffer_T, SDHOST_SLOT_MAX_NUM)
  95
  96 LOCAL SDHOST_PORT_T sdio_port_ctl[SDHOST_SLOT_MAX_NUM];
  97 #ifndef OS_NONE
  98 LOCAL DEVICE_HANDLE s_dev_sdio = SCI_NULL;
  99 LOCAL void  SdhostHisrFunc (uint32 cnt, void *pData);
 100 #endif
 101 PUBLIC ISR_EXE_T _SDHOST_IrqHandle (uint32 isrnum);
 102
 103 PUBLIC void SDHOST_Delayus(uint32 usec)
 104 {
 105         volatile uint32 i;
 106         /* current is 800MHZ, when usec =1, the mean is delay 1 us */
 107         for (i = 0; i < (usec << 1); i++);
 108 }
 109 /*****************************************************************************/
 110 //  Description:  To confirm whether the handle is valid
 111 //  Author: Jason.wu
 112 //  Param
 113 //      sdhost_handler: the handle of host driver
 114 //  Return:
 115 //      TRUE the handle is valid
 116 //      FALSE:the handle is not valid
 117 //  Note:
 118 /*****************************************************************************/
 119 LOCAL BOOLEAN __maybe_unused _RegisterVerifyHOST (SDHOST_HANDLE sdhost_handler)
 120 {
 121     uint32 index;
 122
 123     for (index = 0; index < SDHOST_SLOT_MAX_NUM; index++)
 124     {
 125         if ( (sdhost_handler == &sdio_port_ctl[index]) && (TRUE == sdio_port_ctl[index].open_flag))
 126         {
 127             return TRUE;
 128         }
 129     }
 130
 131     return FALSE;
 132 }
 133
 134 PUBLIC uint32 SDHOST_GetPinState (SDHOST_HANDLE sdhost_handler)
 135 {
 136     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 137
 138     return sdhost_handler->host_cfg->PRESENT_STAT;
 139 }
 140
 141 //---Power Control Register---
 142 /*****************************************************************************/
 143 //  Description:  power on/off led
 144 //  Author: Jason.wu
 145 //  Param
 146 //      sdhost_handler: the handle of host driver
 147 //      onoff:
 148 //  Return:
 149 //      NONE
 150 //  Note:
 151 /*****************************************************************************/
 152 PUBLIC void SDHOST_Led (SDHOST_HANDLE sdhost_handler,SDHOST_LED_ONOFF_E onoff)
 153 {
 154     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 155
 156     //===
 157     switch (onoff)
 158     {
 159         case SDIO_LED_ON:
 160             {
 161                 sdhost_handler->host_cfg->HOST_CTL0 |= 0x1;
 162             }
 163             break;
 164
 165         case SDIO_LED_OFF:
 166             {
 167                 sdhost_handler->host_cfg->HOST_CTL0 &= (~0x1);
 168             }
 169             break;
 170
 171         default:
 172             {
 173                 SCI_ASSERT (0);/*assert verified*/
 174             }
 175             break;
 176     }
 177
 178     //===
 179 }
 180
 181 /*****************************************************************************/
 182 //  Description:  set data bus width
 183 //  Author: Jason.wu
 184 //  Param
 185 //      sdhost_handler: the handle of host driver
 186 //      width: data bus width,only 1bit ,4bit and 8bit canbe used
 187 //  Return:
 188 //      NONE
 189 //  Note:
 190 /*****************************************************************************/
 191 PUBLIC void SDHOST_Cfg_BusWidth (SDHOST_HANDLE sdhost_handler,SDHOST_BIT_WIDTH_E width)
 192 {
 193     uint32 tmpReg =  sdhost_handler->host_cfg->HOST_CTL0;
 194
 195     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 196
 197     tmpReg &= (~ (0x1<<5));
 198     tmpReg &= (~ (0x1<<1));
 199
 200     switch (width)
 201     {
 202         case SDIO_1BIT_WIDTH:
 203             {
 204                 //do nothing
 205             }
 206             break;
 207
 208         case SDIO_4BIT_WIDTH:
 209             {
 210                 tmpReg |= (0x1<<1);
 211             }
 212             break;
 213
 214         case SDIO_8BIT_WIDTH:
 215             {
 216                 tmpReg |= (0x1<<5);
 217             }
 218             break;
 219
 220         default:
 221             {
 222                 SCI_ASSERT (0);/*assert verified*/
 223             }
 224             break;
 225     }
 226
 227     sdhost_handler->host_cfg->HOST_CTL0 = tmpReg;
 228 }
 229
 230 /*****************************************************************************/
 231 //  Description:  set bus speed mode
 232 //  Author: Jason.wu
 233 //  Param
 234 //      sdhost_handler: the handle of host driver
 235 //      speed: speed mode ,only low speed mode and high speed mode canbe used
 236 //  Return:
 237 //      NONE
 238 //  Note:
 239 /*****************************************************************************/
 240 #if defined (CONFIG_SC8825) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
 241 PUBLIC void SDHOST_Cfg_SpeedMode (SDHOST_HANDLE sdhost_handler,SDHOST_SPEED_E speed)
 242 {
 243         uint32 tmpReg = sdhost_handler->host_cfg->HOST_CTL2;
 244         SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 245         tmpReg &= ~(7<<16);
 246         switch (speed)
 247         {
 248         case EMMC_SDR12:
 249                 break;
 250         case EMMC_SDR25:
 251                 tmpReg |= 1<<16;
 252                 break;
 253         case EMMC_SDR50:
 254                 REG32(EMMC_CLK_WR_DL)     = 0x33;
 255                 REG32(EMMC_CLK_RD_POS_DL) = 0x08;
 256                 REG32(EMMC_CLK_RD_NEG_DL) = 0x08;
 257                 tmpReg |= 2<<16;
 258                 break;
 259         case EMMC_SDR104:
 260                 tmpReg |= 3<<16;
 261                 break;
 262         case EMMC_DDR50:
 263                 tmpReg |= 4<<16;
 264                 break;
 265         default:
 266                 return;
 267         }
 268         sdhost_handler->host_cfg->HOST_CTL2 = tmpReg;
 269 }
 270 #else
 271 PUBLIC void SDHOST_Cfg_SpeedMode (SDHOST_HANDLE sdhost_handler,SDHOST_SPEED_E speed)
 272 {
 273     uint32 tmpReg =  sdhost_handler->host_cfg->HOST_CTL0;
 274
 275     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 276
 277     tmpReg &= (~ (0x1 <<2));
 278
 279     switch (speed)
 280     {
 281         case SDIO_HIGHSPEED:
 282             {
 283                 tmpReg |= (0x1<<2);
 284             }
 285             break;
 286
 287         case SDIO_LOWSPEED:
 288             {
 289                 //do nothing
 290             }
 291             break;
 292
 293         default:
 294             {
 295                 SCI_ASSERT (0);/*assert verified*/
 296             }
 297             break;
 298     }
 299
 300     sdhost_handler->host_cfg->HOST_CTL0 = tmpReg;
 301 }
 302 #endif
 303
 304 /*
 305 typedef enum
 306 {
 307         LDO_VOLT_LEVEL0=0,
 308         LDO_VOLT_LEVEL1,
 309         LDO_VOLT_LEVEL2,
 310         LDO_VOLT_LEVEL3,
 311         LDO_VOLT_LEVEL_MAX
 312 }LDO_VOLT_LEVEL_E;
 313
 314 #define LDO_LDO_SDIO 29 */
 315
 316 /*****************************************************************************/
 317 //  Description:  Set operation voltage of card(mmc \sd\sdio card.etc.)
 318 //  Author: Jason.wu
 319 //  Param
 320 //      sdhost_handler: the handle of host driver
 321 //      voltage:
 322 //  Return:
 323 //      NONE
 324 //  Note:
 325 /*****************************************************************************/
 326 PUBLIC void SDHOST_Cfg_Voltage (SDHOST_HANDLE sdhost_handler,SDHOST_VOL_RANGE_E voltage)
 327 {
 328 #if defined (CONFIG_TIGER) || defined (CONFIG_SC7710G2)
 329     /*<CR:MS00234475 modify for SPI smartphone 30/03/2011 by shengyanxin bagin*/
 330 #if defined (MODEM_CONTROL_SUPPORT_SPI)
 331     return;
 332 #else
 333 #ifdef PLATFORM_SC8800G
 334     LDO_VOLT_LEVEL_E ldo_volt_level;
 335     u32 tempreg;
 336     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 337
 338     switch (voltage)
 339     {
 340         case VOL_1_8:
 341             {
 342                 ldo_volt_level = LDO_VOLT_LEVEL3;
 343             }
 344             break;
 345
 346         case VOL_2_65:
 347             {
 348                 ldo_volt_level = LDO_VOLT_LEVEL2;   ///it is 2.5V in sc8800g spec.
 349             }
 350             break;
 351
 352         case VOL_2_8:
 353             {
 354                 ldo_volt_level = LDO_VOLT_LEVEL0;
 355             }
 356             break;
 357
 358         case VOL_3_0:
 359             {
 360                 ldo_volt_level = LDO_VOLT_LEVEL1;
 361             }
 362             break;
 363
 364         default:
 365             {
 366                 SCI_ASSERT (0);/*assert verified*/
 367             }
 368             break;
 369     }
 370
 371 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
 372     LDO_SetVoltLevel (LDO_LDO_SDIO3, LDO_VOLT_LEVEL3);
 373     LDO_SetVoltLevel (LDO_LDO_VDD30, LDO_VOLT_LEVEL1);
 374 #else
 375     if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler){
 376         LDO_SetVoltLevel (LDO_LDO_SDIO0, LDO_VOLT_LEVEL3);
 377     }
 378         else
 379         {
 380             LDO_SetVoltLevel (LDO_LDO_SDIO1, LDO_VOLT_LEVEL3);
 381             LDO_SetVoltLevel (LDO_LDO_SIM2, LDO_VOLT_LEVEL1);
 382         }
 383 #endif
 384
 385     //__udelay(20*1000);
 386     //gpio_direction_output(139, 1);
 387     //gpio_set_value(139, 1);
 388    //control gpio 139 emmc reset pin
 389     /*
 390     *(volatile u32 *)0x8B000008 = 1<<5;
 391     *(volatile u32 *)0x8A000384 = 1<<15;
 392     *(volatile u32 *)0x8A000388 = 1<<15;
 393     *(volatile u32 *)0x8A000380 = 1<<15;
 394   */
 395     tempreg = *(volatile u32 *)0x8B000008;
 396     *(volatile u32 *)0x8B000008 = tempreg | (1<<5);
 397
 398     //*(volatile u32 *)0x8C0003D0 = 0;
 399
 400 #ifdef CONFIG_SC8810_OPENPHONE
 401             tempreg = *(volatile unsigned int  *)0x8A000384;
 402             *(volatile unsigned int  *)0x8A000384 = tempreg | (1<<11);
 403             tempreg = *(volatile unsigned int  *)0x8A000388;
 404             *(volatile unsigned int  *)0x8A000388 = tempreg | (1<<11);
 405             tempreg = *(volatile unsigned int  *)0x8A000380;
 406             *(volatile unsigned int  *)0x8A000380 = tempreg | (1<<11);
 407 #else
 408            tempreg = *(volatile unsigned int  *)0x8A000184;
 409             *(volatile unsigned int  *)0x8A000184 = tempreg | (1<<7);
 410             tempreg = *(volatile unsigned int  *)0x8A000188;
 411             *(volatile unsigned int  *)0x8A000188 = tempreg | (1<<7);
 412             tempreg = *(volatile unsigned int  *)0x8A000180;
 413             *(volatile unsigned int  *)0x8A000180 = tempreg | (1<<7);
 414 #endif
 415
 416 #else
 417
 418     uint32 tmpReg =  sdhost_handler->host_cfg->HOST_CTL0;
 419
 420     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 421
 422     tmpReg &= (~ (0x7<<9));
 423
 424     switch (voltage)
 425     {
 426         case VOL_1_8:
 427             {
 428                 tmpReg |= (0x05<<9);
 429             }
 430             break;
 431
 432         case VOL_2_65:
 433             {
 434                 tmpReg |= (0x01<<9);
 435             }
 436             break;
 437
 438         case VOL_2_8:
 439             {
 440                 tmpReg |= (0x04<<9);
 441             }
 442             break;
 443
 444         case VOL_3_0:
 445             {
 446                 tmpReg |= (0x07<<9);
 447             }
 448             break;
 449
 450         default:
 451             {
 452                 SCI_ASSERT (0);/*assert verified*/
 453             }
 454             break;
 455     }
 456
 457     sdhost_handler->host_cfg->HOST_CTL0 = tmpReg;
 458 #endif
 459 #endif
 460 #endif
 461 }
 462
 463 /*****************************************************************************/
 464 //  Description:  Open or close power supply of card(mmc \sd\sdio card.etc.)
 465 //  Author: Jason.wu
 466 //  Param
 467 //      sdhost_handler: the handle of host driver
 468 //      on_off:
 469 //  Return:
 470 //      NONE
 471 //  Note:
 472 /*****************************************************************************/
 473 PUBLIC void SDHOST_SD_POWER (SDHOST_HANDLE sdhost_handler,SDHOST_PWR_ONOFF_E on_off)
 474 {
 475     /*<CR:MS00234475 modify for SPI smartphone 30/03/2011 by shengyanxin bagin*/
 476 #if defined (MODEM_CONTROL_SUPPORT_SPI) && defined (AP_SOLUTION_INGENIC)
 477     return;
 478 #else
 479     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 480
 481 #if defined(PLATFORM_SC8800G)
 482
 483     ///added by mingwei, Andy need to check again.
 484     if (POWR_ON == on_off)
 485     {
 486         //LDO_TurnOnLDO (LDO_LDO_SDIO);
 487 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
 488                 LDO_TurnOnLDO(LDO_LDO_SDIO3);
 489                 LDO_TurnOnLDO(LDO_LDO_VDD30);
 490 #elif (defined CONFIG_SC8830)
 491         #if defined(CONFIG_SPX30G2)
 492                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 493                 {
 494                         LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
 495                         LDO_TurnOnLDO(LDO_LDO_EMMCIO);
 496                 }
 497                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 498                 {
 499                 /*
 500                         for 2723
 501                         .id = LDO_LDO_SDIO0, .name = "vddsdcore",
 502                         .id = LDO_LDO_SDIO1, .name = "vddsdio",
 503                         sharkl no need open vddsdio.
 504                         if need,turn on vddsdio
 505                         LDO_TurnOnLDO(LDO_LDO_SDIO1);
 506                 */
 507                         LDO_TurnOnLDO(LDO_LDO_SDIO1);
 508                         LDO_TurnOnLDO(LDO_LDO_SDIO0);
 509                 }
 510
 511         #elif (defined CONFIG_SPX20)
 512                         if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 513                         {
 514                                 LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
 515                                 LDO_TurnOnLDO(LDO_LDO_EMMCIO);
 516                         }
 517                         else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 518                         {
 519                                 printf("%s config SDHOST_SLOT_6\r\n", __FUNCTION__);
 520                                 LDO_TurnOnLDO(LDO_LDO_SDIO0);
 521                                 LDO_TurnOnLDO(LDO_LDO_SDIO1);
 522                         }
 523         #else
 524                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 525                 {
 526                         LDO_TurnOnLDO(LDO_LDO_SDIO3);
 527                 }
 528                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 529                 {
 530                         printf("%s config SDHOST_SLOT_6\r\n", __FUNCTION__);
 531                         LDO_TurnOnLDO(LDO_LDO_SDIO0);
 532                 }
 533         #endif
 534 #elif (defined CONFIG_SC9630)
 535                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 536                 {
 537                         LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
 538                         LDO_TurnOnLDO(LDO_LDO_EMMCIO);
 539                 }
 540                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 541                 {
 542
 543                 /*
 544                         for 2723
 545                         .id = LDO_LDO_SDIO0, .name = "vddsdcore",
 546                         .id = LDO_LDO_SDIO1, .name = "vddsdio",
 547                         sharkl no need open vddsdio.
 548                         if need,turn on vddsdio
 549                         LDO_TurnOnLDO(LDO_LDO_SDIO1);
 550                 */
 551                         #if defined(CONFIG_SP9830IEA_5M_H100)
 552                                 LDO_TurnOnLDO(LDO_LDO_SDIO1);
 553                                 LDO_TurnOnLDO(LDO_LDO_SDIO0);
 554                         #else
 555                                 LDO_TurnOnLDO(LDO_LDO_SDIO0);
 556                         #endif
 557                 }
 558 #else
 559                 if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler)
 560                 {
 561                         LDO_TurnOnLDO(LDO_LDO_SDIO0);
 562                 }else
 563                 {
 564                         LDO_TurnOnLDO(LDO_LDO_SDIO1);
 565                         LDO_TurnOnLDO(LDO_LDO_SIM2);
 566                 }
 567 #endif
 568     }
 569     else  // power off
 570     {
 571 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
 572                 LDO_TurnOffLDO(LDO_LDO_SDIO3);
 573                 LDO_TurnOffLDO(LDO_LDO_VDD30);
 574 #elif defined (CONFIG_SC8830)
 575         #if defined(CONFIG_SPX30G2)
 576                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 577                 {
 578                         LDO_TurnOffLDO(LDO_LDO_EMMCCORE);
 579                         LDO_TurnOffLDO(LDO_LDO_EMMCIO);
 580                 }
 581                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 582                 {
 583                         LDO_TurnOffLDO(LDO_LDO_SDIO0);
 584                         LDO_TurnOffLDO(LDO_LDO_SDIO1);
 585                         /*
 586                                 for 2723
 587                                 .id = LDO_LDO_SDIO0, .name = "vddsdcore",
 588                                 .id = LDO_LDO_SDIO1, .name = "vddsdio",
 589                                 sharkl no need open vddsdio.
 590                                 if need,turn off vddsdio
 591                                 LDO_TurnOffLDO(LDO_LDO_SDIO1);
 592                         */
 593                 }
 594
 595         #elif (defined CONFIG_SPX20)
 596                          if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 597                          {
 598                                  LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
 599                                  LDO_TurnOnLDO(LDO_LDO_EMMCIO);
 600                          }
 601                       else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 602                          {
 603                                   printf("%s config SDHOST_SLOT_6\r\n", __FUNCTION__);
 604                                   LDO_TurnOnLDO(LDO_LDO_SDIO0);
 605                                   LDO_TurnOnLDO(LDO_LDO_SDIO1);
 606                          }
 607
 608
 609         #else
 610                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 611                 {
 612                         LDO_TurnOffLDO(LDO_LDO_SDIO3);
 613                 }
 614                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 615                 {
 616                         LDO_TurnOffLDO(LDO_LDO_SDIO0);
 617                 }
 618         #endif
 619 #elif (defined CONFIG_SC9630)
 620                 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
 621                 {
 622                         LDO_TurnOffLDO(LDO_LDO_EMMCCORE);
 623                         LDO_TurnOffLDO(LDO_LDO_EMMCIO);
 624                 }
 625                 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
 626                 {
 627                         LDO_TurnOffLDO(LDO_LDO_SDIO0);
 628                         /*
 629                                 for 2723
 630                                 .id = LDO_LDO_SDIO0, .name = "vddsdcore",
 631                                 .id = LDO_LDO_SDIO1, .name = "vddsdio",
 632                                 sharkl no need open vddsdio.
 633                                 if need,turn off vddsdio
 634                                 LDO_TurnOffLDO(LDO_LDO_SDIO1);
 635                         */
 636                 }
 637 #else
 638                 if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler){
 639                         LDO_TurnOffLDO (LDO_LDO_SDIO0);
 640                 }else
 641                 {
 642                 LDO_TurnOffLDO (LDO_LDO_SDIO1);
 643                 LDO_TurnOffLDO (LDO_LDO_SIM2);
 644                 }
 645 #endif
 646     }
 647
 648 #else // no defined(PLATFORM_SC8800G)
 649
 650     switch (on_off)
 651     {
 652         case POWR_ON:
 653             {
 654                 sdhost_handler->host_cfg->HOST_CTL0 |= (0x1<<8);
 655             }
 656             break;
 657
 658         case POWR_OFF:
 659             {
 660                 sdhost_handler->host_cfg->HOST_CTL0 &= (~ (0x1<<8));
 661             }
 662             break;
 663
 664         default:
 665             {
 666                 SCI_ASSERT (0);/*assert verified*/
 667             }
 668             break;
 669     }
 670
 671 #endif
 672 #endif
 673 }
 674 //---Block Gap Control Register---
 675 /*****************************************************************************/
 676 //  Description:  Set the position of break point
 677 //  Author: Jason.wu
 678 //  Param
 679 //      sdhost_handler: the handle of host driver
 680 //  Return:
 681 //      NONE
 682 //  Note:
 683 /*****************************************************************************/
 684 PUBLIC void SDHOST_BlkGapIntPosSet (SDHOST_HANDLE sdhost_handler)
 685 {
 686     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 687
 688 }
 689
 690 /*****************************************************************************/
 691 //  Description:  Enable pause function of host. the card must support this function,then this function can be worked
 692 //  Author: Jason.wu
 693 //  Param
 694 //      sdhost_handler: the handle of host driver
 695 //  Return:
 696 //      NONE
 697 //  Note:
 698 /*****************************************************************************/
 699 PUBLIC void SDHOST_EnableReadWaitCtl (SDHOST_HANDLE sdhost_handler)
 700 {
 701     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 702
 703     sdhost_handler->host_cfg->HOST_CTL0 |= BIT_18;
 704 }
 705
 706 /*****************************************************************************/
 707 //  Description:  Set break point during the transmition
 708 //  Author: Jason.wu
 709 //  Param
 710 //      sdhost_handler: the handle of host driver
 711 //  Return:
 712 //      NONE
 713 //  Note:
 714 /*****************************************************************************/
 715 PUBLIC void SDHOST_StopAtBlkGap (SDHOST_HANDLE sdhost_handler)
 716 {
 717     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 718
 719     sdhost_handler->host_cfg->HOST_CTL0 |= (BIT_16);
 720 }
 721 PUBLIC void SDHOST_ClearBlkGap (SDHOST_HANDLE sdhost_handler)
 722 {
 723     sdhost_handler->host_cfg->HOST_CTL0 &= (~ (0x01<<16));
 724 }
 725 PUBLIC void SDHOST_BlkGapIntEn (SDHOST_HANDLE sdhost_handler)
 726 {
 727     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler)); /*assert verified*/
 728
 729     sdhost_handler->host_cfg->HOST_CTL0 |= (BIT_19);
 730 }
 731 PUBLIC uint32 SDHOST_GetTransStat (SDHOST_HANDLE sdhost_handler)
 732 {
 733     return (sdhost_handler->host_cfg->PRESENT_STAT & (BIT_8|BIT_9));
 734 }
 735
 736 /*****************************************************************************/
 737 //  Description:  When transmission is paused ,this function can resume the transmission
 738 //  Author: Jason.wu
 739 //  Param
 740 //      sdhost_handler: the handle of host driver
 741 //  Return:
 742 //      NONE
 743 //  Note:
 744 /*****************************************************************************/
 745 PUBLIC void SDHOST_Continue (SDHOST_HANDLE sdhost_handler)
 746 {
 747     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 748
 749     sdhost_handler->host_cfg->HOST_CTL0 &= (~ (0x03<<16));
 750     sdhost_handler->host_cfg->HOST_CTL0 |= BIT_17;
 751
 752 }
 753
 754
 755
 756 //----Clock Control Register---
 757 /*****************************************************************************/
 758 //  Description:  Open or close internal clk.when this clk is disable ,the host will enter in sleep mode
 759 //  Author: Jason.wu
 760 //  Param
 761 //      sdhost_handler: the handle of host driver
 762 //      onoff:
 763 //  Return:
 764 //      NONE
 765 //  Note:
 766 /*****************************************************************************/
 767 PUBLIC void SDHOST_internalClk_OnOff (SDHOST_HANDLE sdhost_handler,SDHOST_CLK_ONOFF_E onoff)
 768 {
 769     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 770
 771     switch (onoff)
 772     {
 773         case CLK_ON:
 774             {
 775                 uint32 timeout;
 776                 //Enable internal clock
 777                 sdhost_handler->host_cfg->HOST_CTL1 |= BIT_0;
 778                 timeout = 30;
 779                 while ((0 == (sdhost_handler->host_cfg->HOST_CTL1 & BIT_1)) && timeout)
 780                 {
 781                    SDHOST_Delayus(100);
 782                     timeout--;
 783                 }
 784             }
 785             break;
 786
 787         case CLK_OFF:
 788             {
 789                 sdhost_handler->host_cfg->HOST_CTL1 &= (~BIT_0);
 790                 SDHOST_Delayus(200);
 791             }
 792             break;
 793
 794         default:
 795             {
 796                 SCI_ASSERT (0);/*assert verified*/
 797             }
 798             break;
 799     }
 800 }
 801
 802 /*****************************************************************************/
 803 //  Description:  Open or close card clk.
 804 //  Author: Jason.wu
 805 //  Param
 806 //      sdhost_handler: the handle of host driver
 807 //      onoff:
 808 //  Return:
 809 //      NONE
 810 //  Note:
 811 /*****************************************************************************/
 812 PUBLIC void SDHOST_SD_clk_OnOff (SDHOST_HANDLE sdhost_handler,SDHOST_CLK_ONOFF_E onoff)
 813 {
 814     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 815
 816     switch (onoff)
 817     {
 818         case CLK_ON:
 819             {
 820                 //Enable internal clock
 821                 sdhost_handler->host_cfg->HOST_CTL1 |= BIT_2;
 822             }
 823             break;
 824
 825         case CLK_OFF:
 826             {
 827                 if ((sdhost_handler->host_cfg->HOST_CTL1 & BIT_2) != 0) {
 828                     sdhost_handler->host_cfg->HOST_CTL1 &= (~BIT_2);
 829                     SDHOST_Delayus(200);
 830                 }
 831             }
 832             break;
 833
 834         default:
 835             {
 836                 SCI_ASSERT (0);/*assert verified*/
 837             }
 838             break;
 839     }
 840 }
 841
 842 /*****************************************************************************/
 843 //  Description:  Set the frequence of Card clock
 844 //  Author: Jason.wu
 845 //  Param
 846 //      sdhost_handler: the handle of host driver
 847 //      sdio_clk: the frequence of card working clock
 848 //  Return:
 849 //      uint32 value : the frequency that be used acctually
 850 //  Note:
 851 /*****************************************************************************/
 852 PUBLIC uint32 SDHOST_SD_Clk_Freq_Set (SDHOST_HANDLE sdhost_handler,uint32 sdio_clk)
 853 {
 854     volatile uint32 tmpReg;
 855     uint32 clkDiv;
 856
 857     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 858     SCI_ASSERT (0 != sdio_clk);/*assert verified*/
 859
 860     sdio_clk = (sdio_clk > SDIO_SD_MAX_CLK) ? (SDIO_SD_MAX_CLK) : (sdio_clk);
 861
 862     //SDCLK Frequency Select ,Configure SDCLK select
 863     clkDiv = sdhost_handler->baseClock/sdio_clk;
 864 #if defined (CONFIG_SC8825) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
 865     clkDiv /= 2;
 866 #endif
 867     if (0 != sdhost_handler->baseClock%sdio_clk)
 868     {
 869         clkDiv++;
 870     }
 871
 872     SDHOST_PRINT ( ("   clkDiv: %d, sdio_clk:%d, baseClock:%d\n",clkDiv, sdio_clk, sdhost_handler->baseClock));
 873
 874     tmpReg = sdhost_handler->host_cfg->HOST_CTL1;
 875 #if defined (CONFIG_SC8825) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
 876     clkDiv--;
 877     tmpReg &= (~ (0x3ff<<6));
 878     tmpReg |= ((clkDiv>>8)&0x3)<<6;
 879     tmpReg |= (clkDiv&0xff)<<8;
 880     sdhost_handler->sdClock = sdhost_handler->baseClock/(2*(clkDiv+1));
 881 #else
 882     tmpReg &= (~ (0xff<<8));
 883     if (256 < clkDiv)
 884     {
 885         SDHOST_PRINT ( ("   clkDiv: %d is too big!!!!!",clkDiv));
 886         SCI_ASSERT (0);/*assert to do*/
 887     }
 888     else if (128 < clkDiv)
 889     {
 890         clkDiv = 256;
 891         tmpReg |= (0x80 << 8);
 892     }
 893     else if (64 < clkDiv)
 894     {
 895         clkDiv = 128;
 896         tmpReg |= (0x40<<8);
 897     }
 898     else if (32 < clkDiv)
 899     {
 900         clkDiv = 64;
 901         tmpReg |= (0x20<<8);
 902     }
 903     else if (16 < clkDiv)
 904     {
 905         clkDiv = 32;
 906         tmpReg |= (0x10<<8);
 907     }
 908     else if (8 < clkDiv)
 909     {
 910         clkDiv = 16;
 911         tmpReg |= (0x8<<8);
 912     }
 913     else if (4 < clkDiv)
 914     {
 915         clkDiv = 8;
 916         tmpReg |= (0x4<<8);
 917     }
 918     else if (2 < clkDiv)
 919     {
 920         clkDiv = 4;
 921         tmpReg |= (0x2<<8);
 922     }
 923     else if (1 < clkDiv)
 924     {
 925         clkDiv = 2;
 926         tmpReg |= (0x1<<8);
 927     }
 928     else if (0 < clkDiv)
 929     {
 930         clkDiv = 1;
 931         //nothing
 932     }
 933     else //if (0 == clkDiv)
 934     {
 935         SCI_ASSERT (0);/*assert to do*/
 936     }
 937     sdhost_handler->sdClock = sdhost_handler->baseClock/clkDiv;
 938 #endif
 939
 940     sdhost_handler->host_cfg->HOST_CTL1 = tmpReg;
 941     SDHOST_PRINT ( ("sd clk: %d KHz.",sdhost_handler->sdClock/1000));
 942
 943     return sdhost_handler->sdClock;
 944 }
 945
 946 //---Timeout Control Register--
 947 /*****************************************************************************/
 948 //  Description:  Set timeout value ,this value is used during the data transmission
 949 //  Author: Jason.wu
 950 //  Param
 951 //      sdhost_handler: the handle of host driver
 952 //      clk_cnt: the value is (2 ^ (clkcnt+13))*T_BSCLK,T_BSCLK is working frequence of host
 953 //  Return:
 954 //      NONE
 955 //  Note:
 956 /*****************************************************************************/
 957 PUBLIC void SDHOST_SetDataTimeOutValue (SDHOST_HANDLE sdhost_handler,uint8 clk_cnt) // (2 ^ (clkcnt+13))*T_BSCLK
 958 {
 959     volatile uint32 tmpReg,tmpIntReg;
 960
 961     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 962
 963     tmpIntReg = sdhost_handler->host_cfg->INT_STA_EN;
 964     // cfg the data timeout clk----------
 965     sdhost_handler->host_cfg->INT_STA_EN &= ~BIT_20;
 966
 967     tmpReg = sdhost_handler->host_cfg->HOST_CTL1;
 968     tmpReg &= ~ (0xF << 16);
 969     tmpReg |= (clk_cnt << 16);
 970     sdhost_handler->host_cfg->HOST_CTL1 = tmpReg;
 971
 972     sdhost_handler->host_cfg->INT_STA_EN = tmpIntReg;
 973 }
 974
 975 //---Software Reset Register---
 976 /*****************************************************************************/
 977 //  Description: Reset data line of host
 978 //  Author: Jason.wu
 979 //  Param
 980 //      sdhost_handler: the handle of host driver
 981 //  Return:
 982 //      NONE
 983 //  Note:
 984 /*****************************************************************************/
 985 LOCAL void _Reset_DAT (SDHOST_HANDLE sdhost_handler)
 986 {
 987     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
 988
 989     sdhost_handler->host_cfg->HOST_CTL1 |= BIT_26;
 990
 991     while (0!= (sdhost_handler->host_cfg->HOST_CTL1 & BIT_26)) {}
 992 }
 993 /*****************************************************************************/
 994 //  Description: Reset command line of host
 995 //  Author: Jason.wu
 996 //  Param
 997 //      sdhost_handler: the handle of host driver
 998 //  Return:
 999 //      NONE
1000 //  Note:
1001 /*****************************************************************************/
1002 LOCAL void _Reset_CMD (SDHOST_HANDLE sdhost_handler)
1003 {
1004     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1005
1006     sdhost_handler->host_cfg->HOST_CTL1 |= BIT_25;
1007
1008     while (0!= (sdhost_handler->host_cfg->HOST_CTL1 & BIT_25)) {}
1009 }
1010
1011 /*****************************************************************************/
1012 //  Description: Reset command line and data line of host
1013 //  Author: Jason.wu
1014 //  Param
1015 //      sdhost_handler: the handle of host driver
1016 //  Return:
1017 //      NONE
1018 //  Note:
1019 /*****************************************************************************/
1020 LOCAL void _Reset_DAT_CMD (SDHOST_HANDLE sdhost_handler)
1021 {
1022     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1023
1024     sdhost_handler->host_cfg->HOST_CTL1 |= (BIT_25|BIT_26);
1025
1026     while (0!= (sdhost_handler->host_cfg->HOST_CTL1 & (BIT_25|BIT_26))) {}
1027
1028
1029 }
1030
1031 /*****************************************************************************/
1032 //  Description: Reset all the module of host
1033 //  Author: Jason.wu
1034 //  Param
1035 //      sdhost_handler: the handle of host driver
1036 //  Return:
1037 //      NONE
1038 //  Note:
1039 /*****************************************************************************/
1040 LOCAL void _Reset_ALL (SDHOST_HANDLE sdhost_handler)
1041 {
1042     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1043
1044     sdhost_handler->host_cfg->HOST_CTL1 |= BIT_24;
1045
1046     while (0 != (sdhost_handler->host_cfg->HOST_CTL1 & BIT_24)) {}
1047
1048 }
1049
1050 /*****************************************************************************/
1051 //  Description: Reset  module of host
1052 //  Author: Wenjun.Shi
1053 //  Param
1054 //      sdhost_handler: the handle of host driver
1055 //  Return:
1056 //      NONE
1057 //  Note:
1058 /*****************************************************************************/
1059 LOCAL  void SDHOST_Reset_Controller(SDHOST_SLOT_NO slot_NO)
1060 {
1061 #if   defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
1062         if (slot_NO == SDHOST_SLOT_6)
1063         {
1064                 REG32 (AHB_CTL0)     |= BIT_8;
1065                 REG32 (AHB_SOFT_RST) |= BIT_11;
1066                 SDHOST_Delayus(200);
1067                 REG32 (AHB_SOFT_RST) &=~BIT_11;
1068         }
1069         else if (slot_NO == SDHOST_SLOT_7)
1070         {
1071                 REG32 (AHB_CTL0)     |= BIT_11;
1072                 REG32 (AHB_SOFT_RST) |= BIT_14;
1073                 SDHOST_Delayus(200);
1074                 REG32 (AHB_SOFT_RST) &=~BIT_14;
1075         }
1076 #elif defined (CONFIG_SC8825)
1077         if (slot_NO == SDHOST_SLOT_6)
1078         {
1079                 REG32 (AHB_CTL0)     |= BIT_4;
1080                 REG32 (AHB_SOFT_RST) |= BIT_12;
1081                 REG32 (AHB_SOFT_RST) &= ~BIT_12;
1082         }
1083         else if (slot_NO == SDHOST_SLOT_7)
1084         {
1085                 REG32 (AHB_CTL0)     |= BIT_23;
1086                 REG32 (AHB_SOFT_RST) |= BIT_21;
1087                 REG32 (AHB_SOFT_RST) &= ~BIT_21;
1088         }
1089 #elif defined(CONFIG_SC7710G2)
1090         REG32 (AHB_CTL6)          |= BIT_2;
1091         REG32 (AHB_SOFT2_RST) |= BIT_0;
1092         REG32 (AHB_SOFT2_RST) &= ~BIT_0;
1093 #else
1094 #define AHB_CTL0_SDIO0_EN       (BIT_4)
1095 #define AHB_CTL0_SDIO1_EN       (BIT_19)
1096
1097 #define AHB_CTL0_SDIO0_RST      (BIT_12)
1098 #define AHB_CTL0_SDIO1_RST      (BIT_16)
1099
1100         if(slot_NO == SDHOST_SLOT_0)
1101         {
1102                 REG32 (AHB_CTL0) |= AHB_CTL0_SDIO0_EN;
1103                 REG32 (AHB_SOFT_RST) |= AHB_CTL0_SDIO0_RST;
1104                 REG32 (AHB_SOFT_RST) &= ~AHB_CTL0_SDIO0_RST;
1105         }else if(slot_NO == SDHOST_SLOT_1)
1106         {
1107                 REG32 (AHB_CTL0) |= AHB_CTL0_SDIO1_EN;
1108                 REG32 (AHB_SOFT_RST) |= AHB_CTL0_SDIO1_RST;
1109                 REG32 (AHB_SOFT_RST) &= ~AHB_CTL0_SDIO1_RST;
1110         }
1111                 // select slot 0
1112 #endif
1113
1114
1115 }
1116
1117 LOCAL void _Reset_MODULE (SDHOST_HANDLE sdhost_handler)
1118 {
1119     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1120
1121     if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler){
1122                 SDHOST_Reset_Controller(SDHOST_SLOT_0);
1123     } else if(&sdio_port_ctl[SDHOST_SLOT_1] == sdhost_handler){
1124                 SDHOST_Reset_Controller(SDHOST_SLOT_1);
1125     }
1126     else if(&sdio_port_ctl[SDHOST_SLOT_6] == sdhost_handler){
1127                 SDHOST_Reset_Controller(SDHOST_SLOT_6);
1128     }
1129     else if(&sdio_port_ctl[SDHOST_SLOT_7] == sdhost_handler){
1130                 SDHOST_Reset_Controller(SDHOST_SLOT_7);
1131     }
1132
1133 }
1134
1135 /*****************************************************************************/
1136 //  Description: Reset the specify module of host
1137 //  Author: Jason.wu
1138 //  Param
1139 //      sdhost_handler: the handle of host driver
1140 //      rst_type: indicate which module will be reset(command lin\data line\all the module)
1141 //  Return:
1142 //      NONE
1143 //  Note:
1144 /*****************************************************************************/
1145 PUBLIC void SDHOST_RST (SDHOST_HANDLE sdhost_handler,SDHOST_RST_TYPE_E rst_type)
1146 {
1147     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1148
1149     switch (rst_type)
1150     {
1151         case RST_CMD_LINE:
1152             {
1153                 _Reset_CMD (sdhost_handler);
1154             }
1155             break;
1156
1157         case RST_DAT_LINE:
1158             {
1159                 _Reset_DAT (sdhost_handler);
1160             }
1161             break;
1162
1163         case RST_CMD_DAT_LINE:
1164             {
1165                 _Reset_DAT_CMD (sdhost_handler);
1166             }
1167             break;
1168
1169         case RST_ALL:
1170             {
1171                 SDHOST_SD_clk_OnOff(sdhost_handler, CLK_OFF);
1172                 _Reset_ALL (sdhost_handler);
1173             }
1174             break;
1175
1176         case RST_MODULE:
1177             {
1178                 SDHOST_SD_clk_OnOff(sdhost_handler, CLK_OFF);
1179                 _Reset_MODULE (sdhost_handler);
1180             }
1181             break;
1182         default:
1183             {
1184                 SCI_ASSERT (0);/*assert verified*/
1185             }
1186             break;
1187     }
1188 }
1189
1190 /*****************************************************************************/
1191 //  Description: Set block size \count of block\and Dma Buffer size
1192 //  Author: Jason.wu
1193 //  Param
1194 //      sdhost_handler: the handle of host driver
1195 //      block_size: size of block( 0 <= block size <=0x0800)
1196 //      block_cnt: the count of block(0 <= block_cnt <= 0xFFFF)
1197 //      DMAsize:buffer size of DMA(4K,8K,16K,32K,64K,128K,256K,512K)
1198 //  Return:
1199 //      NONE
1200 //  Note:
1201 /*****************************************************************************/
1202 PUBLIC void SDHOST_SetDataParam (SDHOST_HANDLE sdhost_handler,uint32 block_size,uint32 block_cnt,SDHOST_DMA_BUF_SIZE_E DMAsize)
1203 {
1204     volatile uint32 tmpReg;
1205
1206     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1207     SCI_ASSERT (0x1000 >= block_size);/*assert verified*/
1208     SCI_ASSERT (0xFFFF >= block_cnt);/*assert verified*/
1209
1210     tmpReg = sdhost_handler->host_cfg->BLK_SIZE_COUNT;
1211
1212     // Set Block Size
1213     tmpReg &= (~BIT_15);
1214     tmpReg &= (~ (0xFFF));
1215     if (0x1000 == block_size)
1216     {
1217         tmpReg |= BIT_15;
1218     }
1219     else
1220     {
1221         tmpReg |= block_size;
1222     }
1223
1224     // Set Block Cnt
1225     tmpReg &= (~0xFFFF0000);
1226     tmpReg |= (block_cnt << 16);
1227
1228     // Set DMA Buf Size
1229     tmpReg &= (~ (0x07<<12));
1230
1231     switch (DMAsize)
1232     {
1233         case SDIO_DMA_4K:
1234             {
1235                 //do nothing
1236             }
1237             break;
1238
1239         case SDIO_DMA_8K:
1240             {
1241                 tmpReg |= (0x01<<12);
1242             }
1243             break;
1244
1245         case SDIO_DMA_16K:
1246             {
1247                 tmpReg |= (0x02<<12);
1248             }
1249             break;
1250
1251         case SDIO_DMA_32K:
1252             {
1253                 tmpReg |= (0x03<<12);
1254             }
1255             break;
1256
1257         case SDIO_DMA_64K:
1258             {
1259                 tmpReg |= (0x04<<12);
1260             }
1261             break;
1262
1263         case SDIO_DMA_128K:
1264             {
1265                 tmpReg |= (0x05<<12);
1266             }
1267             break;
1268
1269         case SDIO_DMA_256K:
1270             {
1271                 tmpReg |= (0x06<<12);
1272             }
1273             break;
1274
1275         case SDIO_DMA_512K:
1276             {
1277                 tmpReg |= (0x07<<12);
1278             }
1279             break;
1280
1281         default:
1282             {
1283                 SCI_ASSERT (0);/*assert verified*/
1284             }
1285             break;
1286
1287     }
1288     sdhost_handler->host_cfg->BLK_SIZE_COUNT = tmpReg;
1289 }
1290
1291 PUBLIC void SDHOST_GetDataParam (SDHOST_HANDLE sdhost_handler,uint32 *block_size,uint32 *block_cnt, uint32 *dmaAddr)
1292 {
1293     uint32 sizecnt;
1294
1295     sizecnt = sdhost_handler->host_cfg->BLK_SIZE_COUNT;
1296     *block_size = sizecnt&0xFFF;
1297     *block_cnt  = ( (sizecnt&0xFFFF0000) >>16);
1298     *dmaAddr    = sdhost_handler->host_cfg->DMA_SYS_ADD;
1299 }
1300
1301 /*****************************************************************************/
1302 //  Description: Set start address of DMA buffer
1303 //  Author: Jason.wu
1304 //  Param
1305 //      sdhost_handler: the handle of host driver
1306 //      dmaAddr: start address of DMA buffer
1307 //  Return:
1308 //      NONE
1309 //  Note:
1310 /*****************************************************************************/
1311 PUBLIC void SDHOST_SetDmaAddr (SDHOST_HANDLE sdhost_handler, uint32 dmaAddr)
1312 {
1313     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1314
1315     sdhost_handler->host_cfg->DMA_SYS_ADD = dmaAddr;
1316
1317 }
1318
1319 /*****************************************************************************/
1320 //  Description: Get stop address of DMA buffer,when buffer is used ,the dma will stop at last address of buffer.this function will get this address
1321 //  Author: Jason.wu
1322 //  Param
1323 //      sdhost_handler: the handle of host driver
1324 //  Return:
1325 //      uint32 value: address that DMA stoped at
1326 //  Note:
1327 /*****************************************************************************/
1328 PUBLIC uint32 SDHOST_GetDmaAddr (SDHOST_HANDLE sdhost_handler)
1329 {
1330     uint32 dmaAddr;
1331
1332     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1333
1334     dmaAddr = sdhost_handler->host_cfg->DMA_SYS_ADD;
1335     return dmaAddr;
1336 }
1337 //---Argument Register---
1338 /*****************************************************************************/
1339 //  Description: Set the argument of command
1340 //  Author: Jason.wu
1341 //  Param
1342 //      sdhost_handler: the handle of host driver
1343 //      argument
1344 //  Return:
1345 //      NONE
1346 //  Note:
1347 /*****************************************************************************/
1348 PUBLIC void SDHOST_SetCmdArg (SDHOST_HANDLE sdhost_handler,uint32 argument)
1349 {
1350     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1351
1352     sdhost_handler->host_cfg->CMD_ARGUMENT = argument;
1353 }
1354
1355 //---CMD Register---
1356 /*****************************************************************************/
1357 //  Description: Set the mode of command
1358 //  Author: Jason.wu
1359 //  Param
1360 //      sdhost_handler: the handle of host driver
1361 //      cmdIndex:   command
1362 //      transmode:  transfer mode
1363 //      cmd_type:   comand type ,it may be normal comman ,resume comman etc.
1364 //      Response:   the inspect response from card. if this comman is performed by card successly ,this response will be return by card
1365 //  Return:
1366 //      NONE
1367 //  Note:
1368 /*****************************************************************************/
1369 PUBLIC void SDHOST_SetCmd (SDHOST_HANDLE sdhost_handler,uint32 cmdIndex,uint32 transmode,SDHOST_CMD_TYPE_E cmd_type,CMD_RSP_TYPE_E Response)
1370 {
1371     volatile uint32 tmpReg;
1372
1373     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1374
1375     tmpReg = sdhost_handler->host_cfg->CMD_TRANSMODE;
1376     tmpReg &= (~ (0x7F|0x30000|0x3FF80000));
1377
1378     if (0 != (TRANS_MODE_ATA_CMPLETE_SIG_EN&transmode))
1379     {
1380         tmpReg |= SDIO_TRANS_COMP_ATA;
1381     }
1382
1383     if (0 != (TRANS_MODE_MULTI_BLOCK&transmode))
1384     {
1385         tmpReg |= SDIO_TRANS_MULTIBLK;
1386     }
1387
1388     if (0 != (TRANS_MODE_READ&transmode))
1389     {
1390         tmpReg |= SDIO_TRANS_DIR_READ;
1391     }
1392
1393     if (0 != (TRANS_MODE_CMD12_EN&transmode))
1394     {
1395         tmpReg |= SDIO_TRANS_AUTO_CMD12_EN;
1396     }
1397
1398     if (0 != (TRANS_MODE_BLOCK_COUNT_EN&transmode))
1399     {
1400         tmpReg |= SDIO_TRANS_BLK_CNT_EN;
1401     }
1402
1403     if (0 != (TRANS_MODE_DMA_EN&transmode))
1404     {
1405         tmpReg |= SDIO_TRANS_DMA_EN;
1406     }
1407
1408     if (0 != (CMD_HAVE_DATA&transmode))
1409     {
1410         tmpReg |= SDIO_CMD_DATA_PRESENT;
1411     }
1412
1413     switch (cmd_type)
1414     {
1415         case CMD_TYPE_NORMAL:
1416             {
1417                 tmpReg |= SDIO_CMD_TYPE_NML;
1418             }
1419             break;
1420
1421         case CMD_TYPE_SUSPEND:
1422             {
1423                 tmpReg |= SDIO_CMD_TYPE_SUSPEND;
1424             }
1425             break;
1426
1427         case CMD_TYPE_RESUME:
1428             {
1429                 tmpReg |= SDIO_CMD_TYPE_RESUME;
1430             }
1431             break;
1432
1433         case CMD_TYPE_ABORT:
1434             {
1435                 tmpReg |= SDIO_CMD_TYPE_ABORT;
1436             }
1437             break;
1438
1439         default:
1440             {
1441                 SCI_ASSERT (0);/*assert verified*/
1442             }
1443             break;
1444     }
1445
1446     switch (Response)
1447     {
1448         case CMD_NO_RSP:
1449             {
1450                 tmpReg |= SDIO_NO_RSP;
1451             }
1452             break;
1453
1454         case CMD_RSP_R1:
1455             {
1456                 tmpReg |= SDIO_R1;
1457             }
1458             break;
1459
1460         case CMD_RSP_R2:
1461             {
1462                 tmpReg |= SDIO_R2;
1463             }
1464             break;
1465
1466         case CMD_RSP_R3:
1467             {
1468                 tmpReg |= SDIO_R3;
1469             }
1470             break;
1471
1472         case CMD_RSP_R4:
1473             {
1474                 tmpReg |= SDIO_R4;
1475             }
1476             break;
1477
1478         case CMD_RSP_R5:
1479             {
1480                 tmpReg |= SDIO_R5;
1481             }
1482             break;
1483
1484         case CMD_RSP_R6:
1485             {
1486                 tmpReg |= SDIO_R6;
1487             }
1488             break;
1489
1490         case CMD_RSP_R7:
1491             {
1492                 tmpReg |= SDIO_R7;
1493             }
1494             break;
1495
1496         case CMD_RSP_R1B:
1497             {
1498                 tmpReg |= SDIO_R1B;
1499             }
1500             break;
1501
1502         case CMD_RSP_R5B:
1503             {
1504                 tmpReg |= SDIO_R5B;
1505             }
1506             break;
1507
1508         default:
1509             {
1510                 SCI_ASSERT (0);/*assert verified*/
1511             }
1512             break;
1513
1514     }
1515     tmpReg &= ~(0x7<<8);
1516     tmpReg |= (cmdIndex<<24);
1517
1518     sdhost_handler->host_cfg->CMD_TRANSMODE = tmpReg;
1519
1520 }
1521
1522
1523 //==
1524 /*****************************************************************************/
1525 //  Description: Get content from host response register
1526 //  Author: Jason.wu
1527 //  Param
1528 //      sdhost_handler: the handle of host driver
1529 //      Response:   the type of response
1530 //      rspBuf:     the content will be stored in this place
1531 //  Return:
1532 //      NONE
1533 //  Note:
1534 /*****************************************************************************/
1535 PUBLIC void SDHOST_GetRspFromBuf (SDHOST_HANDLE sdhost_handler,CMD_RSP_TYPE_E Response,uint8 *rspBuf)
1536 {
1537     uint32 tmpRspBuf[4];
1538     uint32 i;
1539
1540     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1541
1542     tmpRspBuf[0] = sdhost_handler->host_cfg->RSP0;
1543     tmpRspBuf[1] = sdhost_handler->host_cfg->RSP1;
1544     tmpRspBuf[2] = sdhost_handler->host_cfg->RSP2;
1545     tmpRspBuf[3] = sdhost_handler->host_cfg->RSP3;
1546
1547     //  SDHOST_PRINT(("RSP %x %x %x %x",tmpRspBuf[0],tmpRspBuf[1],tmpRspBuf[2],tmpRspBuf[3]));
1548
1549     for (i = 0; i < 4; i++)
1550     {
1551         rspBuf[0+ (i<<2) ] = (uint8) ( (tmpRspBuf[i]>>24) &0xFF);
1552         rspBuf[1+ (i<<2) ] = (uint8) ( (tmpRspBuf[i]>>16) &0xFF);
1553         rspBuf[2+ (i<<2) ] = (uint8) ( (tmpRspBuf[i]>>8) &0xFF);
1554         rspBuf[3+ (i<<2) ] = (uint8) (tmpRspBuf[i]&0xFF);
1555     }
1556
1557     switch (Response)
1558     {
1559         case CMD_NO_RSP:
1560             break;
1561
1562         case CMD_RSP_R1:
1563         case CMD_RSP_R1B:
1564         case CMD_RSP_R3:
1565         case CMD_RSP_R4:
1566         case CMD_RSP_R5:
1567         case CMD_RSP_R6:
1568         case CMD_RSP_R7:
1569         case CMD_RSP_R5B:
1570             {
1571                 rspBuf[0] = (uint8) ( (tmpRspBuf[0]>>24) &0xFF);
1572                 rspBuf[1] = (uint8) ( (tmpRspBuf[0]>>16) &0xFF);
1573                 rspBuf[2] = (uint8) ( (tmpRspBuf[0]>>8) &0xFF);
1574                 rspBuf[3] = (uint8) (tmpRspBuf[0]&0xFF);
1575             }
1576             break;
1577
1578         case CMD_RSP_R2:
1579             {
1580                 rspBuf[0] = (uint8) ( (tmpRspBuf[3]>>16) &0xFF);
1581                 rspBuf[1] = (uint8) ( (tmpRspBuf[3]>>8) &0xFF);
1582                 rspBuf[2] = (uint8) (tmpRspBuf[3]&0xFF);
1583
1584                 rspBuf[3] = (uint8) ( (tmpRspBuf[2]>>24) &0xFF);
1585                 rspBuf[4] = (uint8) ( (tmpRspBuf[2]>>16) &0xFF);
1586                 rspBuf[5] = (uint8) ( (tmpRspBuf[2]>>8) &0xFF);
1587                 rspBuf[6] = (uint8) (tmpRspBuf[2]&0xFF);
1588
1589                 rspBuf[7] = (uint8) ( (tmpRspBuf[1]>>24) &0xFF);
1590                 rspBuf[8] = (uint8) ( (tmpRspBuf[1]>>16) &0xFF);
1591                 rspBuf[9] = (uint8) ( (tmpRspBuf[1]>>8) &0xFF);
1592                 rspBuf[10] = (uint8) (tmpRspBuf[1]&0xFF);
1593
1594                 rspBuf[11] = (uint8) ( (tmpRspBuf[0]>>24) &0xFF);
1595                 rspBuf[12] = (uint8) ( (tmpRspBuf[0]>>16) &0xFF);
1596                 rspBuf[13] = (uint8) ( (tmpRspBuf[0]>>8) &0xFF);
1597                 rspBuf[14] = (uint8) (tmpRspBuf[0]&0xFF);
1598             }
1599             break;
1600
1601         default:
1602             {
1603                 SCI_ASSERT (0);/*assert verified*/
1604             }
1605             break;
1606     }
1607
1608     return;
1609 }
1610
1611
1612 //====
1613
1614 //----
1615 /*****************************************************************************/
1616 //  Description: Get function that host can be support
1617 //  Author: Jason.wu
1618 //  Param
1619 //      sdhost_handler: the handle of host driver
1620 //      capbility
1621 //  Return:
1622 //      NONE
1623 //  Note:
1624 /*****************************************************************************/
1625 LOCAL void __maybe_unused _GetSDHOSTCapbility (SDHOST_HANDLE sdhost_handler,SDHOST_CAPBILIT_T *capbility)
1626 {
1627     volatile uint32 tmpReg;
1628     SCI_MEMSET (capbility,0,sizeof (SDHOST_CAPBILIT_T));
1629
1630     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1631
1632     tmpReg = sdhost_handler->host_cfg->CAPBILITY;
1633
1634     if (0 != (tmpReg &  BIT_26))
1635     {
1636         capbility->capbility_function |= CAP_VOL_1_8V;
1637     }
1638
1639     if (0 != (tmpReg &  BIT_25))
1640     {
1641         capbility->capbility_function |= CAP_VOL_3_0V;
1642     }
1643
1644     if (0 != (tmpReg &  BIT_24))
1645     {
1646         capbility->capbility_function |= CAP_VOL_3_3V;
1647     }
1648
1649     if (0 != (tmpReg &  BIT_23))
1650     {
1651         capbility->capbility_function |= SPD_RESU;
1652     }
1653
1654     if (0 != (tmpReg &  BIT_22))
1655     {
1656         capbility->capbility_function |= DMA_SPT;
1657     }
1658
1659     if (0 != (tmpReg &  BIT_21))
1660     {
1661         capbility->capbility_function |= HIGH_SPEED;
1662     }
1663
1664     switch (tmpReg & (0x3<<16))
1665     {
1666         case (0x00<<16) :
1667             capbility->cability_Max_BlkLen = 512;
1668             break;
1669
1670         case (0x01<<16) :
1671             capbility->cability_Max_BlkLen = 1024;
1672             break;
1673
1674         case (0x02<<16) :
1675             capbility->cability_Max_BlkLen = 2048;
1676             break;
1677
1678         case (0x03<<16) :
1679             capbility->cability_Max_BlkLen = 4096;
1680             break;
1681
1682         default:
1683             SCI_ASSERT (0);/*assert verified*/
1684             break;
1685     }
1686
1687     capbility->sd_Base_Max_Clk = ( (tmpReg & (0x3F<<8)) >>8) * 1000000;
1688
1689     if (0!= (tmpReg & BIT_7))
1690     {
1691         capbility->timeOut_Clk_unit = 1000000;
1692     }
1693     else
1694     {
1695         capbility->timeOut_Clk_unit = 1000;
1696     }
1697
1698     capbility->timeOut_Base_Clk = (tmpReg & 0x3F) *capbility->timeOut_Clk_unit;
1699
1700     tmpReg = sdhost_handler->host_cfg->CURR_CAPBILITY;
1701     capbility->max_current_for_1_8 = ( (tmpReg & (0xFF<<16)) >>16);
1702     capbility->max_current_for_3_0 = ( (tmpReg & (0xFF<<8)) >>8);
1703     capbility->max_current_for_3_3 = (tmpReg & 0xFF);
1704
1705     SDHOST_PRINT ( ("capbility_function = %x",sdhost_handler->capbility.capbility_function));
1706     SDHOST_PRINT ( ("cability_Max_BlkLen = %x",sdhost_handler->capbility.cability_Max_BlkLen));
1707     SDHOST_PRINT ( ("sd_Base_Max_Clk = %x",sdhost_handler->capbility.sd_Base_Max_Clk));
1708     SDHOST_PRINT ( ("timeOut_Clk_unit = %x",sdhost_handler->capbility.timeOut_Clk_unit));
1709     SDHOST_PRINT ( ("timeOut_Base_Clk = %x",sdhost_handler->capbility.timeOut_Base_Clk));
1710     SDHOST_PRINT ( ("max_current_for_1_8 = %x",sdhost_handler->capbility.max_current_for_1_8));
1711     SDHOST_PRINT ( ("max_current_for_3_0 = %x",sdhost_handler->capbility.max_current_for_3_0));
1712     SDHOST_PRINT ( ("max_current_for_3_3 = %x",sdhost_handler->capbility.max_current_for_3_3));
1713 }
1714
1715
1716 /*****************************************************************************/
1717 //  Description: Clear Normal int Status register ,if event is happed ,host will Set status in register
1718 //  Author: Jason.wu
1719 //  Param
1720 //      sdhost_handler: the handle of host driver
1721 //      err_msg:        that int you want to clear
1722 //  Return:
1723 //      NONE
1724 //  Note:
1725 /*****************************************************************************/
1726 PUBLIC void SDHOST_NML_IntStatus_Clr (SDHOST_HANDLE sdhost_handler,uint32 msg)
1727 {
1728     volatile uint32 tmpReg = 0;
1729     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1730
1731     if (0 != (msg&SIG_ERR))
1732     {
1733         //_ERR_IntStatus_Clr (sdhost_handler,ERR_ALL);
1734         tmpReg |= (BIT_28|BIT_24|BIT_23|BIT_22|BIT_21|
1735                    BIT_20|BIT_19|BIT_18|BIT_17|BIT_16);
1736
1737     }
1738
1739     if (0 != (msg&SIG_CARD_IN))
1740     {
1741         //sdhost_handler->host_cfg->INT_STA =BIT_8;
1742     }
1743
1744     if (0 != (msg&SIG_CARD_INSERT))
1745     {
1746                 tmpReg |= BIT_6;
1747     }
1748
1749     if (0 != (msg&SIG_CARD_REMOVE))
1750     {
1751                 tmpReg |= BIT_7;
1752     }
1753
1754     if (0 != (msg&SIG_BUF_RD_RDY))
1755     {
1756                 tmpReg |= BIT_5;
1757     }
1758
1759     if (0 != (msg&SIG_BUF_WD_RDY))
1760     {
1761                 tmpReg |= BIT_4;
1762     }
1763
1764     if (0 != (msg&SIG_DMA_INT))
1765     {
1766                 tmpReg |= BIT_3;
1767     }
1768
1769     if (0 != (msg&SIG_BLK_CAP))
1770     {
1771                 tmpReg |= BIT_2;
1772     }
1773
1774     if (0 != (msg&SIG_TRANS_CMP))
1775     {
1776                 tmpReg |= BIT_1;
1777     }
1778
1779     if (0 != (msg&SIG_CMD_CMP))
1780     {
1781                 tmpReg |= BIT_0;
1782     }
1783     sdhost_handler->host_cfg->INT_STA = tmpReg;
1784 }
1785
1786 /*****************************************************************************/
1787 //  Description: Enable Normal int Signal register ,
1788 //  Author: Jason.wu
1789 //  Param
1790 //      sdhost_handler: the handle of host driver
1791 //      err_msg:        that int you want to Enable
1792 //  Return:
1793 //      NONE
1794 //  Note:
1795 /*****************************************************************************/
1796 PUBLIC void SDHOST_NML_IntStatus_En (SDHOST_HANDLE sdhost_handler,uint32 msg)
1797 {
1798     volatile uint32 tmpReg = 0;
1799     uint32 err_msg;
1800     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1801
1802     if (0 != (msg&SIG_ERR))
1803     {
1804         //_ERR_IntStatus_En (sdhost_handler,sdhost_handler->err_filter);
1805         err_msg = sdhost_handler->err_filter;
1806         if (0 != (err_msg&ERR_RSP))
1807         {
1808                 tmpReg |= BIT_28;
1809         }
1810
1811         if (0 != (err_msg&ERR_CMD12))
1812         {
1813                 tmpReg |= BIT_24;
1814         }
1815
1816         if (0 != (err_msg&ERR_CUR_LIMIT))
1817         {
1818                 tmpReg |= BIT_23;
1819         }
1820
1821         if (0 != (err_msg&ERR_DATA_END))
1822         {
1823                 tmpReg |= BIT_22;
1824         }
1825
1826         if (0 != (err_msg&ERR_DATA_CRC))
1827         {
1828                 tmpReg |= BIT_21;
1829         }
1830
1831         if (0 != (err_msg&ERR_DATA_TIMEOUT))
1832         {
1833                 tmpReg |= BIT_20;
1834         }
1835
1836         if (0 != (err_msg&ERR_CMD_INDEX))
1837         {
1838                 tmpReg |= BIT_19;
1839         }
1840
1841         if (0 != (err_msg&ERR_CMD_END))
1842         {
1843                 tmpReg |= BIT_18;
1844         }
1845
1846         if (0 != (err_msg&ERR_CMD_CRC))
1847         {
1848                 tmpReg |= BIT_17;
1849         }
1850
1851         if (0 != (err_msg&ERR_CMD_TIMEOUT))
1852         {
1853                 tmpReg |= BIT_16;
1854         }
1855
1856     }
1857
1858     if (0 != (msg&SIG_CARD_IN))
1859     {
1860                 tmpReg |= BIT_8;
1861     }
1862
1863     if (0 != (msg&SIG_CARD_INSERT))
1864     {
1865                 tmpReg |= BIT_6;
1866     }
1867
1868     if (0 != (msg&SIG_CARD_REMOVE))
1869     {
1870                 tmpReg |= BIT_7;
1871     }
1872
1873     if (0 != (msg&SIG_BUF_RD_RDY))
1874     {
1875                 tmpReg |= BIT_5;
1876     }
1877
1878     if (0 != (msg&SIG_BUF_WD_RDY))
1879     {
1880                 tmpReg |= BIT_4;
1881     }
1882
1883     if (0 != (msg&SIG_DMA_INT))
1884     {
1885                 tmpReg |= BIT_3;
1886     }
1887
1888     if (0 != (msg&SIG_BLK_CAP))
1889     {
1890                 tmpReg |= BIT_2;
1891     }
1892
1893     if (0 != (msg&SIG_TRANS_CMP))
1894     {
1895                 tmpReg |= BIT_1;
1896     }
1897
1898     if (0 != (msg&SIG_CMD_CMP))
1899     {
1900                 tmpReg |= BIT_0;
1901     }
1902     sdhost_handler->host_cfg->INT_STA_EN |= tmpReg;
1903     sdhost_handler->IntEnabled = sdhost_handler->host_cfg->INT_STA_EN;
1904
1905 }
1906
1907 /*****************************************************************************/
1908 //  Description: Disable Normal int Signal register
1909 //  Author: Jason.wu
1910 //  Param
1911 //      sdhost_handler: the handle of host driver
1912 //      err_msg:        that int you want to Disable
1913 //  Return:
1914 //      NONE
1915 //  Note:
1916 /*****************************************************************************/
1917 PUBLIC void SDHOST_NML_IntStatus_Dis (SDHOST_HANDLE sdhost_handler,uint32 msg)
1918 {
1919     volatile uint32 tmpReg = 0;
1920     uint32 reg_value = sdhost_handler->IntEnabled;
1921     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1922
1923     if (0 != (msg&SIG_ERR))
1924     {
1925         //_ERR_IntStatus_Dis (sdhost_handler,ERR_ALL);
1926         tmpReg |= (BIT_28|BIT_24|BIT_23|BIT_22|BIT_21|
1927                    BIT_20|BIT_19|BIT_18|BIT_17|BIT_16);
1928
1929     }
1930
1931     if (0 != (msg&SIG_CARD_IN))
1932     {
1933                 tmpReg |= BIT_8;
1934     }
1935
1936     if (0 != (msg&SIG_CARD_INSERT))
1937     {
1938                 tmpReg |= BIT_6;
1939     }
1940
1941     if (0 != (msg&SIG_CARD_REMOVE))
1942     {
1943                 tmpReg |= BIT_7;
1944     }
1945
1946     if (0 != (msg&SIG_BUF_RD_RDY))
1947     {
1948                 tmpReg |= BIT_5;
1949     }
1950
1951     if (0 != (msg&SIG_BUF_WD_RDY))
1952     {
1953                 tmpReg |= BIT_4;
1954     }
1955
1956     if (0 != (msg&SIG_DMA_INT))
1957     {
1958                 tmpReg |= BIT_3;
1959     }
1960
1961     if (0 != (msg&SIG_BLK_CAP))
1962     {
1963                 tmpReg |= BIT_2;
1964     }
1965
1966     if (0 != (msg&SIG_TRANS_CMP))
1967     {
1968                 tmpReg |= BIT_1;
1969     }
1970
1971     if (0 != (msg&SIG_CMD_CMP))
1972     {
1973                 tmpReg |= BIT_0;
1974     }
1975     reg_value &= ~tmpReg;
1976     sdhost_handler->host_cfg->INT_STA_EN = reg_value;
1977     sdhost_handler->IntEnabled = reg_value;
1978
1979 }
1980
1981 /*****************************************************************************/
1982 //  Description: Enable Normal int Signal register ,if normal event  is happed ,host will send interrupt to Arm
1983 //  Author: Jason.wu
1984 //  Param
1985 //      sdhost_handler: the handle of host driver
1986 //      err_msg:        that int you want to Enable
1987 //  Return:
1988 //      NONE
1989 //  Note:
1990 /*****************************************************************************/
1991 PUBLIC void SDHOST_NML_IntSig_En (SDHOST_HANDLE sdhost_handler,uint32 msg)
1992 {
1993     volatile uint32 tmpReg = 0;
1994     uint32 err_msg;
1995     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1996
1997     if (0 != (msg&SIG_ERR))
1998     {
1999         //_ERR_IntSig_En (sdhost_handler,sdhost_handler->err_filter);
2000         err_msg = sdhost_handler->err_filter;
2001         if (0 != (err_msg&ERR_RSP))
2002         {
2003                 tmpReg |= BIT_28;
2004         }
2005
2006         if (0 != (err_msg&ERR_CMD12))
2007         {
2008                 tmpReg |= BIT_24;
2009         }
2010
2011         if (0 != (err_msg&ERR_CUR_LIMIT))
2012         {
2013                 tmpReg |= BIT_23;
2014         }
2015
2016         if (0 != (err_msg&ERR_DATA_END))
2017         {
2018                 tmpReg |= BIT_22;
2019         }
2020
2021         if (0 != (err_msg&ERR_DATA_CRC))
2022         {
2023                 tmpReg |= BIT_21;
2024         }
2025
2026         if (0 != (err_msg&ERR_DATA_TIMEOUT))
2027         {
2028                 tmpReg |= BIT_20;
2029         }
2030
2031         if (0 != (err_msg&ERR_CMD_INDEX))
2032         {
2033                 tmpReg |= BIT_19;
2034         }
2035
2036         if (0 != (err_msg&ERR_CMD_END))
2037         {
2038                 tmpReg |= BIT_18;
2039         }
2040
2041         if (0 != (err_msg&ERR_CMD_CRC))
2042         {
2043                 tmpReg |= BIT_17;
2044         }
2045
2046         if (0 != (err_msg&ERR_CMD_TIMEOUT))
2047         {
2048                 tmpReg |= BIT_16;
2049         }
2050
2051     }
2052
2053     if (0 != (msg&SIG_CARD_IN))
2054     {
2055                 tmpReg |= BIT_8;
2056     }
2057
2058     if (0 != (msg&SIG_CARD_INSERT))
2059     {
2060                 tmpReg |= BIT_6;
2061     }
2062
2063     if (0 != (msg&SIG_CARD_REMOVE))
2064     {
2065                 tmpReg |= BIT_7;
2066     }
2067
2068     if (0 != (msg&SIG_BUF_RD_RDY))
2069     {
2070                 tmpReg |= BIT_5;
2071     }
2072
2073     if (0 != (msg&SIG_BUF_WD_RDY))
2074     {
2075                 tmpReg |= BIT_4;
2076     }
2077
2078     if (0 != (msg&SIG_DMA_INT))
2079     {
2080                 tmpReg |= BIT_3;
2081     }
2082
2083     if (0 != (msg&SIG_BLK_CAP))
2084     {
2085                 tmpReg |= BIT_2;
2086     }
2087
2088     if (0 != (msg&SIG_TRANS_CMP))
2089     {
2090                 tmpReg |= BIT_1;
2091     }
2092
2093     if (0 != (msg&SIG_CMD_CMP))
2094     {
2095                 tmpReg |= BIT_0;
2096     }
2097         sdhost_handler->host_cfg->INT_SIG_EN |= tmpReg;
2098
2099 }
2100
2101 /*****************************************************************************/
2102 //  Description: Disable Normal int Signal register ,if normal event  is happed ,host will not send interrupt to Arm
2103 //  Author: Jason.wu
2104 //  Param
2105 //      sdhost_handler: the handle of host driver
2106 //      err_msg:        that int you want to Disable
2107 //  Return:
2108 //      NONE
2109 //  Note:
2110 /*****************************************************************************/
2111 PUBLIC void SDHOST_NML_IntSig_Dis (SDHOST_HANDLE sdhost_handler,uint32 msg)
2112 {
2113     volatile uint32 tmpReg = 0;
2114     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2115
2116     if (0 != (msg&SIG_ERR))
2117     {
2118         //_ERR_IntSig_Dis (sdhost_handler,ERR_ALL);
2119         tmpReg |= (BIT_28|BIT_24|BIT_23|BIT_22|BIT_21|
2120                    BIT_20|BIT_19|BIT_18|BIT_17|BIT_16);
2121
2122     }
2123
2124     if (0 != (msg&SIG_CARD_IN))
2125     {
2126                 tmpReg |= BIT_8;
2127     }
2128
2129     if (0 != (msg&SIG_CARD_INSERT))
2130     {
2131                 tmpReg |= BIT_6;
2132     }
2133
2134     if (0 != (msg&SIG_CARD_REMOVE))
2135     {
2136                 tmpReg |= BIT_7;
2137     }
2138
2139     if (0 != (msg&SIG_BUF_RD_RDY))
2140     {
2141                 tmpReg |= BIT_5;
2142     }
2143
2144     if (0 != (msg&SIG_BUF_WD_RDY))
2145     {
2146                 tmpReg |= BIT_4;
2147     }
2148
2149     if (0 != (msg&SIG_DMA_INT))
2150     {
2151                 tmpReg |= BIT_3;
2152     }
2153
2154     if (0 != (msg&SIG_BLK_CAP))
2155     {
2156                 tmpReg |= BIT_2;
2157     }
2158
2159     if (0 != (msg&SIG_TRANS_CMP))
2160     {
2161                 tmpReg |= BIT_1;
2162     }
2163
2164     if (0 != (msg&SIG_CMD_CMP))
2165     {
2166                 tmpReg |= BIT_0;
2167     }
2168         sdhost_handler->host_cfg->INT_SIG_EN &= ~tmpReg;
2169
2170 }
2171
2172 /*****************************************************************************/
2173 //  Description: Get normal int status register ,to confirm which normal event has happened
2174 //  Author: Jason.wu
2175 //  Param
2176 //      sdhost_handler: the handle of host driver
2177 //  Return:
2178 //      uint32 value: indicate which event happened
2179 //  Note:
2180 /*****************************************************************************/
2181 PUBLIC uint32 SDHOST_GetNMLIntStatus (SDHOST_HANDLE sdhost_handler)
2182 {
2183     volatile uint32 tmpReg;
2184     uint32 msg;
2185
2186     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2187
2188     tmpReg = sdhost_handler->host_cfg->INT_STA;
2189     msg = 0;
2190
2191     if (0 != (tmpReg & BIT_15))
2192     {
2193         msg |= SIG_ERR;
2194     }
2195
2196     if (0 != (tmpReg & BIT_8))
2197     {
2198         msg |= SIG_CARD_IN;
2199     }
2200
2201     if (0 != (tmpReg & BIT_6))
2202     {
2203         msg |= SIG_CARD_INSERT;
2204     }
2205
2206     if (0 != (tmpReg & BIT_7))
2207     {
2208         msg |= SIG_CARD_REMOVE;
2209     }
2210
2211     if (0 != (tmpReg & BIT_5))
2212     {
2213         msg |= SIG_BUF_RD_RDY;
2214     }
2215
2216     if (0 != (tmpReg & BIT_4))
2217     {
2218         msg |= SIG_BUF_WD_RDY;
2219     }
2220
2221     if (0 != (tmpReg & BIT_3))
2222     {
2223         msg |= SIG_DMA_INT;
2224     }
2225
2226     if (0 != (tmpReg & BIT_2))
2227     {
2228         msg |= SIG_BLK_CAP;
2229     }
2230
2231     if (0 != (tmpReg & BIT_1))
2232     {
2233         msg |= SIG_TRANS_CMP;
2234     }
2235
2236     if (0 != (tmpReg & BIT_0))
2237     {
2238         msg |= SIG_CMD_CMP;
2239     }
2240
2241     return msg;
2242 }
2243
2244
2245 /*****************************************************************************/
2246 //  Description: if error interrupt happened ,this function is used to confirm which error event happened
2247 //  Author: Jason.wu
2248 //  Param
2249 //      sdhost_handler: the handle of host driver
2250 //  Return:
2251 //      uint32 value: indicate which error event happened
2252 //  Note:
2253 /*****************************************************************************/
2254 PUBLIC uint32 SDHOST_GetErrCode (SDHOST_HANDLE sdhost_handler)
2255 {
2256     volatile uint32 tmpReg;
2257     uint32 err_msg;
2258
2259     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2260
2261     tmpReg = sdhost_handler->host_cfg->INT_STA;
2262     err_msg = 0;
2263
2264     if (0 != (tmpReg & BIT_28))
2265     {
2266         err_msg |= ERR_RSP;
2267     }
2268
2269     if (0 != (tmpReg & BIT_24))
2270     {
2271         err_msg |= ERR_CMD12;
2272     }
2273
2274     if (0 != (tmpReg & BIT_23))
2275     {
2276         err_msg |= ERR_CUR_LIMIT;
2277     }
2278
2279     if (0 != (tmpReg & BIT_22))
2280     {
2281         err_msg |= ERR_DATA_END;
2282     }
2283
2284     if (0 != (tmpReg & BIT_21))
2285     {
2286         err_msg |= ERR_DATA_CRC;
2287     }
2288
2289     if (0 != (tmpReg & BIT_20))
2290     {
2291         err_msg |= ERR_DATA_TIMEOUT;
2292     }
2293
2294     if (0 != (tmpReg & BIT_19))
2295     {
2296         err_msg |= ERR_CMD_INDEX;
2297     }
2298
2299     if (0 != (tmpReg & BIT_18))
2300     {
2301         err_msg |= ERR_CMD_END;
2302     }
2303
2304     if (0 != (tmpReg & BIT_17))
2305     {
2306         err_msg |= ERR_CMD_CRC;
2307     }
2308
2309     if (0 != (tmpReg & BIT_16))
2310     {
2311         err_msg |= ERR_CMD_TIMEOUT;
2312     }
2313
2314     return err_msg;
2315 }
2316
2317 /*****************************************************************************/
2318 //  Description: this function is used to set which error event you want to watched ,other error event will be ignored if happened
2319 //  Author: Jason.wu
2320 //  Param
2321 //      sdhost_handler: the handle of host driver
2322 //      err_msg:        the event you want to watched
2323 //  Return:
2324 //      NONE
2325 //  Note:
2326 /*****************************************************************************/
2327 PUBLIC void SDHOST_SetErrCodeFilter (SDHOST_HANDLE sdhost_handler,uint32 err_msg)
2328 {
2329     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2330
2331     sdhost_handler->err_filter = err_msg;
2332 }
2333
2334 /*****************************************************************************/
2335 //  Description: To indicate event that happened from which slot
2336 //  Author: Jason.wu
2337 //  Param
2338 //      sdhost_handler: the handle of host driver
2339 //  Return:
2340 //      uint32 value: indicate which slot event happened
2341 //  Note:
2342 /*****************************************************************************/
2343 LOCAL SDHOST_SLOT_NO __maybe_unused _GetIntSDHOSTSlotNum (uint32 port)
2344 {
2345     SDHOST_SLOT_NO ret;
2346 #if defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
2347     ret = SDHOST_SLOT_7;
2348 #else
2349     uint32 tmpReg;
2350 #if defined(CONFIG_TIGER)|| defined (CONFIG_SC7710G2)
2351     if(SDHOST_SLOT_6 == port){
2352         tmpReg = REG32 (SDIO2_NML_INT_SIG_EN);
2353         if(tmpReg == 0)
2354                 REG32 (SDIO2_NML_INT_SIG_EN) = BIT_1;
2355         tmpReg = REG32 (SDIO2_SLOT_INT_STS);
2356         tmpReg &= 0x01;
2357     }
2358     else
2359         tmpReg = REG32 (EMMC_SLOT_INT_STS);
2360 #else
2361     if(port == 0){
2362         tmpReg = REG32 (SDIO0_SLOT_INT_STS);
2363     }
2364     else
2365     {
2366         tmpReg = REG32 (SDIO1_SLOT_INT_STS);
2367     }
2368 #endif
2369
2370     if ( (tmpReg& (0x01<<0)))
2371     {
2372 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
2373         if(SDHOST_SLOT_6 == port)
2374                 ret = SDHOST_SLOT_6;
2375         else
2376                 ret = SDHOST_SLOT_7;
2377 #else
2378                 if(port == 0){
2379                         ret = SDHOST_SLOT_0;
2380                 }else{
2381                 ret = SDHOST_SLOT_1;
2382                 }
2383 #endif
2384     }
2385     else if ( (tmpReg& (0x01<<1)))
2386     {
2387         ret = SDHOST_SLOT_1;
2388     }
2389     else if ( (tmpReg& (0x01<<2)))
2390     {
2391         ret = SDHOST_SLOT_2;
2392     }
2393     else if ( (tmpReg& (0x01<<3)))
2394     {
2395         ret = SDHOST_SLOT_3;
2396     }
2397     else if ( (tmpReg& (0x01<<4)))
2398     {
2399         ret = SDHOST_SLOT_4;
2400     }
2401     else if ( (tmpReg& (0x01<<5)))
2402     {
2403         ret = SDHOST_SLOT_5;
2404     }
2405     else if ( (tmpReg& (0x01<<6)))
2406     {
2407         ret = SDHOST_SLOT_6;
2408     }
2409     else if ( (tmpReg& (0x01<<7)))
2410     {
2411         ret = SDHOST_SLOT_7;
2412     }
2413     else
2414     {
2415         ret = SDHOST_SLOT_MAX_NUM;
2416         SCI_ASSERT (0);/*assert to do*/
2417     }
2418 #endif
2419     return ret;
2420 }
2421
2422 /*****************************************************************************/
2423 //  Description: This function is called by interrupt service .is event happened ,this funtion will
2424 //  clear the event and call the callback of application
2425 //  Author: Jason.wu
2426 //  Param
2427 //      isrnum: the number of arm interrupt
2428 //  Return:
2429 //      NONE
2430 //  Note:
2431 /*****************************************************************************/
2432 PUBLIC ISR_EXE_T _SDHOST_IrqHandle (uint32 isrnum)
2433 {
2434     ISR_Buffer_T buffer;
2435     SDHOST_HANDLE sdhost_handler;
2436
2437     buffer.slotNum = isrnum;
2438     if(buffer.slotNum == SDHOST_SLOT_MAX_NUM){
2439         return ISR_DONE;
2440     }
2441     sdhost_handler = &sdio_port_ctl[buffer.slotNum];
2442     buffer.pSdhost_handler = &sdio_port_ctl[buffer.slotNum];
2443
2444     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2445
2446     if (FALSE == sdhost_handler->open_flag)
2447     {
2448         SDHOST_NML_IntSig_Dis (sdhost_handler, SIG_ALL);
2449         SDHOST_NML_IntStatus_Dis (sdhost_handler, SIG_ALL);
2450         SDHOST_NML_IntStatus_Clr (sdhost_handler, SIG_ALL);
2451         return ISR_DONE;
2452     }
2453
2454     if (NULL == sdhost_handler->sigCallBack)
2455     {
2456         SDHOST_NML_IntSig_Dis (sdhost_handler, SIG_ALL);
2457         SDHOST_NML_IntStatus_Dis (sdhost_handler, SIG_ALL);
2458         SDHOST_NML_IntStatus_Clr (sdhost_handler, SIG_ALL);
2459         return ISR_DONE;
2460     }
2461
2462     buffer.msg = SDHOST_GetNMLIntStatus (sdhost_handler);
2463     buffer.errCode = SDHOST_GetErrCode (sdhost_handler);
2464
2465     SDHOST_NML_IntSig_Dis (sdhost_handler, buffer.msg);
2466     SDHOST_NML_IntStatus_Dis (sdhost_handler, buffer.msg);
2467     SDHOST_NML_IntStatus_Clr (sdhost_handler, buffer.msg);
2468 #ifndef OS_NONE
2469     IsrWriteBuffer (buffer);
2470 #else
2471         sdhost_handler->sigCallBack (buffer.msg, buffer.errCode, buffer.slotNum);
2472 #endif
2473
2474     return CALL_HISR;
2475 }
2476
2477 #ifndef OS_NONE
2478 /*****************************************************************************/
2479 //  Description:    This function is SDIO 's HISR.
2480 //                  1. THE priority is higher than normal task.
2481 //                  2. Is not real ISR.
2482 //  Author:         steve.zhan
2483 //  Note:
2484 /*****************************************************************************/
2485 LOCAL void  SdhostHisrFunc (uint32 cnt, void *pData)
2486 {
2487     ISR_Buffer_T buffer;
2488
2489     while (!threadReadBuffer (&buffer))
2490     {
2491         buffer.pSdhost_handler->sigCallBack (buffer.msg, buffer.errCode, buffer.slotNum);
2492     }
2493 }
2494 #endif
2495
2496 #if !defined (CONFIG_SC8825) && !defined(CONFIG_SPX15) && !defined(CONFIG_SPX30G) && !defined(CONFIG_SC9630) && !defined (CONFIG_SC8830) && !defined(CONFIG_SC7710G2)
2497 LOCAL void _SDHOST_Pin_select(SDHOST_SLOT_NO slot_NO)
2498 {
2499     if(slot_NO == SDHOST_SLOT_1){
2500         *(volatile uint32*)(0x8c0003e8) = 0x280;    //SD1 CMD pullup drv3, strongest strength
2501         *(volatile uint32*)(0x8c0003ec) = 0x280;    //SD1 D0 pullup drv3, strongest strength
2502         *(volatile uint32*)(0x8c0003f0) = 0x280;    //SD1 D1 pullup drv3, strongest strength
2503         *(volatile uint32*)(0x8c0003f4) = 0x280;    //SD1 D2 pullup drv3, strongest strength
2504         *(volatile uint32*)(0x8c0003f8) = 0x280;    //SD1 D3 pullup drv3, strongest strength
2505         *(volatile uint32*)(0x8c0003fc) = 0x280;    //SD1 D3 pullup drv3, strongest strength
2506     }
2507 }
2508 #endif
2509
2510 /*****************************************************************************/
2511 //  Description: Regist host slot
2512 //  Author: Jason.wu
2513 //  Param
2514 //      slot_NO:    which slot you want to used
2515 //      fun:        this function will be called when event happened
2516 //  Return:
2517 //      Not zero: succes
2518 //      zeror: fail
2519 //  Note:
2520 /*****************************************************************************/
2521 PUBLIC SDHOST_HANDLE SDHOST_Register (SDHOST_SLOT_NO slot_NO,SDIO_CALLBACK fun)
2522 {
2523 #ifndef OS_NONE
2524     uint32 status = 0;
2525 #endif
2526
2527     SCI_ASSERT (slot_NO < SDHOST_SLOT_MAX_NUM);/*assert verified*/
2528
2529     if (TRUE == sdio_port_ctl[slot_NO].open_flag)
2530     {
2531         return NULL;
2532     }
2533         if (slot_NO == SDHOST_SLOT_7)
2534         {
2535                 sdio_port_ctl[slot_NO].host_cfg =
2536                                                         (SDIO_REG_CFG *) ( (volatile uint32 *) EMMC_BASE_ADDR);
2537                 SDHOST_SD_clk_OnOff(&sdio_port_ctl[slot_NO], CLK_OFF);
2538         }
2539         SDHOST_Reset_Controller(slot_NO);
2540         sdio_port_ctl[slot_NO].slotNo = slot_NO;
2541     // select slot 0
2542 #if defined (CONFIG_SC8825) || defined(CONFIG_SPX15)||defined(CONFIG_SPX30G) || (defined CONFIG_SC9630)/*CONFIG_SPX15 must be before CONFIG_SC8830*/
2543         sdio_port_ctl[slot_NO].open_flag = TRUE;
2544         #if defined(CONFIG_ARCH_SCX20L) || defined(CONFIG_SPX20)
2545         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_192M);
2546         #else
2547         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_384M);
2548         #endif
2549 #elif defined (CONFIG_SC8830)
2550         sdio_port_ctl[slot_NO].open_flag = TRUE;
2551         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_192M);
2552 #elif defined(CONFIG_SC7710G2)
2553 //    SDHOST_Slot_select(slot_NO); if necessary
2554         sdio_port_ctl[slot_NO].open_flag = TRUE;
2555         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_96M);
2556 #else
2557         _SDHOST_Pin_select(slot_NO);
2558         sdio_port_ctl[slot_NO].open_flag = TRUE;
2559         sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_48M);
2560 #endif
2561
2562 #if defined(CONFIG_FPGA)
2563         sdio_port_ctl[slot_NO].baseClock = 36000000;
2564 #endif
2565
2566     switch (slot_NO)
2567     {
2568         case SDHOST_SLOT_0:
2569             {
2570                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO0_BASE_ADDR);
2571             }
2572             break;
2573
2574         case SDHOST_SLOT_1:
2575             {
2576 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
2577                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO0_BASE_ADDR+0x100) );
2578 #else
2579                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO1_BASE_ADDR);
2580 #endif
2581             }
2582             break;
2583
2584         case SDHOST_SLOT_2:
2585 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2)
2586             {
2587                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO2_BASE_ADDR) );
2588             }
2589             break;
2590 #endif
2591         case SDHOST_SLOT_3:
2592 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2)
2593             {
2594                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO1_BASE_ADDR );
2595             }
2596             break;
2597 #endif
2598         case SDHOST_SLOT_4:
2599 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2)
2600             {
2601                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO1_BASE_ADDR+0x100) );
2602             }
2603             break;
2604 #endif
2605         case SDHOST_SLOT_5:
2606 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2)
2607             {
2608                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO1_BASE_ADDR+0x200) );
2609             }
2610             break;
2611 #endif
2612         case SDHOST_SLOT_6:
2613                         REG32(REG_PIN_SD0_CLK0)= 0x300;
2614                         REG32(REG_PIN_SD0_CLK1)= 0x300;
2615                         REG32(REG_PIN_SD0_CMD) = 0x280;
2616                         REG32(REG_PIN_SD0_D0)  = 0x280;
2617                         REG32(REG_PIN_SD0_D0)  = 0x280;
2618                         REG32(REG_PIN_SD0_D1)  = 0x280;
2619                         REG32(REG_PIN_SD0_D2)  = 0x280;
2620                         sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO0_BASE_ADDR );
2621             break;
2622         case SDHOST_SLOT_7:
2623 #if defined(CONFIG_TIGER)       || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
2624 #ifdef CONFIG_SC8825
2625                         REG32(PIN_CTL3_REG)  |= (0x1ff<<8);//  set emmc data line, cmd line pull up resistor 4.7k
2626                         REG32(PIN_SD3CLK_REG) = 0x200;
2627                         REG32(PIN_SD3CMD_REG)= 0x280;
2628                         REG32(PIN_SD3D0_REG) = 0x280;
2629                         REG32(PIN_SD3D1_REG) = 0x280;
2630                         REG32(PIN_SD3D2_REG) = 0x280;
2631                         REG32(PIN_SD3D3_REG) = 0x280;
2632                         REG32(PIN_SD3D4_REG) = 0x280;
2633                         REG32(PIN_SD3D5_REG) = 0x280;
2634                         REG32(PIN_SD3D6_REG) = 0x280;
2635                         REG32(PIN_SD3D7_REG) = 0x280;
2636 #elif defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
2637 #ifndef CONFIG_FPGA
2638 #ifdef CONFIG_SPX15
2639 #define REG_PIN_EMMC_CLK     REG_PIN_NFREN
2640 #define REG_PIN_EMMC_CMD     REG_PIN_NFRB
2641 #define REG_PIN_EMMC_D0      REG_PIN_NFWPN
2642 #define REG_PIN_EMMC_D1      REG_PIN_NFD11
2643 #define REG_PIN_EMMC_D2      REG_PIN_NFD14
2644 #define REG_PIN_EMMC_D3      REG_PIN_NFD7
2645 #define REG_PIN_EMMC_D4      REG_PIN_NFD5
2646 #define REG_PIN_EMMC_D5      REG_PIN_NFD4
2647 #define REG_PIN_EMMC_D6      REG_PIN_NFCLE
2648 #define REG_PIN_EMMC_D7      REG_PIN_NFALE
2649                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x210;
2650                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x1198;
2651                         REG32(CTL_PIN_BASE+REG_PIN_NFD10)   = 0x198;
2652                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x198;
2653                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x198;
2654                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x198;
2655                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x198;
2656                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x198;
2657                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x198;
2658                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x198;
2659                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x198;
2660 #elif defined(CONFIG_SPX30G)
2661 #if defined(CONFIG_SPX20)
2662 #define REG_PIN_EMMC_CLK     REG_PIN_NFREN
2663 #define REG_PIN_EMMC_CMD     REG_PIN_NFRBN
2664 #define REG_PIN_EMMC_D0      REG_PIN_NFWPN
2665 #define REG_PIN_EMMC_D1      REG_PIN_NFD11
2666 #define REG_PIN_EMMC_D2      REG_PIN_NFD14
2667 #define REG_PIN_EMMC_D3      REG_PIN_NFD7
2668 #define REG_PIN_EMMC_D4      REG_PIN_NFD5
2669 #define REG_PIN_EMMC_D5      REG_PIN_NFD4
2670 #define REG_PIN_EMMC_D6      REG_PIN_NFCLE
2671 #define REG_PIN_EMMC_D7      REG_PIN_NFALE
2672                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x80010;
2673                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x80090;
2674                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x80090;
2675                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x80090;
2676                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x80090;
2677                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x80090;
2678                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x80090;
2679                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x80090;
2680                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x80090;
2681                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x80090;
2682 #else   /* TIZEN */
2683                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x00;
2684                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x80;
2685                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x80;
2686                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x80;
2687                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x80;
2688                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x80;
2689                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x80;
2690                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x80;
2691                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x80;
2692                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x80;
2693 #if 0
2694                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x80000;
2695                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x80080;
2696                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x80080;
2697                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x80080;
2698                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x80080;
2699                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x80080;
2700                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x80080;
2701                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x80080;
2702                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x80080;
2703                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x80080;
2704 #endif
2705 #endif
2706 #elif defined(CONFIG_SC9630)
2707 #define REG_PIN_EMMC_CLK   REG_PIN_NFREN
2708 #define REG_PIN_EMMC_CMD  REG_PIN_NFRB
2709 #define REG_PIN_EMMC_D0      REG_PIN_NFWPN
2710 #define REG_PIN_EMMC_D1      REG_PIN_NFD11
2711 #define REG_PIN_EMMC_D2      REG_PIN_NFD14
2712 #define REG_PIN_EMMC_D3      REG_PIN_NFD7
2713 #define REG_PIN_EMMC_D4      REG_PIN_NFD5
2714 #define REG_PIN_EMMC_D5      REG_PIN_NFD4
2715 #define REG_PIN_EMMC_D6      REG_PIN_NFCLE
2716 #define REG_PIN_EMMC_D7      REG_PIN_NFALE
2717                         sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO0_BASE_ADDR );
2718
2719                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x82011;
2720                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x83094;
2721                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x3094;
2722                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x3094;
2723                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x3094;
2724                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x3094;
2725                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x3094;
2726                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x3094;
2727                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x3094;
2728                         REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x3094;
2729 #else
2730         /* Other chip,do nothing*/
2731 #endif
2732 #endif /* CONFIG_FPGA */
2733 #endif
2734             {
2735                 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) EMMC_BASE_ADDR);
2736             }
2737             break;
2738 #endif
2739         default:
2740             {
2741                 SCI_ASSERT (0);/*assert to do*/
2742             }
2743             break;
2744     }
2745     sdio_port_ctl[slot_NO].sigCallBack = fun;
2746     sdio_port_ctl[slot_NO].err_filter = 0;
2747
2748 #ifndef OS_NONE
2749     status = ISR_RegHandler_Ex (TB_SDIO_INT, (TB_ISR) _SDHOST_IrqHandle, SdhostHisrFunc, CHIPDRV_HISR_PRIO_1, NULL);
2750     if (TB_SUCCESS == status)
2751     {
2752         CHIPDRV_EnableIRQINT (TB_SDIO_INT);
2753     }
2754 #endif
2755     return &sdio_port_ctl[slot_NO];
2756 }
2757
2758 /*****************************************************************************/
2759 //  Description: Free the slot resource
2760 //  Author: Jason.wu
2761 //  Param
2762 //      sdhost_handler: the handler of host driver ,this is returned by SDHOST_Register
2763 //  Return:
2764 //      Not zero: succes
2765 //      zeror: fail
2766 //  Note:
2767 /*****************************************************************************/
2768 PUBLIC BOOLEAN SDHOST_UnRegister (SDHOST_HANDLE sdhost_handler)
2769 {
2770     SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2771
2772     SDHOST_SD_POWER (sdhost_handler,POWR_OFF);
2773     SDHOST_RST (sdhost_handler,RST_ALL);
2774     SDHOST_SD_clk_OnOff (sdhost_handler,CLK_OFF);
2775     SDHOST_internalClk_OnOff (sdhost_handler,CLK_OFF);
2776     sdhost_handler->sigCallBack = NULL;
2777     sdhost_handler->open_flag = FALSE;
2778     return TRUE;
2779 }
2780
2781 //====================
2782 //---External function---
2783 //====================
2784 /*****************************************************************************/
2785 //  Description: Set basic clk of host,card clk will divided from this clk
2786 //  Author: Jason.wu
2787 //  Param
2788 //      sdhost_handler: the handler of host driver ,this is returned by SDHOST_Register
2789 //      sdio_base_clk: the frequecy that you want to set
2790 //  Return:
2791 //      uint32 value :the frequency that be used acctually
2792 //  Note: This function must be applied according different platform
2793 /*****************************************************************************/
2794 #ifndef OS_NONE
2795 #if 0
2796 PUBLIC uint32 SDHOST_BaseClk_Set (uint32 sdio_base_clk)
2797 {
2798 #ifdef  PLATFORM_SC8800G
2799     uint32 clk = 0;
2800
2801     //Select the clk source of SDIO
2802     if (sdio_base_clk >= SDIO_BASE_CLK_96M)
2803     {
2804         DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_96M);
2805         clk = SDIO_BASE_CLK_96M;
2806     }
2807     else if (sdio_base_clk >= SDIO_BASE_CLK_64M)
2808     {
2809         clk = SDIO_BASE_CLK_64M;
2810         DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_64M);
2811
2812     }
2813     else if (sdio_base_clk >= SDIO_BASE_CLK_48M)
2814     {
2815         clk = SDIO_BASE_CLK_48M;
2816         DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_48M);
2817     }
2818     else
2819     {
2820         clk = SDIO_BASE_CLK_26M;
2821         DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_26M);
2822     }
2823
2824     return clk;
2825 #endif
2826 }
2827 #endif
2828 #else
2829 PUBLIC uint32 SDHOST_BaseClk_Set(SDHOST_SLOT_NO slot_NO,uint32 sdio_base_clk)
2830 {
2831     uint32 clk = 0;
2832
2833 #if defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
2834
2835
2836 #if defined(CONFIG_SPX15)|| (defined CONFIG_SC9630)
2837         #if defined (CONFIG_ARCH_SCX20L)
2838                         if (slot_NO == SDHOST_SLOT_6)
2839                         {
2840                                 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
2841
2842                                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2843                                 {
2844                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
2845                                         clk = SDIO_BASE_CLK_384M;
2846                                 }
2847                                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2848                                 {
2849                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
2850                                         clk = SDIO_BASE_CLK_312M;
2851                                 }
2852                                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2853                                 {
2854                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
2855                                         clk = SDIO_BASE_CLK_256M;
2856                                 }
2857                                 else
2858                                 {
2859                                         clk = SDIO_BASE_CLK_26M;
2860                                 }
2861 #if 0
2862                                 if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2863                                 {
2864                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
2865                                         clk = SDIO_BASE_CLK_256M;
2866                                 }
2867                                 else if (sdio_base_clk >= SDIO_BASE_CLK_192M)
2868                                 {
2869                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
2870                                         clk = SDIO_BASE_CLK_192M;
2871                                 }
2872                                 else if (sdio_base_clk >= SDIO_BASE_CLK_153M)
2873                                 {
2874                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
2875                                         clk = SDIO_BASE_CLK_256M;
2876                                 }
2877                                 else
2878                                 {
2879                                         clk = SDIO_BASE_CLK_26M;
2880                                 }
2881 #endif
2882                         }
2883                         else
2884                         {
2885                                 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
2886
2887                                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2888                                 {
2889                                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
2890                                         clk = SDIO_BASE_CLK_384M;
2891                                 }
2892                                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2893                                 {
2894                                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
2895                                         clk = SDIO_BASE_CLK_312M;
2896                                 }
2897                                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2898                                 {
2899                                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
2900                                         clk = SDIO_BASE_CLK_256M;
2901                                 }
2902                                 else
2903                                 {
2904                                         clk = SDIO_BASE_CLK_26M;
2905                                 }
2906 #if 0
2907                                 if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2908                                 {
2909                                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
2910                                         clk = SDIO_BASE_CLK_256M;
2911                                 }
2912                                 else if (sdio_base_clk >= SDIO_BASE_CLK_192M)
2913                                 {
2914                                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
2915                                         clk = SDIO_BASE_CLK_192M;
2916                                 }
2917                                 else if (sdio_base_clk >= SDIO_BASE_CLK_153M)
2918                                 {
2919                                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
2920                                         clk = SDIO_BASE_CLK_153M;
2921                                 }
2922                                 else
2923                                 {
2924                                         clk = SDIO_BASE_CLK_26M;
2925                                 }
2926 #endif
2927                         }
2928         #elif defined(CONFIG_SPX20)
2929                 if (slot_NO == SDHOST_SLOT_6)
2930                 {
2931                         REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
2932
2933                         if (sdio_base_clk == SDIO_BASE_CLK_192M)
2934                         {
2935                                 REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
2936                                 clk = SDIO_BASE_CLK_192M;
2937                         }
2938                         else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2939                         {
2940                                 REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
2941                                 clk = SDIO_BASE_CLK_312M;
2942                         }
2943                         else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2944                         {
2945                                 REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
2946                                 clk = SDIO_BASE_CLK_256M;
2947                         }
2948                         else
2949                         {
2950                                 clk = SDIO_BASE_CLK_26M;
2951                         }
2952                 }
2953                 else
2954                 {
2955                         REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
2956
2957                         if (sdio_base_clk == SDIO_BASE_CLK_192M)
2958                         {
2959                                 REG32(REG_AP_CLK_EMMC_CFG) |=  3;
2960                                 clk = SDIO_BASE_CLK_192M;
2961                         }
2962                         else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2963                         {
2964                                 REG32(REG_AP_CLK_EMMC_CFG) |=  2;
2965                                 clk = SDIO_BASE_CLK_312M;
2966                         }
2967                         else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2968                         {
2969                                 REG32(REG_AP_CLK_EMMC_CFG) |=  1;
2970                                 clk = SDIO_BASE_CLK_256M;
2971                         }
2972                         else
2973                         {
2974                                 clk = SDIO_BASE_CLK_26M;
2975                         }
2976                 }
2977         #else
2978                 if (slot_NO == SDHOST_SLOT_6)
2979                         {
2980                                 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
2981
2982                                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2983                                 {
2984                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
2985                                         clk = SDIO_BASE_CLK_384M;
2986                                 }
2987                                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2988                                 {
2989                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
2990                                         clk = SDIO_BASE_CLK_312M;
2991                                 }
2992                                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2993                                 {
2994                                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
2995                                         clk = SDIO_BASE_CLK_256M;
2996                                 }
2997                                 else
2998                                 {
2999                                         clk = SDIO_BASE_CLK_26M;
3000                                 }
3001                         }
3002                         else
3003                         {
3004                                 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3005
3006                                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3007                                 {
3008                                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
3009                                         clk = SDIO_BASE_CLK_384M;
3010                                 }
3011                                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3012                                 {
3013                                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
3014                                         clk = SDIO_BASE_CLK_312M;
3015                                 }
3016                                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3017                                 {
3018                                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
3019                                         clk = SDIO_BASE_CLK_256M;
3020                                 }
3021                                 else
3022                                 {
3023                                         clk = SDIO_BASE_CLK_26M;
3024                                 }
3025                         }
3026         #endif
3027 #else   /* TIZEN */
3028         if (slot_NO == SDHOST_SLOT_6)
3029         {
3030                 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3031
3032                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3033                 {
3034                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
3035                         clk = SDIO_BASE_CLK_384M;
3036                 }
3037                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3038                 {
3039                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
3040                         clk = SDIO_BASE_CLK_312M;
3041                 }
3042                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3043                 {
3044                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
3045                         clk = SDIO_BASE_CLK_256M;
3046                 }
3047                 else
3048                 {
3049                         clk = SDIO_BASE_CLK_26M;
3050                 }
3051         }
3052         else
3053         {
3054                 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3055
3056                 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3057                 {
3058                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
3059                         clk = SDIO_BASE_CLK_384M;
3060                 }
3061                 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3062                 {
3063                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
3064                         clk = SDIO_BASE_CLK_312M;
3065                 }
3066                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3067                 {
3068                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
3069                         clk = SDIO_BASE_CLK_256M;
3070                 }
3071                 else
3072                 {
3073                         clk = SDIO_BASE_CLK_26M;
3074                 }
3075         }
3076
3077 #if 0
3078         if (slot_NO == SDHOST_SLOT_6)
3079         {
3080                 if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3081                 {
3082                         REG32(REG_AP_CLK_SDIO0_CFG) |=  3;
3083                         clk = SDIO_BASE_CLK_312M;
3084                 }
3085                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3086                 {
3087                         REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3088                         REG32(REG_AP_CLK_SDIO0_CFG) |=  2;
3089                         clk = SDIO_BASE_CLK_256M;
3090                 }
3091                 if (sdio_base_clk >= SDIO_BASE_CLK_192M)
3092                 {
3093                         REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3094                         REG32(REG_AP_CLK_SDIO0_CFG) |=  1;
3095                         clk = SDIO_BASE_CLK_192M;
3096                 }
3097                 else
3098                 {
3099                         REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3100                         clk = SDIO_BASE_CLK_26M;
3101                 }
3102         }
3103         else
3104         {
3105                 if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3106                 {
3107                         REG32(REG_AP_CLK_EMMC_CFG) |=  3;
3108                         clk = SDIO_BASE_CLK_312M;
3109                 }
3110                 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3111                 {
3112                         REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3113                         REG32(REG_AP_CLK_EMMC_CFG) |=  2;
3114                         clk = SDIO_BASE_CLK_256M;
3115                 }
3116                 if (sdio_base_clk >= SDIO_BASE_CLK_192M)
3117                 {
3118                         REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3119                         REG32(REG_AP_CLK_EMMC_CFG) |=  1;
3120                         clk = SDIO_BASE_CLK_192M;
3121                 }
3122                 else
3123                 {
3124                         REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3125                         clk = SDIO_BASE_CLK_26M;
3126                 }
3127         }
3128 #endif
3129 #endif
3130 #elif defined(CONFIG_TIGER)
3131     REG32 (GR_CLK_GEN5) &= ~ (BIT_23|BIT_24);
3132     //Select the clk source of SDIO
3133     if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3134     {
3135         clk = SDIO_BASE_CLK_384M;
3136     }
3137     else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3138     {
3139         clk = SDIO_BASE_CLK_256M;
3140         REG32 (GR_CLK_GEN5) |= (1<<23);
3141     }
3142     else if (sdio_base_clk >= SDIO_BASE_CLK_153M)
3143     {
3144         clk = SDIO_BASE_CLK_153M;
3145         REG32 (GR_CLK_GEN5) |= (2<<23);
3146     }
3147     else
3148     {
3149         clk = SDIO_BASE_CLK_26M;
3150         REG32 (GR_CLK_GEN5) |= (3<<23);
3151     }
3152 #elif defined(CONFIG_SC7710G2)
3153     if(SDHOST_SLOT_6 == slot_NO){
3154         REG32 (GR_CLK_GEN7) &= ~ (BIT_21|BIT_22);
3155         //Select the clk source of SDIO
3156         if (sdio_base_clk >= SDIO_BASE_CLK_96M) {
3157                 clk = SDIO_BASE_CLK_96M;
3158         } else if (sdio_base_clk >= SDIO_BASE_CLK_64M) {
3159                 clk = SDIO_BASE_CLK_64M;
3160                 REG32 (GR_CLK_GEN7) |= (1<<21);
3161         } else if (sdio_base_clk >= SDIO_BASE_CLK_48M) {
3162                 clk = SDIO_BASE_CLK_48M;
3163                 REG32 (GR_CLK_GEN7) |= (2<<21);
3164         } else {
3165                 clk = SDIO_BASE_CLK_26M;
3166                 REG32 (GR_CLK_GEN7) |= (3<<21);
3167         }
3168     } else {
3169         REG32 (GR_CLK_GEN7) &= ~ (BIT_23|BIT_24);
3170         //Select the clk source of SDIO
3171         if (sdio_base_clk >= SDIO_BASE_CLK_384M){
3172                 clk = SDIO_BASE_CLK_384M;
3173                 REG32 (GR_CLK_GEN7) |= (1<<23);
3174         } else if (sdio_base_clk >= SDIO_BASE_CLK_256M){
3175                 clk = SDIO_BASE_CLK_256M;
3176                 REG32 (GR_CLK_GEN7) |= (2<<23);
3177         } else if (sdio_base_clk >= SDIO_BASE_CLK_153M){
3178                 clk = SDIO_BASE_CLK_153M;
3179                 REG32 (GR_CLK_GEN7) |= (3<<23);
3180         }else
3181                 clk = SDIO_BASE_CLK_26M;
3182     }
3183 #elif defined(PLATFORM_SC8800G)
3184     //Select the clk source of SDIO1
3185     if(SDHOST_SLOT_1 == slot_NO){
3186         *(volatile uint32 *)GR_CLK_GEN5 &= ~(BIT_19|BIT_20);
3187         if(sdio_base_clk >= SDIO_BASE_CLK_96M)
3188                 clk = SDIO_BASE_CLK_96M;
3189         else if(sdio_base_clk >= SDIO_BASE_CLK_64M){
3190                 clk = SDIO_BASE_CLK_64M;
3191                 *(volatile uint32 *)GR_CLK_GEN5 |= (1<<19);
3192         } else if(sdio_base_clk >= SDIO_BASE_CLK_48M) {
3193                 clk = SDIO_BASE_CLK_48M;
3194                 *(volatile uint32 *)GR_CLK_GEN5 |= (2<<19);
3195         } else {
3196                 clk = SDIO_BASE_CLK_26M;
3197                 *(volatile uint32 *)GR_CLK_GEN5 |= (3<<19);
3198         }
3199     } else if(SDHOST_SLOT_0 == slot_NO){
3200         *(volatile uint32 *)GR_CLK_GEN5 &= ~(BIT_17|BIT_18);
3201         if(sdio_base_clk >= SDIO_BASE_CLK_96M)
3202                 clk = SDIO_BASE_CLK_96M;
3203         else if(sdio_base_clk >= SDIO_BASE_CLK_64M){
3204                 clk = SDIO_BASE_CLK_64M;
3205                 *(volatile uint32 *)GR_CLK_GEN5 |= (1<<17);
3206         } else if(sdio_base_clk >= SDIO_BASE_CLK_48M) {
3207                 clk = SDIO_BASE_CLK_48M;
3208                 *(volatile uint32 *)GR_CLK_GEN5 |= (2<<17);
3209         } else {
3210                 clk = SDIO_BASE_CLK_26M;
3211                 *(volatile uint32 *)GR_CLK_GEN5 |= (3<<17);
3212         }
3213     }
3214 #endif
3215     return clk;
3216 }
3217
3218 #endif
3219
3220 /*****************************************************************************/
3221 //  Description: select witch slot to work
3222 //  Author: Jason.wu
3223 //  Param
3224 //      slot_NO: slot number
3225 //  Return:
3226 //      NONE
3227 //  Note: This function must be applied according different platform
3228 /*****************************************************************************/
3229 PUBLIC void SDHOST_Slot_select (SDHOST_SLOT_NO slot_NO)
3230 {
3231         SCI_ASSERT (slot_NO < SDHOST_SLOT_MAX_NUM);/*assert verified*/
3232 #if !(defined(CONFIG_SC8830) || defined(CONFIG_SC9630) )
3233         * (volatile uint32 *) AHB_SDIO_CTL = (AHB_SDIO_CTRL_SLOT0); //select master0
3234 #endif
3235 }
3236
3237 //===end===
3238