1 /******************************************************************************
2 ** File Name: sdhost_drv.c
5 ** Copyright: 2004 Spreadtrum, Incoporated. All Rights Reserved.
6 ** Description: This file describe operation of SD host.
7 ******************************************************************************
9 ******************************************************************************
11 ** ------------------------------------------------------------------------- *
12 ** DATE NAME DESCRIPTION
13 ** 09/17/2007 Jason.wu Create.
14 ******************************************************************************/
16 /**---------------------------------------------------------------------------*
18 **---------------------------------------------------------------------------*/
19 #include "asm/arch/sci_types.h"
20 #include "asm/arch/os_api.h"
21 #include "asm/arch/chip_plf_export.h"
22 #include "sdhost_drv.h"
24 #if defined(CONFIG_SC8825) || defined (CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
25 #include <asm/arch/sdio_reg_v3.h>
26 //#include <asm/arch/int_reg_v3.h>
27 #include <asm/arch/sys_timer_reg_v0.h>
30 #if defined(CONFIG_SC8825) || defined (CONFIG_SC7710G2)
31 #include <asm/arch/sc8810_module_config.h>
32 #elif defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
33 #include <asm/arch/sprd_module_config.h>
34 #include <asm/arch/regs_ahb.h>
35 #include <asm/arch/isr_drvapi.h>
36 #include <asm/arch/pinmap.h>
39 #include "asm/arch/ldo.h"
42 #include <asm/arch/pin_reg_v3.h>
45 #if defined (CONFIG_SC8810) || defined (CONFIG_SC8825) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
46 #define PLATFORM_SC8800G
48 #if defined CONFIG_SC8825 && defined CONFIG_UBOOT_DEBUG
49 #define SDHOST_PRINT(x) printf x
51 #define SDHOST_PRINT(x) SCI_TRACE_LOW x
53 /*****************************************************************************/
54 // Description: Handle of sdhost
57 // host_cfg: start register of host controller
58 // open_flag: Indicate whether this port has be used by other application
59 // baseClock: the basic frequence that host work on
60 // sdClock: the frequence that card work on
61 // capbility: the function that canbe supported by host
62 // err_filter: the error code that application want to watched
63 // sigCallBack: the point of application that used to anounce that some signal happened
65 /*****************************************************************************/
66 typedef struct SDHOST_PORT_T_TAG
68 volatile SDIO_REG_CFG *host_cfg;
73 SDHOST_CAPBILIT_T capbility;
75 SDIO_CALLBACK sigCallBack;
84 SDHOST_SLOT_NO slotNum;
85 SDHOST_HANDLE pSdhost_handler;
89 //INPUT_BUFFER_INIT (ISR_Buffer_T, SDHOST_SLOT_MAX_NUM)
91 LOCAL SDHOST_PORT_T sdio_port_ctl[SDHOST_SLOT_MAX_NUM];
93 LOCAL DEVICE_HANDLE s_dev_sdio = SCI_NULL;
96 PUBLIC ISR_EXE_T _SDHOST_IrqHandle (uint32 isrnum);
97 LOCAL void SdhostHisrFunc (uint32 cnt, void *pData);
99 PUBLIC void SDHOST_Delayus(uint32 usec)
102 /* current is 800MHZ, when usec =1, the mean is delay 1 us */
103 for (i = 0; i < (usec << 1); i++);
105 /*****************************************************************************/
106 // Description: To confirm whether the handle is valid
109 // sdhost_handler: the handle of host driver
111 // TRUE the handle is valid
112 // FALSE:the handle is not valid
114 /*****************************************************************************/
115 LOCAL BOOLEAN _RegisterVerifyHOST (SDHOST_HANDLE sdhost_handler)
119 for (index = 0; index < SDHOST_SLOT_MAX_NUM; index++)
121 if ( (sdhost_handler == &sdio_port_ctl[index]) && (TRUE == sdio_port_ctl[index].open_flag))
130 PUBLIC uint32 SDHOST_GetPinState (SDHOST_HANDLE sdhost_handler)
132 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
134 return sdhost_handler->host_cfg->PRESENT_STAT;
137 //---Power Control Register---
138 /*****************************************************************************/
139 // Description: power on/off led
142 // sdhost_handler: the handle of host driver
147 /*****************************************************************************/
148 PUBLIC void SDHOST_Led (SDHOST_HANDLE sdhost_handler,SDHOST_LED_ONOFF_E onoff)
150 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
157 sdhost_handler->host_cfg->HOST_CTL0 |= 0x1;
163 sdhost_handler->host_cfg->HOST_CTL0 &= (~0x1);
169 SCI_ASSERT (0);/*assert verified*/
177 /*****************************************************************************/
178 // Description: set data bus width
181 // sdhost_handler: the handle of host driver
182 // width: data bus width,only 1bit ,4bit and 8bit canbe used
186 /*****************************************************************************/
187 PUBLIC void SDHOST_Cfg_BusWidth (SDHOST_HANDLE sdhost_handler,SDHOST_BIT_WIDTH_E width)
189 uint32 tmpReg = sdhost_handler->host_cfg->HOST_CTL0;
191 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
193 tmpReg &= (~ (0x1<<5));
194 tmpReg &= (~ (0x1<<1));
198 case SDIO_1BIT_WIDTH:
204 case SDIO_4BIT_WIDTH:
210 case SDIO_8BIT_WIDTH:
218 SCI_ASSERT (0);/*assert verified*/
223 sdhost_handler->host_cfg->HOST_CTL0 = tmpReg;
226 /*****************************************************************************/
227 // Description: set bus speed mode
230 // sdhost_handler: the handle of host driver
231 // speed: speed mode ,only low speed mode and high speed mode canbe used
235 /*****************************************************************************/
236 #if defined (CONFIG_SC8825) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
237 PUBLIC void SDHOST_Cfg_SpeedMode (SDHOST_HANDLE sdhost_handler,SDHOST_SPEED_E speed)
239 uint32 tmpReg = sdhost_handler->host_cfg->HOST_CTL2;
240 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
250 REG32(EMMC_CLK_WR_DL) = 0x33;
251 REG32(EMMC_CLK_RD_POS_DL) = 0x08;
252 REG32(EMMC_CLK_RD_NEG_DL) = 0x08;
264 sdhost_handler->host_cfg->HOST_CTL2 = tmpReg;
267 PUBLIC void SDHOST_Cfg_SpeedMode (SDHOST_HANDLE sdhost_handler,SDHOST_SPEED_E speed)
269 uint32 tmpReg = sdhost_handler->host_cfg->HOST_CTL0;
271 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
273 tmpReg &= (~ (0x1 <<2));
291 SCI_ASSERT (0);/*assert verified*/
296 sdhost_handler->host_cfg->HOST_CTL0 = tmpReg;
310 #define LDO_LDO_SDIO 29 */
312 /*****************************************************************************/
313 // Description: Set operation voltage of card(mmc \sd\sdio card.etc.)
316 // sdhost_handler: the handle of host driver
321 /*****************************************************************************/
322 PUBLIC void SDHOST_Cfg_Voltage (SDHOST_HANDLE sdhost_handler,SDHOST_VOL_RANGE_E voltage)
324 #if defined (CONFIG_TIGER) || defined (CONFIG_SC7710G2)
325 /*<CR:MS00234475 modify for SPI smartphone 30/03/2011 by shengyanxin bagin*/
326 #if defined (MODEM_CONTROL_SUPPORT_SPI)
329 #ifdef PLATFORM_SC8800G
330 LDO_VOLT_LEVEL_E ldo_volt_level;
332 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
338 ldo_volt_level = LDO_VOLT_LEVEL3;
344 ldo_volt_level = LDO_VOLT_LEVEL2; ///it is 2.5V in sc8800g spec.
350 ldo_volt_level = LDO_VOLT_LEVEL0;
356 ldo_volt_level = LDO_VOLT_LEVEL1;
362 SCI_ASSERT (0);/*assert verified*/
367 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
368 LDO_SetVoltLevel (LDO_LDO_SDIO3, LDO_VOLT_LEVEL3);
369 LDO_SetVoltLevel (LDO_LDO_VDD30, LDO_VOLT_LEVEL1);
371 if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler){
372 LDO_SetVoltLevel (LDO_LDO_SDIO0, LDO_VOLT_LEVEL3);
376 LDO_SetVoltLevel (LDO_LDO_SDIO1, LDO_VOLT_LEVEL3);
377 LDO_SetVoltLevel (LDO_LDO_SIM2, LDO_VOLT_LEVEL1);
382 //gpio_direction_output(139, 1);
383 //gpio_set_value(139, 1);
384 //control gpio 139 emmc reset pin
386 *(volatile u32 *)0x8B000008 = 1<<5;
387 *(volatile u32 *)0x8A000384 = 1<<15;
388 *(volatile u32 *)0x8A000388 = 1<<15;
389 *(volatile u32 *)0x8A000380 = 1<<15;
391 tempreg = *(volatile u32 *)0x8B000008;
392 *(volatile u32 *)0x8B000008 = tempreg | (1<<5);
394 //*(volatile u32 *)0x8C0003D0 = 0;
396 #ifdef CONFIG_SC8810_OPENPHONE
397 tempreg = *(volatile unsigned int *)0x8A000384;
398 *(volatile unsigned int *)0x8A000384 = tempreg | (1<<11);
399 tempreg = *(volatile unsigned int *)0x8A000388;
400 *(volatile unsigned int *)0x8A000388 = tempreg | (1<<11);
401 tempreg = *(volatile unsigned int *)0x8A000380;
402 *(volatile unsigned int *)0x8A000380 = tempreg | (1<<11);
404 tempreg = *(volatile unsigned int *)0x8A000184;
405 *(volatile unsigned int *)0x8A000184 = tempreg | (1<<7);
406 tempreg = *(volatile unsigned int *)0x8A000188;
407 *(volatile unsigned int *)0x8A000188 = tempreg | (1<<7);
408 tempreg = *(volatile unsigned int *)0x8A000180;
409 *(volatile unsigned int *)0x8A000180 = tempreg | (1<<7);
414 uint32 tmpReg = sdhost_handler->host_cfg->HOST_CTL0;
416 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
418 tmpReg &= (~ (0x7<<9));
448 SCI_ASSERT (0);/*assert verified*/
453 sdhost_handler->host_cfg->HOST_CTL0 = tmpReg;
459 /*****************************************************************************/
460 // Description: Open or close power supply of card(mmc \sd\sdio card.etc.)
463 // sdhost_handler: the handle of host driver
468 /*****************************************************************************/
469 PUBLIC void SDHOST_SD_POWER (SDHOST_HANDLE sdhost_handler,SDHOST_PWR_ONOFF_E on_off)
471 /*<CR:MS00234475 modify for SPI smartphone 30/03/2011 by shengyanxin bagin*/
472 #if defined (MODEM_CONTROL_SUPPORT_SPI) && defined (AP_SOLUTION_INGENIC)
475 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
477 #if defined(PLATFORM_SC8800G)
479 ///added by mingwei, Andy need to check again.
480 if (POWR_ON == on_off)
482 //LDO_TurnOnLDO (LDO_LDO_SDIO);
483 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
484 LDO_TurnOnLDO(LDO_LDO_SDIO3);
485 LDO_TurnOnLDO(LDO_LDO_VDD30);
486 #elif (defined CONFIG_SC8830)
487 #if defined(CONFIG_SPX30G2)
488 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
490 LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
491 LDO_TurnOnLDO(LDO_LDO_EMMCIO);
493 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
497 .id = LDO_LDO_SDIO0, .name = "vddsdcore",
498 .id = LDO_LDO_SDIO1, .name = "vddsdio",
499 sharkl no need open vddsdio.
500 if need,turn on vddsdio
501 LDO_TurnOnLDO(LDO_LDO_SDIO1);
503 LDO_TurnOnLDO(LDO_LDO_SDIO1);
504 LDO_TurnOnLDO(LDO_LDO_SDIO0);
507 #elif (defined CONFIG_SPX20)
508 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
510 LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
511 LDO_TurnOnLDO(LDO_LDO_EMMCIO);
513 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
515 printf("%s config SDHOST_SLOT_6\r\n", __FUNCTION__);
516 LDO_TurnOnLDO(LDO_LDO_SDIO0);
517 LDO_TurnOnLDO(LDO_LDO_SDIO1);
520 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
522 LDO_TurnOnLDO(LDO_LDO_SDIO3);
524 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
526 printf("%s config SDHOST_SLOT_6\r\n", __FUNCTION__);
527 LDO_TurnOnLDO(LDO_LDO_SDIO0);
530 #elif (defined CONFIG_SC9630)
531 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
533 LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
534 LDO_TurnOnLDO(LDO_LDO_EMMCIO);
536 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
541 .id = LDO_LDO_SDIO0, .name = "vddsdcore",
542 .id = LDO_LDO_SDIO1, .name = "vddsdio",
543 sharkl no need open vddsdio.
544 if need,turn on vddsdio
545 LDO_TurnOnLDO(LDO_LDO_SDIO1);
547 #if defined(CONFIG_SP9830IEA_5M_H100)
548 LDO_TurnOnLDO(LDO_LDO_SDIO1);
549 LDO_TurnOnLDO(LDO_LDO_SDIO0);
551 LDO_TurnOnLDO(LDO_LDO_SDIO0);
555 if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler)
557 LDO_TurnOnLDO(LDO_LDO_SDIO0);
560 LDO_TurnOnLDO(LDO_LDO_SDIO1);
561 LDO_TurnOnLDO(LDO_LDO_SIM2);
567 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
568 LDO_TurnOffLDO(LDO_LDO_SDIO3);
569 LDO_TurnOffLDO(LDO_LDO_VDD30);
570 #elif defined (CONFIG_SC8830)
571 #if defined(CONFIG_SPX30G2)
572 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
574 LDO_TurnOffLDO(LDO_LDO_EMMCCORE);
575 LDO_TurnOffLDO(LDO_LDO_EMMCIO);
577 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
579 LDO_TurnOffLDO(LDO_LDO_SDIO0);
580 LDO_TurnOffLDO(LDO_LDO_SDIO1);
583 .id = LDO_LDO_SDIO0, .name = "vddsdcore",
584 .id = LDO_LDO_SDIO1, .name = "vddsdio",
585 sharkl no need open vddsdio.
586 if need,turn off vddsdio
587 LDO_TurnOffLDO(LDO_LDO_SDIO1);
591 #elif (defined CONFIG_SPX20)
592 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
594 LDO_TurnOnLDO(LDO_LDO_EMMCCORE);
595 LDO_TurnOnLDO(LDO_LDO_EMMCIO);
597 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
599 printf("%s config SDHOST_SLOT_6\r\n", __FUNCTION__);
600 LDO_TurnOnLDO(LDO_LDO_SDIO0);
601 LDO_TurnOnLDO(LDO_LDO_SDIO1);
606 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
608 LDO_TurnOffLDO(LDO_LDO_SDIO3);
610 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
612 LDO_TurnOffLDO(LDO_LDO_SDIO0);
615 #elif (defined CONFIG_SC9630)
616 if (sdhost_handler->slotNo == SDHOST_SLOT_7)
618 LDO_TurnOffLDO(LDO_LDO_EMMCCORE);
619 LDO_TurnOffLDO(LDO_LDO_EMMCIO);
621 else if (sdhost_handler->slotNo == SDHOST_SLOT_6)
623 LDO_TurnOffLDO(LDO_LDO_SDIO0);
626 .id = LDO_LDO_SDIO0, .name = "vddsdcore",
627 .id = LDO_LDO_SDIO1, .name = "vddsdio",
628 sharkl no need open vddsdio.
629 if need,turn off vddsdio
630 LDO_TurnOffLDO(LDO_LDO_SDIO1);
634 if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler){
635 LDO_TurnOffLDO (LDO_LDO_SDIO0);
638 LDO_TurnOffLDO (LDO_LDO_SDIO1);
639 LDO_TurnOffLDO (LDO_LDO_SIM2);
644 #else // no defined(PLATFORM_SC8800G)
650 sdhost_handler->host_cfg->HOST_CTL0 |= (0x1<<8);
656 sdhost_handler->host_cfg->HOST_CTL0 &= (~ (0x1<<8));
662 SCI_ASSERT (0);/*assert verified*/
670 //---Block Gap Control Register---
671 /*****************************************************************************/
672 // Description: Set the position of break point
675 // sdhost_handler: the handle of host driver
679 /*****************************************************************************/
680 PUBLIC void SDHOST_BlkGapIntPosSet (SDHOST_HANDLE sdhost_handler)
682 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
686 /*****************************************************************************/
687 // Description: Enable pause function of host. the card must support this function,then this function can be worked
690 // sdhost_handler: the handle of host driver
694 /*****************************************************************************/
695 PUBLIC void SDHOST_EnableReadWaitCtl (SDHOST_HANDLE sdhost_handler)
697 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
699 sdhost_handler->host_cfg->HOST_CTL0 |= BIT_18;
702 /*****************************************************************************/
703 // Description: Set break point during the transmition
706 // sdhost_handler: the handle of host driver
710 /*****************************************************************************/
711 PUBLIC void SDHOST_StopAtBlkGap (SDHOST_HANDLE sdhost_handler)
713 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
715 sdhost_handler->host_cfg->HOST_CTL0 |= (BIT_16);
717 PUBLIC void SDHOST_ClearBlkGap (SDHOST_HANDLE sdhost_handler)
719 sdhost_handler->host_cfg->HOST_CTL0 &= (~ (0x01<<16));
721 PUBLIC void SDHOST_BlkGapIntEn (SDHOST_HANDLE sdhost_handler)
723 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler)); /*assert verified*/
725 sdhost_handler->host_cfg->HOST_CTL0 |= (BIT_19);
727 PUBLIC uint32 SDHOST_GetTransStat (SDHOST_HANDLE sdhost_handler)
729 return (sdhost_handler->host_cfg->PRESENT_STAT & (BIT_8|BIT_9));
732 /*****************************************************************************/
733 // Description: When transmission is paused ,this function can resume the transmission
736 // sdhost_handler: the handle of host driver
740 /*****************************************************************************/
741 PUBLIC void SDHOST_Continue (SDHOST_HANDLE sdhost_handler)
743 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
745 sdhost_handler->host_cfg->HOST_CTL0 &= (~ (0x03<<16));
746 sdhost_handler->host_cfg->HOST_CTL0 |= BIT_17;
752 //----Clock Control Register---
753 /*****************************************************************************/
754 // Description: Open or close internal clk.when this clk is disable ,the host will enter in sleep mode
757 // sdhost_handler: the handle of host driver
762 /*****************************************************************************/
763 PUBLIC void SDHOST_internalClk_OnOff (SDHOST_HANDLE sdhost_handler,SDHOST_CLK_ONOFF_E onoff)
765 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
772 //Enable internal clock
773 sdhost_handler->host_cfg->HOST_CTL1 |= BIT_0;
775 while ((0 == (sdhost_handler->host_cfg->HOST_CTL1 & BIT_1)) && timeout)
785 sdhost_handler->host_cfg->HOST_CTL1 &= (~BIT_0);
792 SCI_ASSERT (0);/*assert verified*/
798 /*****************************************************************************/
799 // Description: Open or close card clk.
802 // sdhost_handler: the handle of host driver
807 /*****************************************************************************/
808 PUBLIC void SDHOST_SD_clk_OnOff (SDHOST_HANDLE sdhost_handler,SDHOST_CLK_ONOFF_E onoff)
810 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
816 //Enable internal clock
817 sdhost_handler->host_cfg->HOST_CTL1 |= BIT_2;
823 if ((sdhost_handler->host_cfg->HOST_CTL1 & BIT_2) != 0) {
824 sdhost_handler->host_cfg->HOST_CTL1 &= (~BIT_2);
832 SCI_ASSERT (0);/*assert verified*/
838 /*****************************************************************************/
839 // Description: Set the frequence of Card clock
842 // sdhost_handler: the handle of host driver
843 // sdio_clk: the frequence of card working clock
845 // uint32 value : the frequency that be used acctually
847 /*****************************************************************************/
848 PUBLIC uint32 SDHOST_SD_Clk_Freq_Set (SDHOST_HANDLE sdhost_handler,uint32 sdio_clk)
850 volatile uint32 tmpReg;
853 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
854 SCI_ASSERT (0 != sdio_clk);/*assert verified*/
856 sdio_clk = (sdio_clk > SDIO_SD_MAX_CLK) ? (SDIO_SD_MAX_CLK) : (sdio_clk);
858 //SDCLK Frequency Select ,Configure SDCLK select
859 clkDiv = sdhost_handler->baseClock/sdio_clk;
860 #if defined (CONFIG_SC8825) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
863 if (0 != sdhost_handler->baseClock%sdio_clk)
868 SDHOST_PRINT ( (" clkDiv: %d, sdio_clk:%d, baseClock:%d\n",clkDiv, sdio_clk, sdhost_handler->baseClock));
870 tmpReg = sdhost_handler->host_cfg->HOST_CTL1;
871 #if defined (CONFIG_SC8825) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
873 tmpReg &= (~ (0x3ff<<6));
874 tmpReg |= ((clkDiv>>8)&0x3)<<6;
875 tmpReg |= (clkDiv&0xff)<<8;
876 sdhost_handler->sdClock = sdhost_handler->baseClock/(2*(clkDiv+1));
878 tmpReg &= (~ (0xff<<8));
881 SDHOST_PRINT ( (" clkDiv: %d is too big!!!!!",clkDiv));
882 SCI_ASSERT (0);/*assert to do*/
884 else if (128 < clkDiv)
887 tmpReg |= (0x80 << 8);
889 else if (64 < clkDiv)
894 else if (32 < clkDiv)
899 else if (16 < clkDiv)
929 else //if (0 == clkDiv)
931 SCI_ASSERT (0);/*assert to do*/
933 sdhost_handler->sdClock = sdhost_handler->baseClock/clkDiv;
936 sdhost_handler->host_cfg->HOST_CTL1 = tmpReg;
937 SDHOST_PRINT ( ("sd clk: %d KHz.",sdhost_handler->sdClock/1000));
939 return sdhost_handler->sdClock;
942 //---Timeout Control Register--
943 /*****************************************************************************/
944 // Description: Set timeout value ,this value is used during the data transmission
947 // sdhost_handler: the handle of host driver
948 // clk_cnt: the value is (2 ^ (clkcnt+13))*T_BSCLK,T_BSCLK is working frequence of host
952 /*****************************************************************************/
953 PUBLIC void SDHOST_SetDataTimeOutValue (SDHOST_HANDLE sdhost_handler,uint8 clk_cnt) // (2 ^ (clkcnt+13))*T_BSCLK
955 volatile uint32 tmpReg,tmpIntReg;
957 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
959 tmpIntReg = sdhost_handler->host_cfg->INT_STA_EN;
960 // cfg the data timeout clk----------
961 sdhost_handler->host_cfg->INT_STA_EN &= ~BIT_20;
963 tmpReg = sdhost_handler->host_cfg->HOST_CTL1;
964 tmpReg &= ~ (0xF << 16);
965 tmpReg |= (clk_cnt << 16);
966 sdhost_handler->host_cfg->HOST_CTL1 = tmpReg;
968 sdhost_handler->host_cfg->INT_STA_EN = tmpIntReg;
971 //---Software Reset Register---
972 /*****************************************************************************/
973 // Description: Reset data line of host
976 // sdhost_handler: the handle of host driver
980 /*****************************************************************************/
981 LOCAL void _Reset_DAT (SDHOST_HANDLE sdhost_handler)
983 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
985 sdhost_handler->host_cfg->HOST_CTL1 |= BIT_26;
987 while (0!= (sdhost_handler->host_cfg->HOST_CTL1 & BIT_26)) {}
989 /*****************************************************************************/
990 // Description: Reset command line of host
993 // sdhost_handler: the handle of host driver
997 /*****************************************************************************/
998 LOCAL void _Reset_CMD (SDHOST_HANDLE sdhost_handler)
1000 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1002 sdhost_handler->host_cfg->HOST_CTL1 |= BIT_25;
1004 while (0!= (sdhost_handler->host_cfg->HOST_CTL1 & BIT_25)) {}
1007 /*****************************************************************************/
1008 // Description: Reset command line and data line of host
1011 // sdhost_handler: the handle of host driver
1015 /*****************************************************************************/
1016 LOCAL void _Reset_DAT_CMD (SDHOST_HANDLE sdhost_handler)
1018 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1020 sdhost_handler->host_cfg->HOST_CTL1 |= (BIT_25|BIT_26);
1022 while (0!= (sdhost_handler->host_cfg->HOST_CTL1 & (BIT_25|BIT_26))) {}
1027 /*****************************************************************************/
1028 // Description: Reset all the module of host
1031 // sdhost_handler: the handle of host driver
1035 /*****************************************************************************/
1036 LOCAL void _Reset_ALL (SDHOST_HANDLE sdhost_handler)
1038 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1040 sdhost_handler->host_cfg->HOST_CTL1 |= BIT_24;
1042 while (0 != (sdhost_handler->host_cfg->HOST_CTL1 & BIT_24)) {}
1046 /*****************************************************************************/
1047 // Description: Reset module of host
1048 // Author: Wenjun.Shi
1050 // sdhost_handler: the handle of host driver
1054 /*****************************************************************************/
1055 LOCAL void SDHOST_Reset_Controller(SDHOST_SLOT_NO slot_NO)
1057 #if defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
1058 if (slot_NO == SDHOST_SLOT_6)
1060 REG32 (AHB_CTL0) |= BIT_8;
1061 REG32 (AHB_SOFT_RST) |= BIT_11;
1062 SDHOST_Delayus(200);
1063 REG32 (AHB_SOFT_RST) &=~BIT_11;
1065 else if (slot_NO == SDHOST_SLOT_7)
1067 REG32 (AHB_CTL0) |= BIT_11;
1068 REG32 (AHB_SOFT_RST) |= BIT_14;
1069 SDHOST_Delayus(200);
1070 REG32 (AHB_SOFT_RST) &=~BIT_14;
1072 #elif defined (CONFIG_SC8825)
1073 if (slot_NO == SDHOST_SLOT_6)
1075 REG32 (AHB_CTL0) |= BIT_4;
1076 REG32 (AHB_SOFT_RST) |= BIT_12;
1077 REG32 (AHB_SOFT_RST) &= ~BIT_12;
1079 else if (slot_NO == SDHOST_SLOT_7)
1081 REG32 (AHB_CTL0) |= BIT_23;
1082 REG32 (AHB_SOFT_RST) |= BIT_21;
1083 REG32 (AHB_SOFT_RST) &= ~BIT_21;
1085 #elif defined(CONFIG_SC7710G2)
1086 REG32 (AHB_CTL6) |= BIT_2;
1087 REG32 (AHB_SOFT2_RST) |= BIT_0;
1088 REG32 (AHB_SOFT2_RST) &= ~BIT_0;
1090 #define AHB_CTL0_SDIO0_EN (BIT_4)
1091 #define AHB_CTL0_SDIO1_EN (BIT_19)
1093 #define AHB_CTL0_SDIO0_RST (BIT_12)
1094 #define AHB_CTL0_SDIO1_RST (BIT_16)
1096 if(slot_NO == SDHOST_SLOT_0)
1098 REG32 (AHB_CTL0) |= AHB_CTL0_SDIO0_EN;
1099 REG32 (AHB_SOFT_RST) |= AHB_CTL0_SDIO0_RST;
1100 REG32 (AHB_SOFT_RST) &= ~AHB_CTL0_SDIO0_RST;
1101 }else if(slot_NO == SDHOST_SLOT_1)
1103 REG32 (AHB_CTL0) |= AHB_CTL0_SDIO1_EN;
1104 REG32 (AHB_SOFT_RST) |= AHB_CTL0_SDIO1_RST;
1105 REG32 (AHB_SOFT_RST) &= ~AHB_CTL0_SDIO1_RST;
1113 LOCAL void _Reset_MODULE (SDHOST_HANDLE sdhost_handler)
1115 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1117 if(&sdio_port_ctl[SDHOST_SLOT_0] == sdhost_handler){
1118 SDHOST_Reset_Controller(SDHOST_SLOT_0);
1119 } else if(&sdio_port_ctl[SDHOST_SLOT_1] == sdhost_handler){
1120 SDHOST_Reset_Controller(SDHOST_SLOT_1);
1122 else if(&sdio_port_ctl[SDHOST_SLOT_6] == sdhost_handler){
1123 SDHOST_Reset_Controller(SDHOST_SLOT_6);
1125 else if(&sdio_port_ctl[SDHOST_SLOT_7] == sdhost_handler){
1126 SDHOST_Reset_Controller(SDHOST_SLOT_7);
1131 /*****************************************************************************/
1132 // Description: Reset the specify module of host
1135 // sdhost_handler: the handle of host driver
1136 // rst_type: indicate which module will be reset(command lin\data line\all the module)
1140 /*****************************************************************************/
1141 PUBLIC void SDHOST_RST (SDHOST_HANDLE sdhost_handler,SDHOST_RST_TYPE_E rst_type)
1143 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1149 _Reset_CMD (sdhost_handler);
1155 _Reset_DAT (sdhost_handler);
1159 case RST_CMD_DAT_LINE:
1161 _Reset_DAT_CMD (sdhost_handler);
1167 SDHOST_SD_clk_OnOff(sdhost_handler, CLK_OFF);
1168 _Reset_ALL (sdhost_handler);
1174 SDHOST_SD_clk_OnOff(sdhost_handler, CLK_OFF);
1175 _Reset_MODULE (sdhost_handler);
1180 SCI_ASSERT (0);/*assert verified*/
1186 /*****************************************************************************/
1187 // Description: Set block size \count of block\and Dma Buffer size
1190 // sdhost_handler: the handle of host driver
1191 // block_size: size of block( 0 <= block size <=0x0800)
1192 // block_cnt: the count of block(0 <= block_cnt <= 0xFFFF)
1193 // DMAsize:buffer size of DMA(4K,8K,16K,32K,64K,128K,256K,512K)
1197 /*****************************************************************************/
1198 PUBLIC void SDHOST_SetDataParam (SDHOST_HANDLE sdhost_handler,uint32 block_size,uint32 block_cnt,SDHOST_DMA_BUF_SIZE_E DMAsize)
1200 volatile uint32 tmpReg;
1202 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1203 SCI_ASSERT (0x1000 >= block_size);/*assert verified*/
1204 SCI_ASSERT (0xFFFF >= block_cnt);/*assert verified*/
1206 tmpReg = sdhost_handler->host_cfg->BLK_SIZE_COUNT;
1209 tmpReg &= (~BIT_15);
1210 tmpReg &= (~ (0xFFF));
1211 if (0x1000 == block_size)
1217 tmpReg |= block_size;
1221 tmpReg &= (~0xFFFF0000);
1222 tmpReg |= (block_cnt << 16);
1225 tmpReg &= (~ (0x07<<12));
1237 tmpReg |= (0x01<<12);
1243 tmpReg |= (0x02<<12);
1249 tmpReg |= (0x03<<12);
1255 tmpReg |= (0x04<<12);
1261 tmpReg |= (0x05<<12);
1267 tmpReg |= (0x06<<12);
1273 tmpReg |= (0x07<<12);
1279 SCI_ASSERT (0);/*assert verified*/
1284 sdhost_handler->host_cfg->BLK_SIZE_COUNT = tmpReg;
1287 PUBLIC void SDHOST_GetDataParam (SDHOST_HANDLE sdhost_handler,uint32 *block_size,uint32 *block_cnt, uint32 *dmaAddr)
1291 sizecnt = sdhost_handler->host_cfg->BLK_SIZE_COUNT;
1292 *block_size = sizecnt&0xFFF;
1293 *block_cnt = ( (sizecnt&0xFFFF0000) >>16);
1294 *dmaAddr = sdhost_handler->host_cfg->DMA_SYS_ADD;
1297 /*****************************************************************************/
1298 // Description: Set start address of DMA buffer
1301 // sdhost_handler: the handle of host driver
1302 // dmaAddr: start address of DMA buffer
1306 /*****************************************************************************/
1307 PUBLIC void SDHOST_SetDmaAddr (SDHOST_HANDLE sdhost_handler, uint32 dmaAddr)
1309 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1311 sdhost_handler->host_cfg->DMA_SYS_ADD = dmaAddr;
1315 /*****************************************************************************/
1316 // Description: Get stop address of DMA buffer,when buffer is used ,the dma will stop at last address of buffer.this function will get this address
1319 // sdhost_handler: the handle of host driver
1321 // uint32 value: address that DMA stoped at
1323 /*****************************************************************************/
1324 PUBLIC uint32 SDHOST_GetDmaAddr (SDHOST_HANDLE sdhost_handler)
1328 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1330 dmaAddr = sdhost_handler->host_cfg->DMA_SYS_ADD;
1333 //---Argument Register---
1334 /*****************************************************************************/
1335 // Description: Set the argument of command
1338 // sdhost_handler: the handle of host driver
1343 /*****************************************************************************/
1344 PUBLIC void SDHOST_SetCmdArg (SDHOST_HANDLE sdhost_handler,uint32 argument)
1346 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1348 sdhost_handler->host_cfg->CMD_ARGUMENT = argument;
1351 //---CMD Register---
1352 /*****************************************************************************/
1353 // Description: Set the mode of command
1356 // sdhost_handler: the handle of host driver
1357 // cmdIndex: command
1358 // transmode: transfer mode
1359 // cmd_type: comand type ,it may be normal comman ,resume comman etc.
1360 // Response: the inspect response from card. if this comman is performed by card successly ,this response will be return by card
1364 /*****************************************************************************/
1365 PUBLIC void SDHOST_SetCmd (SDHOST_HANDLE sdhost_handler,uint32 cmdIndex,uint32 transmode,SDHOST_CMD_TYPE_E cmd_type,CMD_RSP_TYPE_E Response)
1367 volatile uint32 tmpReg;
1369 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1371 tmpReg = sdhost_handler->host_cfg->CMD_TRANSMODE;
1372 tmpReg &= (~ (0x7F|0x30000|0x3FF80000));
1374 if (0 != (TRANS_MODE_ATA_CMPLETE_SIG_EN&transmode))
1376 tmpReg |= SDIO_TRANS_COMP_ATA;
1379 if (0 != (TRANS_MODE_MULTI_BLOCK&transmode))
1381 tmpReg |= SDIO_TRANS_MULTIBLK;
1384 if (0 != (TRANS_MODE_READ&transmode))
1386 tmpReg |= SDIO_TRANS_DIR_READ;
1389 if (0 != (TRANS_MODE_CMD12_EN&transmode))
1391 tmpReg |= SDIO_TRANS_AUTO_CMD12_EN;
1394 if (0 != (TRANS_MODE_BLOCK_COUNT_EN&transmode))
1396 tmpReg |= SDIO_TRANS_BLK_CNT_EN;
1399 if (0 != (TRANS_MODE_DMA_EN&transmode))
1401 tmpReg |= SDIO_TRANS_DMA_EN;
1404 if (0 != (CMD_HAVE_DATA&transmode))
1406 tmpReg |= SDIO_CMD_DATA_PRESENT;
1411 case CMD_TYPE_NORMAL:
1413 tmpReg |= SDIO_CMD_TYPE_NML;
1417 case CMD_TYPE_SUSPEND:
1419 tmpReg |= SDIO_CMD_TYPE_SUSPEND;
1423 case CMD_TYPE_RESUME:
1425 tmpReg |= SDIO_CMD_TYPE_RESUME;
1429 case CMD_TYPE_ABORT:
1431 tmpReg |= SDIO_CMD_TYPE_ABORT;
1437 SCI_ASSERT (0);/*assert verified*/
1446 tmpReg |= SDIO_NO_RSP;
1506 SCI_ASSERT (0);/*assert verified*/
1511 tmpReg &= ~(0x7<<8);
1512 tmpReg |= (cmdIndex<<24);
1514 sdhost_handler->host_cfg->CMD_TRANSMODE = tmpReg;
1520 /*****************************************************************************/
1521 // Description: Get content from host response register
1524 // sdhost_handler: the handle of host driver
1525 // Response: the type of response
1526 // rspBuf: the content will be stored in this place
1530 /*****************************************************************************/
1531 PUBLIC void SDHOST_GetRspFromBuf (SDHOST_HANDLE sdhost_handler,CMD_RSP_TYPE_E Response,uint8 *rspBuf)
1533 uint32 tmpRspBuf[4];
1536 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1538 tmpRspBuf[0] = sdhost_handler->host_cfg->RSP0;
1539 tmpRspBuf[1] = sdhost_handler->host_cfg->RSP1;
1540 tmpRspBuf[2] = sdhost_handler->host_cfg->RSP2;
1541 tmpRspBuf[3] = sdhost_handler->host_cfg->RSP3;
1543 // SDHOST_PRINT(("RSP %x %x %x %x",tmpRspBuf[0],tmpRspBuf[1],tmpRspBuf[2],tmpRspBuf[3]));
1545 for (i = 0; i < 4; i++)
1547 rspBuf[0+ (i<<2) ] = (uint8) ( (tmpRspBuf[i]>>24) &0xFF);
1548 rspBuf[1+ (i<<2) ] = (uint8) ( (tmpRspBuf[i]>>16) &0xFF);
1549 rspBuf[2+ (i<<2) ] = (uint8) ( (tmpRspBuf[i]>>8) &0xFF);
1550 rspBuf[3+ (i<<2) ] = (uint8) (tmpRspBuf[i]&0xFF);
1567 rspBuf[0] = (uint8) ( (tmpRspBuf[0]>>24) &0xFF);
1568 rspBuf[1] = (uint8) ( (tmpRspBuf[0]>>16) &0xFF);
1569 rspBuf[2] = (uint8) ( (tmpRspBuf[0]>>8) &0xFF);
1570 rspBuf[3] = (uint8) (tmpRspBuf[0]&0xFF);
1576 rspBuf[0] = (uint8) ( (tmpRspBuf[3]>>16) &0xFF);
1577 rspBuf[1] = (uint8) ( (tmpRspBuf[3]>>8) &0xFF);
1578 rspBuf[2] = (uint8) (tmpRspBuf[3]&0xFF);
1580 rspBuf[3] = (uint8) ( (tmpRspBuf[2]>>24) &0xFF);
1581 rspBuf[4] = (uint8) ( (tmpRspBuf[2]>>16) &0xFF);
1582 rspBuf[5] = (uint8) ( (tmpRspBuf[2]>>8) &0xFF);
1583 rspBuf[6] = (uint8) (tmpRspBuf[2]&0xFF);
1585 rspBuf[7] = (uint8) ( (tmpRspBuf[1]>>24) &0xFF);
1586 rspBuf[8] = (uint8) ( (tmpRspBuf[1]>>16) &0xFF);
1587 rspBuf[9] = (uint8) ( (tmpRspBuf[1]>>8) &0xFF);
1588 rspBuf[10] = (uint8) (tmpRspBuf[1]&0xFF);
1590 rspBuf[11] = (uint8) ( (tmpRspBuf[0]>>24) &0xFF);
1591 rspBuf[12] = (uint8) ( (tmpRspBuf[0]>>16) &0xFF);
1592 rspBuf[13] = (uint8) ( (tmpRspBuf[0]>>8) &0xFF);
1593 rspBuf[14] = (uint8) (tmpRspBuf[0]&0xFF);
1599 SCI_ASSERT (0);/*assert verified*/
1611 /*****************************************************************************/
1612 // Description: Get function that host can be support
1615 // sdhost_handler: the handle of host driver
1620 /*****************************************************************************/
1621 LOCAL void _GetSDHOSTCapbility (SDHOST_HANDLE sdhost_handler,SDHOST_CAPBILIT_T *capbility)
1623 volatile uint32 tmpReg;
1624 SCI_MEMSET (capbility,0,sizeof (SDHOST_CAPBILIT_T));
1626 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1628 tmpReg = sdhost_handler->host_cfg->CAPBILITY;
1630 if (0 != (tmpReg & BIT_26))
1632 capbility->capbility_function |= CAP_VOL_1_8V;
1635 if (0 != (tmpReg & BIT_25))
1637 capbility->capbility_function |= CAP_VOL_3_0V;
1640 if (0 != (tmpReg & BIT_24))
1642 capbility->capbility_function |= CAP_VOL_3_3V;
1645 if (0 != (tmpReg & BIT_23))
1647 capbility->capbility_function |= SPD_RESU;
1650 if (0 != (tmpReg & BIT_22))
1652 capbility->capbility_function |= DMA_SPT;
1655 if (0 != (tmpReg & BIT_21))
1657 capbility->capbility_function |= HIGH_SPEED;
1660 switch (tmpReg & (0x3<<16))
1663 capbility->cability_Max_BlkLen = 512;
1667 capbility->cability_Max_BlkLen = 1024;
1671 capbility->cability_Max_BlkLen = 2048;
1675 capbility->cability_Max_BlkLen = 4096;
1679 SCI_ASSERT (0);/*assert verified*/
1683 capbility->sd_Base_Max_Clk = ( (tmpReg & (0x3F<<8)) >>8) * 1000000;
1685 if (0!= (tmpReg & BIT_7))
1687 capbility->timeOut_Clk_unit = 1000000;
1691 capbility->timeOut_Clk_unit = 1000;
1694 capbility->timeOut_Base_Clk = (tmpReg & 0x3F) *capbility->timeOut_Clk_unit;
1696 tmpReg = sdhost_handler->host_cfg->CURR_CAPBILITY;
1697 capbility->max_current_for_1_8 = ( (tmpReg & (0xFF<<16)) >>16);
1698 capbility->max_current_for_3_0 = ( (tmpReg & (0xFF<<8)) >>8);
1699 capbility->max_current_for_3_3 = (tmpReg & 0xFF);
1701 SDHOST_PRINT ( ("capbility_function = %x",sdhost_handler->capbility.capbility_function));
1702 SDHOST_PRINT ( ("cability_Max_BlkLen = %x",sdhost_handler->capbility.cability_Max_BlkLen));
1703 SDHOST_PRINT ( ("sd_Base_Max_Clk = %x",sdhost_handler->capbility.sd_Base_Max_Clk));
1704 SDHOST_PRINT ( ("timeOut_Clk_unit = %x",sdhost_handler->capbility.timeOut_Clk_unit));
1705 SDHOST_PRINT ( ("timeOut_Base_Clk = %x",sdhost_handler->capbility.timeOut_Base_Clk));
1706 SDHOST_PRINT ( ("max_current_for_1_8 = %x",sdhost_handler->capbility.max_current_for_1_8));
1707 SDHOST_PRINT ( ("max_current_for_3_0 = %x",sdhost_handler->capbility.max_current_for_3_0));
1708 SDHOST_PRINT ( ("max_current_for_3_3 = %x",sdhost_handler->capbility.max_current_for_3_3));
1712 /*****************************************************************************/
1713 // Description: Clear Normal int Status register ,if event is happed ,host will Set status in register
1716 // sdhost_handler: the handle of host driver
1717 // err_msg: that int you want to clear
1721 /*****************************************************************************/
1722 PUBLIC void SDHOST_NML_IntStatus_Clr (SDHOST_HANDLE sdhost_handler,uint32 msg)
1724 volatile uint32 tmpReg = 0;
1725 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1727 if (0 != (msg&SIG_ERR))
1729 //_ERR_IntStatus_Clr (sdhost_handler,ERR_ALL);
1730 tmpReg |= (BIT_28|BIT_24|BIT_23|BIT_22|BIT_21|
1731 BIT_20|BIT_19|BIT_18|BIT_17|BIT_16);
1735 if (0 != (msg&SIG_CARD_IN))
1737 //sdhost_handler->host_cfg->INT_STA =BIT_8;
1740 if (0 != (msg&SIG_CARD_INSERT))
1745 if (0 != (msg&SIG_CARD_REMOVE))
1750 if (0 != (msg&SIG_BUF_RD_RDY))
1755 if (0 != (msg&SIG_BUF_WD_RDY))
1760 if (0 != (msg&SIG_DMA_INT))
1765 if (0 != (msg&SIG_BLK_CAP))
1770 if (0 != (msg&SIG_TRANS_CMP))
1775 if (0 != (msg&SIG_CMD_CMP))
1779 sdhost_handler->host_cfg->INT_STA = tmpReg;
1782 /*****************************************************************************/
1783 // Description: Enable Normal int Signal register ,
1786 // sdhost_handler: the handle of host driver
1787 // err_msg: that int you want to Enable
1791 /*****************************************************************************/
1792 PUBLIC void SDHOST_NML_IntStatus_En (SDHOST_HANDLE sdhost_handler,uint32 msg)
1794 volatile uint32 tmpReg = 0;
1796 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1798 if (0 != (msg&SIG_ERR))
1800 //_ERR_IntStatus_En (sdhost_handler,sdhost_handler->err_filter);
1801 err_msg = sdhost_handler->err_filter;
1802 if (0 != (err_msg&ERR_RSP))
1807 if (0 != (err_msg&ERR_CMD12))
1812 if (0 != (err_msg&ERR_CUR_LIMIT))
1817 if (0 != (err_msg&ERR_DATA_END))
1822 if (0 != (err_msg&ERR_DATA_CRC))
1827 if (0 != (err_msg&ERR_DATA_TIMEOUT))
1832 if (0 != (err_msg&ERR_CMD_INDEX))
1837 if (0 != (err_msg&ERR_CMD_END))
1842 if (0 != (err_msg&ERR_CMD_CRC))
1847 if (0 != (err_msg&ERR_CMD_TIMEOUT))
1854 if (0 != (msg&SIG_CARD_IN))
1859 if (0 != (msg&SIG_CARD_INSERT))
1864 if (0 != (msg&SIG_CARD_REMOVE))
1869 if (0 != (msg&SIG_BUF_RD_RDY))
1874 if (0 != (msg&SIG_BUF_WD_RDY))
1879 if (0 != (msg&SIG_DMA_INT))
1884 if (0 != (msg&SIG_BLK_CAP))
1889 if (0 != (msg&SIG_TRANS_CMP))
1894 if (0 != (msg&SIG_CMD_CMP))
1898 sdhost_handler->host_cfg->INT_STA_EN |= tmpReg;
1899 sdhost_handler->IntEnabled = sdhost_handler->host_cfg->INT_STA_EN;
1903 /*****************************************************************************/
1904 // Description: Disable Normal int Signal register
1907 // sdhost_handler: the handle of host driver
1908 // err_msg: that int you want to Disable
1912 /*****************************************************************************/
1913 PUBLIC void SDHOST_NML_IntStatus_Dis (SDHOST_HANDLE sdhost_handler,uint32 msg)
1915 volatile uint32 tmpReg = 0;
1916 uint32 reg_value = sdhost_handler->IntEnabled;
1917 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1919 if (0 != (msg&SIG_ERR))
1921 //_ERR_IntStatus_Dis (sdhost_handler,ERR_ALL);
1922 tmpReg |= (BIT_28|BIT_24|BIT_23|BIT_22|BIT_21|
1923 BIT_20|BIT_19|BIT_18|BIT_17|BIT_16);
1927 if (0 != (msg&SIG_CARD_IN))
1932 if (0 != (msg&SIG_CARD_INSERT))
1937 if (0 != (msg&SIG_CARD_REMOVE))
1942 if (0 != (msg&SIG_BUF_RD_RDY))
1947 if (0 != (msg&SIG_BUF_WD_RDY))
1952 if (0 != (msg&SIG_DMA_INT))
1957 if (0 != (msg&SIG_BLK_CAP))
1962 if (0 != (msg&SIG_TRANS_CMP))
1967 if (0 != (msg&SIG_CMD_CMP))
1971 reg_value &= ~tmpReg;
1972 sdhost_handler->host_cfg->INT_STA_EN = reg_value;
1973 sdhost_handler->IntEnabled = reg_value;
1977 /*****************************************************************************/
1978 // Description: Enable Normal int Signal register ,if normal event is happed ,host will send interrupt to Arm
1981 // sdhost_handler: the handle of host driver
1982 // err_msg: that int you want to Enable
1986 /*****************************************************************************/
1987 PUBLIC void SDHOST_NML_IntSig_En (SDHOST_HANDLE sdhost_handler,uint32 msg)
1989 volatile uint32 tmpReg = 0;
1991 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
1993 if (0 != (msg&SIG_ERR))
1995 //_ERR_IntSig_En (sdhost_handler,sdhost_handler->err_filter);
1996 err_msg = sdhost_handler->err_filter;
1997 if (0 != (err_msg&ERR_RSP))
2002 if (0 != (err_msg&ERR_CMD12))
2007 if (0 != (err_msg&ERR_CUR_LIMIT))
2012 if (0 != (err_msg&ERR_DATA_END))
2017 if (0 != (err_msg&ERR_DATA_CRC))
2022 if (0 != (err_msg&ERR_DATA_TIMEOUT))
2027 if (0 != (err_msg&ERR_CMD_INDEX))
2032 if (0 != (err_msg&ERR_CMD_END))
2037 if (0 != (err_msg&ERR_CMD_CRC))
2042 if (0 != (err_msg&ERR_CMD_TIMEOUT))
2049 if (0 != (msg&SIG_CARD_IN))
2054 if (0 != (msg&SIG_CARD_INSERT))
2059 if (0 != (msg&SIG_CARD_REMOVE))
2064 if (0 != (msg&SIG_BUF_RD_RDY))
2069 if (0 != (msg&SIG_BUF_WD_RDY))
2074 if (0 != (msg&SIG_DMA_INT))
2079 if (0 != (msg&SIG_BLK_CAP))
2084 if (0 != (msg&SIG_TRANS_CMP))
2089 if (0 != (msg&SIG_CMD_CMP))
2093 sdhost_handler->host_cfg->INT_SIG_EN |= tmpReg;
2097 /*****************************************************************************/
2098 // Description: Disable Normal int Signal register ,if normal event is happed ,host will not send interrupt to Arm
2101 // sdhost_handler: the handle of host driver
2102 // err_msg: that int you want to Disable
2106 /*****************************************************************************/
2107 PUBLIC void SDHOST_NML_IntSig_Dis (SDHOST_HANDLE sdhost_handler,uint32 msg)
2109 volatile uint32 tmpReg = 0;
2110 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2112 if (0 != (msg&SIG_ERR))
2114 //_ERR_IntSig_Dis (sdhost_handler,ERR_ALL);
2115 tmpReg |= (BIT_28|BIT_24|BIT_23|BIT_22|BIT_21|
2116 BIT_20|BIT_19|BIT_18|BIT_17|BIT_16);
2120 if (0 != (msg&SIG_CARD_IN))
2125 if (0 != (msg&SIG_CARD_INSERT))
2130 if (0 != (msg&SIG_CARD_REMOVE))
2135 if (0 != (msg&SIG_BUF_RD_RDY))
2140 if (0 != (msg&SIG_BUF_WD_RDY))
2145 if (0 != (msg&SIG_DMA_INT))
2150 if (0 != (msg&SIG_BLK_CAP))
2155 if (0 != (msg&SIG_TRANS_CMP))
2160 if (0 != (msg&SIG_CMD_CMP))
2164 sdhost_handler->host_cfg->INT_SIG_EN &= ~tmpReg;
2168 /*****************************************************************************/
2169 // Description: Get normal int status register ,to confirm which normal event has happened
2172 // sdhost_handler: the handle of host driver
2174 // uint32 value: indicate which event happened
2176 /*****************************************************************************/
2177 PUBLIC uint32 SDHOST_GetNMLIntStatus (SDHOST_HANDLE sdhost_handler)
2179 volatile uint32 tmpReg;
2182 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2184 tmpReg = sdhost_handler->host_cfg->INT_STA;
2187 if (0 != (tmpReg & BIT_15))
2192 if (0 != (tmpReg & BIT_8))
2197 if (0 != (tmpReg & BIT_6))
2199 msg |= SIG_CARD_INSERT;
2202 if (0 != (tmpReg & BIT_7))
2204 msg |= SIG_CARD_REMOVE;
2207 if (0 != (tmpReg & BIT_5))
2209 msg |= SIG_BUF_RD_RDY;
2212 if (0 != (tmpReg & BIT_4))
2214 msg |= SIG_BUF_WD_RDY;
2217 if (0 != (tmpReg & BIT_3))
2222 if (0 != (tmpReg & BIT_2))
2227 if (0 != (tmpReg & BIT_1))
2229 msg |= SIG_TRANS_CMP;
2232 if (0 != (tmpReg & BIT_0))
2241 /*****************************************************************************/
2242 // Description: if error interrupt happened ,this function is used to confirm which error event happened
2245 // sdhost_handler: the handle of host driver
2247 // uint32 value: indicate which error event happened
2249 /*****************************************************************************/
2250 PUBLIC uint32 SDHOST_GetErrCode (SDHOST_HANDLE sdhost_handler)
2252 volatile uint32 tmpReg;
2255 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2257 tmpReg = sdhost_handler->host_cfg->INT_STA;
2260 if (0 != (tmpReg & BIT_28))
2265 if (0 != (tmpReg & BIT_24))
2267 err_msg |= ERR_CMD12;
2270 if (0 != (tmpReg & BIT_23))
2272 err_msg |= ERR_CUR_LIMIT;
2275 if (0 != (tmpReg & BIT_22))
2277 err_msg |= ERR_DATA_END;
2280 if (0 != (tmpReg & BIT_21))
2282 err_msg |= ERR_DATA_CRC;
2285 if (0 != (tmpReg & BIT_20))
2287 err_msg |= ERR_DATA_TIMEOUT;
2290 if (0 != (tmpReg & BIT_19))
2292 err_msg |= ERR_CMD_INDEX;
2295 if (0 != (tmpReg & BIT_18))
2297 err_msg |= ERR_CMD_END;
2300 if (0 != (tmpReg & BIT_17))
2302 err_msg |= ERR_CMD_CRC;
2305 if (0 != (tmpReg & BIT_16))
2307 err_msg |= ERR_CMD_TIMEOUT;
2313 /*****************************************************************************/
2314 // Description: this function is used to set which error event you want to watched ,other error event will be ignored if happened
2317 // sdhost_handler: the handle of host driver
2318 // err_msg: the event you want to watched
2322 /*****************************************************************************/
2323 PUBLIC void SDHOST_SetErrCodeFilter (SDHOST_HANDLE sdhost_handler,uint32 err_msg)
2325 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2327 sdhost_handler->err_filter = err_msg;
2330 /*****************************************************************************/
2331 // Description: To indicate event that happened from which slot
2334 // sdhost_handler: the handle of host driver
2336 // uint32 value: indicate which slot event happened
2338 /*****************************************************************************/
2339 LOCAL SDHOST_SLOT_NO _GetIntSDHOSTSlotNum (uint32 port)
2343 #if defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
2344 ret = SDHOST_SLOT_7;
2346 #if defined(CONFIG_TIGER)|| defined (CONFIG_SC7710G2)
2347 if(SDHOST_SLOT_6 == port){
2348 tmpReg = REG32 (SDIO2_NML_INT_SIG_EN);
2350 REG32 (SDIO2_NML_INT_SIG_EN) = BIT_1;
2351 tmpReg = REG32 (SDIO2_SLOT_INT_STS);
2355 tmpReg = REG32 (EMMC_SLOT_INT_STS);
2358 tmpReg = REG32 (SDIO0_SLOT_INT_STS);
2362 tmpReg = REG32 (SDIO1_SLOT_INT_STS);
2366 if ( (tmpReg& (0x01<<0)))
2368 #if defined(CONFIG_TIGER) || defined (CONFIG_SC7710G2)
2369 if(SDHOST_SLOT_6 == port)
2370 ret = SDHOST_SLOT_6;
2372 ret = SDHOST_SLOT_7;
2375 ret = SDHOST_SLOT_0;
2377 ret = SDHOST_SLOT_1;
2381 else if ( (tmpReg& (0x01<<1)))
2383 ret = SDHOST_SLOT_1;
2385 else if ( (tmpReg& (0x01<<2)))
2387 ret = SDHOST_SLOT_2;
2389 else if ( (tmpReg& (0x01<<3)))
2391 ret = SDHOST_SLOT_3;
2393 else if ( (tmpReg& (0x01<<4)))
2395 ret = SDHOST_SLOT_4;
2397 else if ( (tmpReg& (0x01<<5)))
2399 ret = SDHOST_SLOT_5;
2401 else if ( (tmpReg& (0x01<<6)))
2403 ret = SDHOST_SLOT_6;
2405 else if ( (tmpReg& (0x01<<7)))
2407 ret = SDHOST_SLOT_7;
2411 ret = SDHOST_SLOT_MAX_NUM;
2412 SCI_ASSERT (0);/*assert to do*/
2418 /*****************************************************************************/
2419 // Description: This function is called by interrupt service .is event happened ,this funtion will
2420 // clear the event and call the callback of application
2423 // isrnum: the number of arm interrupt
2427 /*****************************************************************************/
2428 PUBLIC ISR_EXE_T _SDHOST_IrqHandle (uint32 isrnum)
2430 ISR_Buffer_T buffer;
2431 SDHOST_HANDLE sdhost_handler;
2433 buffer.slotNum = isrnum;
2434 if(buffer.slotNum == SDHOST_SLOT_MAX_NUM){
2437 sdhost_handler = &sdio_port_ctl[buffer.slotNum];
2438 buffer.pSdhost_handler = &sdio_port_ctl[buffer.slotNum];
2440 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2442 if (FALSE == sdhost_handler->open_flag)
2444 SDHOST_NML_IntSig_Dis (sdhost_handler, SIG_ALL);
2445 SDHOST_NML_IntStatus_Dis (sdhost_handler, SIG_ALL);
2446 SDHOST_NML_IntStatus_Clr (sdhost_handler, SIG_ALL);
2450 if (NULL == sdhost_handler->sigCallBack)
2452 SDHOST_NML_IntSig_Dis (sdhost_handler, SIG_ALL);
2453 SDHOST_NML_IntStatus_Dis (sdhost_handler, SIG_ALL);
2454 SDHOST_NML_IntStatus_Clr (sdhost_handler, SIG_ALL);
2458 buffer.msg = SDHOST_GetNMLIntStatus (sdhost_handler);
2459 buffer.errCode = SDHOST_GetErrCode (sdhost_handler);
2461 SDHOST_NML_IntSig_Dis (sdhost_handler, buffer.msg);
2462 SDHOST_NML_IntStatus_Dis (sdhost_handler, buffer.msg);
2463 SDHOST_NML_IntStatus_Clr (sdhost_handler, buffer.msg);
2465 IsrWriteBuffer (buffer);
2467 sdhost_handler->sigCallBack (buffer.msg, buffer.errCode, buffer.slotNum);
2473 /*****************************************************************************/
2474 // Description: This function is SDIO 's HISR.
2475 // 1. THE priority is higher than normal task.
2476 // 2. Is not real ISR.
2477 // Author: steve.zhan
2479 /*****************************************************************************/
2480 LOCAL void SdhostHisrFunc (uint32 cnt, void *pData)
2482 ISR_Buffer_T buffer;
2484 while (!threadReadBuffer (&buffer))
2486 buffer.pSdhost_handler->sigCallBack (buffer.msg, buffer.errCode, buffer.slotNum);
2490 LOCAL void _SDHOST_Pin_select(SDHOST_SLOT_NO slot_NO)
2492 if(slot_NO == SDHOST_SLOT_1){
2493 *(volatile uint32*)(0x8c0003e8) = 0x280; //SD1 CMD pullup drv3, strongest strength
2494 *(volatile uint32*)(0x8c0003ec) = 0x280; //SD1 D0 pullup drv3, strongest strength
2495 *(volatile uint32*)(0x8c0003f0) = 0x280; //SD1 D1 pullup drv3, strongest strength
2496 *(volatile uint32*)(0x8c0003f4) = 0x280; //SD1 D2 pullup drv3, strongest strength
2497 *(volatile uint32*)(0x8c0003f8) = 0x280; //SD1 D3 pullup drv3, strongest strength
2498 *(volatile uint32*)(0x8c0003fc) = 0x280; //SD1 D3 pullup drv3, strongest strength
2502 /*****************************************************************************/
2503 // Description: Regist host slot
2506 // slot_NO: which slot you want to used
2507 // fun: this function will be called when event happened
2512 /*****************************************************************************/
2513 PUBLIC SDHOST_HANDLE SDHOST_Register (SDHOST_SLOT_NO slot_NO,SDIO_CALLBACK fun)
2515 uint32 status = 0, i = 0;
2517 SCI_ASSERT (slot_NO < SDHOST_SLOT_MAX_NUM);/*assert verified*/
2519 if (TRUE == sdio_port_ctl[slot_NO].open_flag)
2523 if (slot_NO == SDHOST_SLOT_7)
2525 sdio_port_ctl[slot_NO].host_cfg =
2526 (SDIO_REG_CFG *) ( (volatile uint32 *) EMMC_BASE_ADDR);
2527 SDHOST_SD_clk_OnOff(&sdio_port_ctl[slot_NO], CLK_OFF);
2529 SDHOST_Reset_Controller(slot_NO);
2530 sdio_port_ctl[slot_NO].slotNo = slot_NO;
2532 #if defined (CONFIG_SC8825) || defined(CONFIG_SPX15)||defined(CONFIG_SPX30G) || (defined CONFIG_SC9630)/*CONFIG_SPX15 must be before CONFIG_SC8830*/
2533 sdio_port_ctl[slot_NO].open_flag = TRUE;
2534 #if defined(CONFIG_ARCH_SCX20L) || defined(CONFIG_SPX20)
2535 sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_192M);
2537 sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_384M);
2539 #elif defined (CONFIG_SC8830)
2540 sdio_port_ctl[slot_NO].open_flag = TRUE;
2541 sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_192M);
2542 #elif defined(CONFIG_SC7710G2)
2543 // SDHOST_Slot_select(slot_NO); if necessary
2544 sdio_port_ctl[slot_NO].open_flag = TRUE;
2545 sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_96M);
2547 _SDHOST_Pin_select(slot_NO);
2548 sdio_port_ctl[slot_NO].open_flag = TRUE;
2549 sdio_port_ctl[slot_NO].baseClock = SDHOST_BaseClk_Set (slot_NO,SDIO_BASE_CLK_48M);
2552 #if defined(CONFIG_FPGA)
2553 sdio_port_ctl[slot_NO].baseClock = 36000000;
2560 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO0_BASE_ADDR);
2566 #if defined(CONFIG_TIGER) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
2567 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO0_BASE_ADDR+0x100) );
2569 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO1_BASE_ADDR);
2575 #if defined(CONFIG_TIGER) || defined(CONFIG_SC7710G2)
2577 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO2_BASE_ADDR) );
2582 #if defined(CONFIG_TIGER) || defined(CONFIG_SC7710G2)
2584 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO1_BASE_ADDR );
2589 #if defined(CONFIG_TIGER) || defined(CONFIG_SC7710G2)
2591 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO1_BASE_ADDR+0x100) );
2596 #if defined(CONFIG_TIGER) || defined(CONFIG_SC7710G2)
2598 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) (SDIO1_BASE_ADDR+0x200) );
2603 REG32(REG_PIN_SD0_CLK0)= 0x300;
2604 REG32(REG_PIN_SD0_CLK1)= 0x300;
2605 REG32(REG_PIN_SD0_CMD) = 0x280;
2606 REG32(REG_PIN_SD0_D0) = 0x280;
2607 REG32(REG_PIN_SD0_D0) = 0x280;
2608 REG32(REG_PIN_SD0_D1) = 0x280;
2609 REG32(REG_PIN_SD0_D2) = 0x280;
2610 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO0_BASE_ADDR );
2613 #if defined(CONFIG_TIGER) || defined(CONFIG_SC7710G2) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
2614 #ifdef CONFIG_SC8825
2615 REG32(PIN_CTL3_REG) |= (0x1ff<<8);// set emmc data line, cmd line pull up resistor 4.7k
2616 REG32(PIN_SD3CLK_REG) = 0x200;
2617 REG32(PIN_SD3CMD_REG)= 0x280;
2618 REG32(PIN_SD3D0_REG) = 0x280;
2619 REG32(PIN_SD3D1_REG) = 0x280;
2620 REG32(PIN_SD3D2_REG) = 0x280;
2621 REG32(PIN_SD3D3_REG) = 0x280;
2622 REG32(PIN_SD3D4_REG) = 0x280;
2623 REG32(PIN_SD3D5_REG) = 0x280;
2624 REG32(PIN_SD3D6_REG) = 0x280;
2625 REG32(PIN_SD3D7_REG) = 0x280;
2626 #elif defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
2629 #define REG_PIN_EMMC_CLK REG_PIN_NFREN
2630 #define REG_PIN_EMMC_CMD REG_PIN_NFRB
2631 #define REG_PIN_EMMC_D0 REG_PIN_NFWPN
2632 #define REG_PIN_EMMC_D1 REG_PIN_NFD11
2633 #define REG_PIN_EMMC_D2 REG_PIN_NFD14
2634 #define REG_PIN_EMMC_D3 REG_PIN_NFD7
2635 #define REG_PIN_EMMC_D4 REG_PIN_NFD5
2636 #define REG_PIN_EMMC_D5 REG_PIN_NFD4
2637 #define REG_PIN_EMMC_D6 REG_PIN_NFCLE
2638 #define REG_PIN_EMMC_D7 REG_PIN_NFALE
2639 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x210;
2640 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x1198;
2641 REG32(CTL_PIN_BASE+REG_PIN_NFD10) = 0x198;
2642 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x198;
2643 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x198;
2644 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x198;
2645 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x198;
2646 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x198;
2647 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x198;
2648 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x198;
2649 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x198;
2650 #elif defined(CONFIG_SPX30G)
2651 #if defined(CONFIG_SPX20)
2652 #define REG_PIN_EMMC_CLK REG_PIN_NFREN
2653 #define REG_PIN_EMMC_CMD REG_PIN_NFRBN
2654 #define REG_PIN_EMMC_D0 REG_PIN_NFWPN
2655 #define REG_PIN_EMMC_D1 REG_PIN_NFD11
2656 #define REG_PIN_EMMC_D2 REG_PIN_NFD14
2657 #define REG_PIN_EMMC_D3 REG_PIN_NFD7
2658 #define REG_PIN_EMMC_D4 REG_PIN_NFD5
2659 #define REG_PIN_EMMC_D5 REG_PIN_NFD4
2660 #define REG_PIN_EMMC_D6 REG_PIN_NFCLE
2661 #define REG_PIN_EMMC_D7 REG_PIN_NFALE
2662 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x80010;
2663 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x80090;
2664 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x80090;
2665 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x80090;
2666 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x80090;
2667 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x80090;
2668 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x80090;
2669 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x80090;
2670 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x80090;
2671 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x80090;
2673 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x00;
2674 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x80;
2675 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x80;
2676 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x80;
2677 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x80;
2678 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x80;
2679 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x80;
2680 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x80;
2681 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x80;
2682 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x80;
2684 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x80000;
2685 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x80080;
2686 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x80080;
2687 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x80080;
2688 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x80080;
2689 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x80080;
2690 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x80080;
2691 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x80080;
2692 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x80080;
2693 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x80080;
2696 #elif defined(CONFIG_SC9630)
2697 #define REG_PIN_EMMC_CLK REG_PIN_NFREN
2698 #define REG_PIN_EMMC_CMD REG_PIN_NFRB
2699 #define REG_PIN_EMMC_D0 REG_PIN_NFWPN
2700 #define REG_PIN_EMMC_D1 REG_PIN_NFD11
2701 #define REG_PIN_EMMC_D2 REG_PIN_NFD14
2702 #define REG_PIN_EMMC_D3 REG_PIN_NFD7
2703 #define REG_PIN_EMMC_D4 REG_PIN_NFD5
2704 #define REG_PIN_EMMC_D5 REG_PIN_NFD4
2705 #define REG_PIN_EMMC_D6 REG_PIN_NFCLE
2706 #define REG_PIN_EMMC_D7 REG_PIN_NFALE
2707 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) SDIO0_BASE_ADDR );
2709 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CLK)= 0x82011;
2710 REG32(CTL_PIN_BASE+REG_PIN_EMMC_CMD)= 0x83094;
2711 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D0) = 0x3094;
2712 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D1) = 0x3094;
2713 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D2) = 0x3094;
2714 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D3) = 0x3094;
2715 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D4) = 0x3094;
2716 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D5) = 0x3094;
2717 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D6) = 0x3094;
2718 REG32(CTL_PIN_BASE+REG_PIN_EMMC_D7) = 0x3094;
2720 /* Other chip,do nothing*/
2722 #endif /* CONFIG_FPGA */
2725 sdio_port_ctl[slot_NO].host_cfg = (SDIO_REG_CFG *) ( (volatile uint32 *) EMMC_BASE_ADDR);
2731 SCI_ASSERT (0);/*assert to do*/
2735 sdio_port_ctl[slot_NO].sigCallBack = fun;
2736 sdio_port_ctl[slot_NO].err_filter = 0;
2739 status = ISR_RegHandler_Ex (TB_SDIO_INT, (TB_ISR) _SDHOST_IrqHandle, SdhostHisrFunc, CHIPDRV_HISR_PRIO_1, NULL);
2740 if (TB_SUCCESS == status)
2742 CHIPDRV_EnableIRQINT (TB_SDIO_INT);
2745 return &sdio_port_ctl[slot_NO];
2748 /*****************************************************************************/
2749 // Description: Free the slot resource
2752 // sdhost_handler: the handler of host driver ,this is returned by SDHOST_Register
2757 /*****************************************************************************/
2758 PUBLIC BOOLEAN SDHOST_UnRegister (SDHOST_HANDLE sdhost_handler)
2760 SCI_ASSERT (TRUE == _RegisterVerifyHOST (sdhost_handler));/*assert verified*/
2762 SDHOST_SD_POWER (sdhost_handler,POWR_OFF);
2763 SDHOST_RST (sdhost_handler,RST_ALL);
2764 SDHOST_SD_clk_OnOff (sdhost_handler,CLK_OFF);
2765 SDHOST_internalClk_OnOff (sdhost_handler,CLK_OFF);
2766 sdhost_handler->sigCallBack = NULL;
2767 sdhost_handler->open_flag = FALSE;
2771 //====================
2772 //---External function---
2773 //====================
2774 /*****************************************************************************/
2775 // Description: Set basic clk of host,card clk will divided from this clk
2778 // sdhost_handler: the handler of host driver ,this is returned by SDHOST_Register
2779 // sdio_base_clk: the frequecy that you want to set
2781 // uint32 value :the frequency that be used acctually
2782 // Note: This function must be applied according different platform
2783 /*****************************************************************************/
2786 PUBLIC uint32 SDHOST_BaseClk_Set (uint32 sdio_base_clk)
2788 #ifdef PLATFORM_SC8800G
2791 //Select the clk source of SDIO
2792 if (sdio_base_clk >= SDIO_BASE_CLK_96M)
2794 DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_96M);
2795 clk = SDIO_BASE_CLK_96M;
2797 else if (sdio_base_clk >= SDIO_BASE_CLK_64M)
2799 clk = SDIO_BASE_CLK_64M;
2800 DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_64M);
2803 else if (sdio_base_clk >= SDIO_BASE_CLK_48M)
2805 clk = SDIO_BASE_CLK_48M;
2806 DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_48M);
2810 clk = SDIO_BASE_CLK_26M;
2811 DEVICE_SetClock (s_dev_sdio, SDIO_BASE_CLK_26M);
2819 PUBLIC uint32 SDHOST_BaseClk_Set(SDHOST_SLOT_NO slot_NO,uint32 sdio_base_clk)
2823 #if defined(CONFIG_SC8830) || (defined CONFIG_SC9630)
2826 #if defined(CONFIG_SPX15)|| (defined CONFIG_SC9630)
2827 #if defined (CONFIG_ARCH_SCX20L)
2828 if (slot_NO == SDHOST_SLOT_6)
2830 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
2832 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2834 REG32(REG_AP_CLK_SDIO0_CFG) |= 3;
2835 clk = SDIO_BASE_CLK_384M;
2837 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2839 REG32(REG_AP_CLK_SDIO0_CFG) |= 2;
2840 clk = SDIO_BASE_CLK_312M;
2842 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2844 REG32(REG_AP_CLK_SDIO0_CFG) |= 1;
2845 clk = SDIO_BASE_CLK_256M;
2849 clk = SDIO_BASE_CLK_26M;
2852 if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2854 REG32(REG_AP_CLK_SDIO0_CFG) |= 3;
2855 clk = SDIO_BASE_CLK_256M;
2857 else if (sdio_base_clk >= SDIO_BASE_CLK_192M)
2859 REG32(REG_AP_CLK_SDIO0_CFG) |= 2;
2860 clk = SDIO_BASE_CLK_192M;
2862 else if (sdio_base_clk >= SDIO_BASE_CLK_153M)
2864 REG32(REG_AP_CLK_SDIO0_CFG) |= 1;
2865 clk = SDIO_BASE_CLK_256M;
2869 clk = SDIO_BASE_CLK_26M;
2875 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
2877 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2879 REG32(REG_AP_CLK_EMMC_CFG) |= 3;
2880 clk = SDIO_BASE_CLK_384M;
2882 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2884 REG32(REG_AP_CLK_EMMC_CFG) |= 2;
2885 clk = SDIO_BASE_CLK_312M;
2887 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2889 REG32(REG_AP_CLK_EMMC_CFG) |= 1;
2890 clk = SDIO_BASE_CLK_256M;
2894 clk = SDIO_BASE_CLK_26M;
2897 if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2899 REG32(REG_AP_CLK_EMMC_CFG) |= 3;
2900 clk = SDIO_BASE_CLK_256M;
2902 else if (sdio_base_clk >= SDIO_BASE_CLK_192M)
2904 REG32(REG_AP_CLK_EMMC_CFG) |= 2;
2905 clk = SDIO_BASE_CLK_192M;
2907 else if (sdio_base_clk >= SDIO_BASE_CLK_153M)
2909 REG32(REG_AP_CLK_EMMC_CFG) |= 1;
2910 clk = SDIO_BASE_CLK_153M;
2914 clk = SDIO_BASE_CLK_26M;
2918 #elif defined(CONFIG_SPX20)
2919 if (slot_NO == SDHOST_SLOT_6)
2921 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
2923 if (sdio_base_clk == SDIO_BASE_CLK_192M)
2925 REG32(REG_AP_CLK_SDIO0_CFG) |= 3;
2926 clk = SDIO_BASE_CLK_192M;
2928 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2930 REG32(REG_AP_CLK_SDIO0_CFG) |= 2;
2931 clk = SDIO_BASE_CLK_312M;
2933 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2935 REG32(REG_AP_CLK_SDIO0_CFG) |= 1;
2936 clk = SDIO_BASE_CLK_256M;
2940 clk = SDIO_BASE_CLK_26M;
2945 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
2947 if (sdio_base_clk == SDIO_BASE_CLK_192M)
2949 REG32(REG_AP_CLK_EMMC_CFG) |= 3;
2950 clk = SDIO_BASE_CLK_192M;
2952 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2954 REG32(REG_AP_CLK_EMMC_CFG) |= 2;
2955 clk = SDIO_BASE_CLK_312M;
2957 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2959 REG32(REG_AP_CLK_EMMC_CFG) |= 1;
2960 clk = SDIO_BASE_CLK_256M;
2964 clk = SDIO_BASE_CLK_26M;
2968 if (slot_NO == SDHOST_SLOT_6)
2970 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
2972 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2974 REG32(REG_AP_CLK_SDIO0_CFG) |= 3;
2975 clk = SDIO_BASE_CLK_384M;
2977 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
2979 REG32(REG_AP_CLK_SDIO0_CFG) |= 2;
2980 clk = SDIO_BASE_CLK_312M;
2982 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
2984 REG32(REG_AP_CLK_SDIO0_CFG) |= 1;
2985 clk = SDIO_BASE_CLK_256M;
2989 clk = SDIO_BASE_CLK_26M;
2994 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
2996 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
2998 REG32(REG_AP_CLK_EMMC_CFG) |= 3;
2999 clk = SDIO_BASE_CLK_384M;
3001 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3003 REG32(REG_AP_CLK_EMMC_CFG) |= 2;
3004 clk = SDIO_BASE_CLK_312M;
3006 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3008 REG32(REG_AP_CLK_EMMC_CFG) |= 1;
3009 clk = SDIO_BASE_CLK_256M;
3013 clk = SDIO_BASE_CLK_26M;
3018 if (slot_NO == SDHOST_SLOT_6)
3020 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3022 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3024 REG32(REG_AP_CLK_SDIO0_CFG) |= 3;
3025 clk = SDIO_BASE_CLK_384M;
3027 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3029 REG32(REG_AP_CLK_SDIO0_CFG) |= 2;
3030 clk = SDIO_BASE_CLK_312M;
3032 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3034 REG32(REG_AP_CLK_SDIO0_CFG) |= 1;
3035 clk = SDIO_BASE_CLK_256M;
3039 clk = SDIO_BASE_CLK_26M;
3044 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3046 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3048 REG32(REG_AP_CLK_EMMC_CFG) |= 3;
3049 clk = SDIO_BASE_CLK_384M;
3051 else if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3053 REG32(REG_AP_CLK_EMMC_CFG) |= 2;
3054 clk = SDIO_BASE_CLK_312M;
3056 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3058 REG32(REG_AP_CLK_EMMC_CFG) |= 1;
3059 clk = SDIO_BASE_CLK_256M;
3063 clk = SDIO_BASE_CLK_26M;
3068 if (slot_NO == SDHOST_SLOT_6)
3070 if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3072 REG32(REG_AP_CLK_SDIO0_CFG) |= 3;
3073 clk = SDIO_BASE_CLK_312M;
3075 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3077 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3078 REG32(REG_AP_CLK_SDIO0_CFG) |= 2;
3079 clk = SDIO_BASE_CLK_256M;
3081 if (sdio_base_clk >= SDIO_BASE_CLK_192M)
3083 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3084 REG32(REG_AP_CLK_SDIO0_CFG) |= 1;
3085 clk = SDIO_BASE_CLK_192M;
3089 REG32(REG_AP_CLK_SDIO0_CFG) &= ~3;
3090 clk = SDIO_BASE_CLK_26M;
3095 if (sdio_base_clk >= SDIO_BASE_CLK_312M)
3097 REG32(REG_AP_CLK_EMMC_CFG) |= 3;
3098 clk = SDIO_BASE_CLK_312M;
3100 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3102 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3103 REG32(REG_AP_CLK_EMMC_CFG) |= 2;
3104 clk = SDIO_BASE_CLK_256M;
3106 if (sdio_base_clk >= SDIO_BASE_CLK_192M)
3108 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3109 REG32(REG_AP_CLK_EMMC_CFG) |= 1;
3110 clk = SDIO_BASE_CLK_192M;
3114 REG32(REG_AP_CLK_EMMC_CFG) &= ~3;
3115 clk = SDIO_BASE_CLK_26M;
3120 #elif defined(CONFIG_TIGER)
3121 REG32 (GR_CLK_GEN5) &= ~ (BIT_23|BIT_24);
3122 //Select the clk source of SDIO
3123 if (sdio_base_clk >= SDIO_BASE_CLK_384M)
3125 clk = SDIO_BASE_CLK_384M;
3127 else if (sdio_base_clk >= SDIO_BASE_CLK_256M)
3129 clk = SDIO_BASE_CLK_256M;
3130 REG32 (GR_CLK_GEN5) |= (1<<23);
3132 else if (sdio_base_clk >= SDIO_BASE_CLK_153M)
3134 clk = SDIO_BASE_CLK_153M;
3135 REG32 (GR_CLK_GEN5) |= (2<<23);
3139 clk = SDIO_BASE_CLK_26M;
3140 REG32 (GR_CLK_GEN5) |= (3<<23);
3142 #elif defined(CONFIG_SC7710G2)
3143 if(SDHOST_SLOT_6 == slot_NO){
3144 REG32 (GR_CLK_GEN7) &= ~ (BIT_21|BIT_22);
3145 //Select the clk source of SDIO
3146 if (sdio_base_clk >= SDIO_BASE_CLK_96M) {
3147 clk = SDIO_BASE_CLK_96M;
3148 } else if (sdio_base_clk >= SDIO_BASE_CLK_64M) {
3149 clk = SDIO_BASE_CLK_64M;
3150 REG32 (GR_CLK_GEN7) |= (1<<21);
3151 } else if (sdio_base_clk >= SDIO_BASE_CLK_48M) {
3152 clk = SDIO_BASE_CLK_48M;
3153 REG32 (GR_CLK_GEN7) |= (2<<21);
3155 clk = SDIO_BASE_CLK_26M;
3156 REG32 (GR_CLK_GEN7) |= (3<<21);
3159 REG32 (GR_CLK_GEN7) &= ~ (BIT_23|BIT_24);
3160 //Select the clk source of SDIO
3161 if (sdio_base_clk >= SDIO_BASE_CLK_384M){
3162 clk = SDIO_BASE_CLK_384M;
3163 REG32 (GR_CLK_GEN7) |= (1<<23);
3164 } else if (sdio_base_clk >= SDIO_BASE_CLK_256M){
3165 clk = SDIO_BASE_CLK_256M;
3166 REG32 (GR_CLK_GEN7) |= (2<<23);
3167 } else if (sdio_base_clk >= SDIO_BASE_CLK_153M){
3168 clk = SDIO_BASE_CLK_153M;
3169 REG32 (GR_CLK_GEN7) |= (3<<23);
3171 clk = SDIO_BASE_CLK_26M;
3173 #elif defined(PLATFORM_SC8800G)
3174 //Select the clk source of SDIO1
3175 if(SDHOST_SLOT_1 == slot_NO){
3176 *(volatile uint32 *)GR_CLK_GEN5 &= ~(BIT_19|BIT_20);
3177 if(sdio_base_clk >= SDIO_BASE_CLK_96M)
3178 clk = SDIO_BASE_CLK_96M;
3179 else if(sdio_base_clk >= SDIO_BASE_CLK_64M){
3180 clk = SDIO_BASE_CLK_64M;
3181 *(volatile uint32 *)GR_CLK_GEN5 |= (1<<19);
3182 } else if(sdio_base_clk >= SDIO_BASE_CLK_48M) {
3183 clk = SDIO_BASE_CLK_48M;
3184 *(volatile uint32 *)GR_CLK_GEN5 |= (2<<19);
3186 clk = SDIO_BASE_CLK_26M;
3187 *(volatile uint32 *)GR_CLK_GEN5 |= (3<<19);
3189 } else if(SDHOST_SLOT_0 == slot_NO){
3190 *(volatile uint32 *)GR_CLK_GEN5 &= ~(BIT_17|BIT_18);
3191 if(sdio_base_clk >= SDIO_BASE_CLK_96M)
3192 clk = SDIO_BASE_CLK_96M;
3193 else if(sdio_base_clk >= SDIO_BASE_CLK_64M){
3194 clk = SDIO_BASE_CLK_64M;
3195 *(volatile uint32 *)GR_CLK_GEN5 |= (1<<17);
3196 } else if(sdio_base_clk >= SDIO_BASE_CLK_48M) {
3197 clk = SDIO_BASE_CLK_48M;
3198 *(volatile uint32 *)GR_CLK_GEN5 |= (2<<17);
3200 clk = SDIO_BASE_CLK_26M;
3201 *(volatile uint32 *)GR_CLK_GEN5 |= (3<<17);
3210 /*****************************************************************************/
3211 // Description: select witch slot to work
3214 // slot_NO: slot number
3217 // Note: This function must be applied according different platform
3218 /*****************************************************************************/
3219 PUBLIC void SDHOST_Slot_select (SDHOST_SLOT_NO slot_NO)
3221 SCI_ASSERT (slot_NO < SDHOST_SLOT_MAX_NUM);/*assert verified*/
3222 #if !(defined(CONFIG_SC8830) || defined(CONFIG_SC9630) )
3223 * (volatile uint32 *) AHB_SDIO_CTL = (AHB_SDIO_CTRL_SLOT0); //select master0