1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
18 #include <linux/dma-mapping.h>
21 static void sdhci_reset(struct sdhci_host *host, u8 mask)
23 unsigned long timeout;
27 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
28 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
30 printf("%s: Reset 0x%x never completed.\n",
39 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
42 if (cmd->resp_type & MMC_RSP_136) {
43 /* CRC is stripped so we need to do some shifting. */
44 for (i = 0; i < 4; i++) {
45 cmd->response[i] = sdhci_readl(host,
46 SDHCI_RESPONSE + (3-i)*4) << 8;
48 cmd->response[i] |= sdhci_readb(host,
49 SDHCI_RESPONSE + (3-i)*4-1);
52 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
56 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
60 for (i = 0; i < data->blocksize; i += 4) {
61 offs = data->dest + i;
62 if (data->flags == MMC_DATA_READ)
63 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
65 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
69 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
70 static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
73 struct sdhci_adma_desc *desc;
76 desc = &host->adma_desc_table[host->desc_slot];
78 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
82 attr |= ADMA_DESC_ATTR_END;
87 desc->addr_lo = lower_32_bits(dma_addr);
88 #ifdef CONFIG_DMA_ADDR_T_64BIT
89 desc->addr_hi = upper_32_bits(dma_addr);
93 static void sdhci_prepare_adma_table(struct sdhci_host *host,
94 struct mmc_data *data)
96 uint trans_bytes = data->blocksize * data->blocks;
97 uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
99 dma_addr_t dma_addr = host->start_addr;
104 sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
105 dma_addr += ADMA_MAX_LEN;
106 trans_bytes -= ADMA_MAX_LEN;
109 sdhci_adma_desc(host, dma_addr, trans_bytes, true);
111 flush_cache((dma_addr_t)host->adma_desc_table,
112 ROUND(desc_count * sizeof(struct sdhci_adma_desc),
115 #elif defined(CONFIG_MMC_SDHCI_SDMA)
116 static void sdhci_prepare_adma_table(struct sdhci_host *host,
117 struct mmc_data *data)
120 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
121 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
122 int *is_aligned, int trans_bytes)
127 if (data->flags == MMC_DATA_READ)
130 buf = (void *)data->src;
132 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
133 ctrl &= ~SDHCI_CTRL_DMA_MASK;
134 if (host->flags & USE_ADMA64)
135 ctrl |= SDHCI_CTRL_ADMA64;
136 else if (host->flags & USE_ADMA)
137 ctrl |= SDHCI_CTRL_ADMA32;
138 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
140 if (host->flags & USE_SDMA &&
141 (host->force_align_buffer ||
142 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
143 ((unsigned long)buf & 0x7) != 0x0))) {
145 if (data->flags != MMC_DATA_READ)
146 memcpy(host->align_buffer, buf, trans_bytes);
147 buf = host->align_buffer;
150 host->start_addr = dma_map_single(buf, trans_bytes,
151 mmc_get_dma_dir(data));
153 if (host->flags & USE_SDMA) {
154 sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
156 } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
157 sdhci_prepare_adma_table(host, data);
159 sdhci_writel(host, lower_32_bits(host->adma_addr),
161 if (host->flags & USE_ADMA64)
162 sdhci_writel(host, upper_32_bits(host->adma_addr),
163 SDHCI_ADMA_ADDRESS_HI);
167 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
168 int *is_aligned, int trans_bytes)
171 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
173 dma_addr_t start_addr = host->start_addr;
174 unsigned int stat, rdy, mask, timeout, block = 0;
175 bool transfer_done = false;
178 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
179 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
181 stat = sdhci_readl(host, SDHCI_INT_STATUS);
182 if (stat & SDHCI_INT_ERROR) {
183 pr_debug("%s: Error detected in status(0x%X)!\n",
187 if (!transfer_done && (stat & rdy)) {
188 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
190 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
191 sdhci_transfer_pio(host, data);
192 data->dest += data->blocksize;
193 if (++block >= data->blocks) {
194 /* Keep looping until the SDHCI_INT_DATA_END is
195 * cleared, even if we finished sending all the
198 transfer_done = true;
202 if ((host->flags & USE_DMA) && !transfer_done &&
203 (stat & SDHCI_INT_DMA_END)) {
204 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
205 if (host->flags & USE_SDMA) {
207 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
208 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
209 sdhci_writel(host, phys_to_bus((ulong)start_addr),
216 printf("%s: Transfer data timeout\n", __func__);
219 } while (!(stat & SDHCI_INT_DATA_END));
221 dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
222 mmc_get_dma_dir(data));
228 * No command will be sent by driver if card is busy, so driver must wait
229 * for card ready state.
230 * Every time when card is busy after timeout then (last) timeout value will be
231 * increased twice but only if it doesn't exceed global defined maximum.
232 * Each function call will use last timeout value.
234 #define SDHCI_CMD_MAX_TIMEOUT 3200
235 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
236 #define SDHCI_READ_STATUS_TIMEOUT 1000
239 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
240 struct mmc_data *data)
242 struct mmc *mmc = mmc_get_mmc_dev(dev);
245 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
246 struct mmc_data *data)
249 struct sdhci_host *host = mmc->priv;
250 unsigned int stat = 0;
252 int trans_bytes = 0, is_aligned = 1;
253 u32 mask, flags, mode;
254 unsigned int time = 0;
255 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
256 ulong start = get_timer(0);
258 host->start_addr = 0;
259 /* Timeout unit - ms */
260 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
262 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
264 /* We shouldn't wait for data inihibit for stop commands, even
265 though they might use busy signaling */
266 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
267 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
268 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
269 mask &= ~SDHCI_DATA_INHIBIT;
271 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
272 if (time >= cmd_timeout) {
273 printf("%s: MMC: %d busy ", __func__, mmc_dev);
274 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
275 cmd_timeout += cmd_timeout;
276 printf("timeout increasing to: %u ms.\n",
287 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
289 mask = SDHCI_INT_RESPONSE;
290 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
291 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
292 mask = SDHCI_INT_DATA_AVAIL;
294 if (!(cmd->resp_type & MMC_RSP_PRESENT))
295 flags = SDHCI_CMD_RESP_NONE;
296 else if (cmd->resp_type & MMC_RSP_136)
297 flags = SDHCI_CMD_RESP_LONG;
298 else if (cmd->resp_type & MMC_RSP_BUSY) {
299 flags = SDHCI_CMD_RESP_SHORT_BUSY;
301 mask |= SDHCI_INT_DATA_END;
303 flags = SDHCI_CMD_RESP_SHORT;
305 if (cmd->resp_type & MMC_RSP_CRC)
306 flags |= SDHCI_CMD_CRC;
307 if (cmd->resp_type & MMC_RSP_OPCODE)
308 flags |= SDHCI_CMD_INDEX;
309 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
310 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
311 flags |= SDHCI_CMD_DATA;
313 /* Set Transfer mode regarding to data flag */
315 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
316 mode = SDHCI_TRNS_BLK_CNT_EN;
317 trans_bytes = data->blocks * data->blocksize;
318 if (data->blocks > 1)
319 mode |= SDHCI_TRNS_MULTI;
321 if (data->flags == MMC_DATA_READ)
322 mode |= SDHCI_TRNS_READ;
324 if (host->flags & USE_DMA) {
325 mode |= SDHCI_TRNS_DMA;
326 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
329 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
332 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
333 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
334 } else if (cmd->resp_type & MMC_RSP_BUSY) {
335 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
338 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
339 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
340 start = get_timer(0);
342 stat = sdhci_readl(host, SDHCI_INT_STATUS);
343 if (stat & SDHCI_INT_ERROR)
346 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
347 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
350 printf("%s: Timeout for status update!\n",
355 } while ((stat & mask) != mask);
357 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
358 sdhci_cmd_done(host, cmd);
359 sdhci_writel(host, mask, SDHCI_INT_STATUS);
364 ret = sdhci_transfer_data(host, data);
366 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
369 stat = sdhci_readl(host, SDHCI_INT_STATUS);
370 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
372 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
373 !is_aligned && (data->flags == MMC_DATA_READ))
374 memcpy(data->dest, host->align_buffer, trans_bytes);
378 sdhci_reset(host, SDHCI_RESET_CMD);
379 sdhci_reset(host, SDHCI_RESET_DATA);
380 if (stat & SDHCI_INT_TIMEOUT)
386 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
387 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
390 struct mmc *mmc = mmc_get_mmc_dev(dev);
391 struct sdhci_host *host = mmc->priv;
393 debug("%s\n", __func__);
395 if (host->ops && host->ops->platform_execute_tuning) {
396 err = host->ops->platform_execute_tuning(mmc, opcode);
404 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
406 struct sdhci_host *host = mmc->priv;
407 unsigned int div, clk = 0, timeout;
411 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
412 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
414 printf("%s: Timeout to wait cmd & data inhibit\n",
423 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
428 if (host->ops && host->ops->set_delay)
429 host->ops->set_delay(host);
431 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
433 * Check if the Host Controller supports Programmable Clock
437 for (div = 1; div <= 1024; div++) {
438 if ((host->max_clk / div) <= clock)
443 * Set Programmable Clock Mode in the Clock
446 clk = SDHCI_PROG_CLOCK_MODE;
449 /* Version 3.00 divisors must be a multiple of 2. */
450 if (host->max_clk <= clock) {
454 div < SDHCI_MAX_DIV_SPEC_300;
456 if ((host->max_clk / div) <= clock)
463 /* Version 2.00 divisors must be a power of 2. */
464 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
465 if ((host->max_clk / div) <= clock)
471 if (host->ops && host->ops->set_clock)
472 host->ops->set_clock(host, div);
474 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
475 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
476 << SDHCI_DIVIDER_HI_SHIFT;
477 clk |= SDHCI_CLOCK_INT_EN;
478 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
482 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
483 & SDHCI_CLOCK_INT_STABLE)) {
485 printf("%s: Internal clock never stabilised.\n",
493 clk |= SDHCI_CLOCK_CARD_EN;
494 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
498 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
502 if (power != (unsigned short)-1) {
503 switch (1 << power) {
504 case MMC_VDD_165_195:
505 pwr = SDHCI_POWER_180;
509 pwr = SDHCI_POWER_300;
513 pwr = SDHCI_POWER_330;
519 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
523 pwr |= SDHCI_POWER_ON;
525 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
528 void sdhci_set_uhs_timing(struct sdhci_host *host)
530 struct mmc *mmc = host->mmc;
533 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
534 reg &= ~SDHCI_CTRL_UHS_MASK;
536 switch (mmc->selected_mode) {
539 reg |= SDHCI_CTRL_UHS_SDR50;
543 reg |= SDHCI_CTRL_UHS_DDR50;
547 reg |= SDHCI_CTRL_UHS_SDR104;
550 reg |= SDHCI_CTRL_UHS_SDR12;
553 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
557 static int sdhci_set_ios(struct udevice *dev)
559 struct mmc *mmc = mmc_get_mmc_dev(dev);
561 static int sdhci_set_ios(struct mmc *mmc)
565 struct sdhci_host *host = mmc->priv;
567 if (host->ops && host->ops->set_control_reg)
568 host->ops->set_control_reg(host);
570 if (mmc->clock != host->clock)
571 sdhci_set_clock(mmc, mmc->clock);
573 if (mmc->clk_disable)
574 sdhci_set_clock(mmc, 0);
577 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
578 if (mmc->bus_width == 8) {
579 ctrl &= ~SDHCI_CTRL_4BITBUS;
580 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
581 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
582 ctrl |= SDHCI_CTRL_8BITBUS;
584 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
585 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
586 ctrl &= ~SDHCI_CTRL_8BITBUS;
587 if (mmc->bus_width == 4)
588 ctrl |= SDHCI_CTRL_4BITBUS;
590 ctrl &= ~SDHCI_CTRL_4BITBUS;
593 if (mmc->clock > 26000000)
594 ctrl |= SDHCI_CTRL_HISPD;
596 ctrl &= ~SDHCI_CTRL_HISPD;
598 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
599 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
600 ctrl &= ~SDHCI_CTRL_HISPD;
602 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
604 /* If available, call the driver specific "post" set_ios() function */
605 if (host->ops && host->ops->set_ios_post)
606 return host->ops->set_ios_post(host);
611 static int sdhci_init(struct mmc *mmc)
613 struct sdhci_host *host = mmc->priv;
614 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
615 struct udevice *dev = mmc->dev;
617 gpio_request_by_name(dev, "cd-gpios", 0,
618 &host->cd_gpio, GPIOD_IS_IN);
621 sdhci_reset(host, SDHCI_RESET_ALL);
623 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
624 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
626 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
629 host->force_align_buffer = true;
631 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
632 host->align_buffer = memalign(8, 512 * 1024);
633 if (!host->align_buffer) {
634 printf("%s: Aligned buffer alloc failed!!!\n",
641 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
643 if (host->ops && host->ops->get_cd)
644 host->ops->get_cd(host);
646 /* Enable only interrupts served by the SD controller */
647 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
649 /* Mask all sdhci interrupt sources */
650 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
656 int sdhci_probe(struct udevice *dev)
658 struct mmc *mmc = mmc_get_mmc_dev(dev);
660 return sdhci_init(mmc);
663 static int sdhci_deferred_probe(struct udevice *dev)
666 struct mmc *mmc = mmc_get_mmc_dev(dev);
667 struct sdhci_host *host = mmc->priv;
669 if (host->ops && host->ops->deferred_probe) {
670 err = host->ops->deferred_probe(host);
677 static int sdhci_get_cd(struct udevice *dev)
679 struct mmc *mmc = mmc_get_mmc_dev(dev);
680 struct sdhci_host *host = mmc->priv;
683 /* If nonremovable, assume that the card is always present. */
684 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
686 /* If polling, assume that the card is always present. */
687 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
690 #if CONFIG_IS_ENABLED(DM_GPIO)
691 value = dm_gpio_get_value(&host->cd_gpio);
693 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
699 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
701 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
707 const struct dm_mmc_ops sdhci_ops = {
708 .send_cmd = sdhci_send_command,
709 .set_ios = sdhci_set_ios,
710 .get_cd = sdhci_get_cd,
711 .deferred_probe = sdhci_deferred_probe,
712 #ifdef MMC_SUPPORTS_TUNING
713 .execute_tuning = sdhci_execute_tuning,
717 static const struct mmc_ops sdhci_ops = {
718 .send_cmd = sdhci_send_command,
719 .set_ios = sdhci_set_ios,
724 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
725 u32 f_max, u32 f_min)
727 u32 caps, caps_1 = 0;
728 #if CONFIG_IS_ENABLED(DM_MMC)
729 u64 dt_caps, dt_caps_mask;
731 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
732 "sdhci-caps-mask", 0);
733 dt_caps = dev_read_u64_default(host->mmc->dev,
735 caps = ~(u32)dt_caps_mask &
736 sdhci_readl(host, SDHCI_CAPABILITIES);
737 caps |= (u32)dt_caps;
739 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
741 debug("%s, caps: 0x%x\n", __func__, caps);
743 #ifdef CONFIG_MMC_SDHCI_SDMA
744 if ((caps & SDHCI_CAN_DO_SDMA)) {
745 host->flags |= USE_SDMA;
747 debug("%s: Your controller doesn't support SDMA!!\n",
751 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
752 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
753 printf("%s: Your controller doesn't support SDMA!!\n",
757 host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
759 host->adma_addr = (dma_addr_t)host->adma_desc_table;
760 #ifdef CONFIG_DMA_ADDR_T_64BIT
761 host->flags |= USE_ADMA64;
763 host->flags |= USE_ADMA;
766 if (host->quirks & SDHCI_QUIRK_REG32_RW)
768 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
770 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
772 cfg->name = host->name;
773 #ifndef CONFIG_DM_MMC
774 cfg->ops = &sdhci_ops;
777 /* Check whether the clock multiplier is supported or not */
778 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
779 #if CONFIG_IS_ENABLED(DM_MMC)
780 caps_1 = ~(u32)(dt_caps_mask >> 32) &
781 sdhci_readl(host, SDHCI_CAPABILITIES_1);
782 caps_1 |= (u32)(dt_caps >> 32);
784 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
786 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
787 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
788 SDHCI_CLOCK_MUL_SHIFT;
791 if (host->max_clk == 0) {
792 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
793 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
794 SDHCI_CLOCK_BASE_SHIFT;
796 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
797 SDHCI_CLOCK_BASE_SHIFT;
798 host->max_clk *= 1000000;
800 host->max_clk *= host->clk_mul;
802 if (host->max_clk == 0) {
803 printf("%s: Hardware doesn't specify base clock frequency\n",
807 if (f_max && (f_max < host->max_clk))
810 cfg->f_max = host->max_clk;
814 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
815 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
817 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
820 if (caps & SDHCI_CAN_VDD_330)
821 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
822 if (caps & SDHCI_CAN_VDD_300)
823 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
824 if (caps & SDHCI_CAN_VDD_180)
825 cfg->voltages |= MMC_VDD_165_195;
827 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
828 cfg->voltages |= host->voltages;
830 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
832 /* Since Host Controller Version3.0 */
833 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
834 if (!(caps & SDHCI_CAN_DO_8BIT))
835 cfg->host_caps &= ~MMC_MODE_8BIT;
838 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
839 cfg->host_caps &= ~MMC_MODE_HS;
840 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
843 if (!(cfg->voltages & MMC_VDD_165_195))
844 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
845 SDHCI_SUPPORT_DDR50);
847 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
848 SDHCI_SUPPORT_DDR50))
849 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
851 if (caps_1 & SDHCI_SUPPORT_SDR104) {
852 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
854 * SD3.0: SDR104 is supported so (for eMMC) the caps2
855 * field can be promoted to support HS200.
857 cfg->host_caps |= MMC_CAP(MMC_HS_200);
858 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
859 cfg->host_caps |= MMC_CAP(UHS_SDR50);
862 if (caps_1 & SDHCI_SUPPORT_DDR50)
863 cfg->host_caps |= MMC_CAP(UHS_DDR50);
866 cfg->host_caps |= host->host_caps;
868 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
874 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
876 return mmc_bind(dev, mmc, cfg);
879 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
883 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
887 host->mmc = mmc_create(&host->cfg, host);
888 if (host->mmc == NULL) {
889 printf("%s: mmc create fail!\n", __func__);