drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <sdhci.h>
  17 #include <dm.h>
  18 #include <linux/dma-mapping.h>
  19
  20 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  21 {
  22         unsigned long timeout;
  23
  24         /* Wait max 100 ms */
  25         timeout = 100;
  26         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  27         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  28                 if (timeout == 0) {
  29                         printf("%s: Reset 0x%x never completed.\n",
  30                                __func__, (int)mask);
  31                         return;
  32                 }
  33                 timeout--;
  34                 udelay(1000);
  35         }
  36 }
  37
  38 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  39 {
  40         int i;
  41         if (cmd->resp_type & MMC_RSP_136) {
  42                 /* CRC is stripped so we need to do some shifting. */
  43                 for (i = 0; i < 4; i++) {
  44                         cmd->response[i] = sdhci_readl(host,
  45                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  46                         if (i != 3)
  47                                 cmd->response[i] |= sdhci_readb(host,
  48                                                 SDHCI_RESPONSE + (3-i)*4-1);
  49                 }
  50         } else {
  51                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  52         }
  53 }
  54
  55 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  56 {
  57         int i;
  58         char *offs;
  59         for (i = 0; i < data->blocksize; i += 4) {
  60                 offs = data->dest + i;
  61                 if (data->flags == MMC_DATA_READ)
  62                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  63                 else
  64                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  65         }
  66 }
  67
  68 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  69 static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
  70                             u16 len, bool end)
  71 {
  72         struct sdhci_adma_desc *desc;
  73         u8 attr;
  74
  75         desc = &host->adma_desc_table[host->desc_slot];
  76
  77         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  78         if (!end)
  79                 host->desc_slot++;
  80         else
  81                 attr |= ADMA_DESC_ATTR_END;
  82
  83         desc->attr = attr;
  84         desc->len = len;
  85         desc->reserved = 0;
  86         desc->addr_lo = lower_32_bits(dma_addr);
  87 #ifdef CONFIG_DMA_ADDR_T_64BIT
  88         desc->addr_hi = upper_32_bits(dma_addr);
  89 #endif
  90 }
  91
  92 static void sdhci_prepare_adma_table(struct sdhci_host *host,
  93                                      struct mmc_data *data)
  94 {
  95         uint trans_bytes = data->blocksize * data->blocks;
  96         uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
  97         int i = desc_count;
  98         dma_addr_t dma_addr = host->start_addr;
  99
 100         host->desc_slot = 0;
 101
 102         while (--i) {
 103                 sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
 104                 dma_addr += ADMA_MAX_LEN;
 105                 trans_bytes -= ADMA_MAX_LEN;
 106         }
 107
 108         sdhci_adma_desc(host, dma_addr, trans_bytes, true);
 109
 110         flush_cache((dma_addr_t)host->adma_desc_table,
 111                     ROUND(desc_count * sizeof(struct sdhci_adma_desc),
 112                           ARCH_DMA_MINALIGN));
 113 }
 114 #elif defined(CONFIG_MMC_SDHCI_SDMA)
 115 static void sdhci_prepare_adma_table(struct sdhci_host *host,
 116                                      struct mmc_data *data)
 117 {}
 118 #endif
 119 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 120 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 121                               int *is_aligned, int trans_bytes)
 122 {
 123         unsigned char ctrl;
 124         void *buf;
 125
 126         if (data->flags == MMC_DATA_READ)
 127                 buf = data->dest;
 128         else
 129                 buf = (void *)data->src;
 130
 131         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 132         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 133         if (host->flags & USE_ADMA64)
 134                 ctrl |= SDHCI_CTRL_ADMA64;
 135         else if (host->flags & USE_ADMA)
 136                 ctrl |= SDHCI_CTRL_ADMA32;
 137         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 138
 139         if (host->flags & USE_SDMA &&
 140             (host->force_align_buffer ||
 141              (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
 142               ((unsigned long)buf & 0x7) != 0x0))) {
 143                 *is_aligned = 0;
 144                 if (data->flags != MMC_DATA_READ)
 145                         memcpy(host->align_buffer, buf, trans_bytes);
 146                 buf = host->align_buffer;
 147         }
 148
 149         host->start_addr = dma_map_single(buf, trans_bytes,
 150                                           mmc_get_dma_dir(data));
 151
 152         if (host->flags & USE_SDMA) {
 153                 sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
 154         } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 155                 sdhci_prepare_adma_table(host, data);
 156
 157                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 158                              SDHCI_ADMA_ADDRESS);
 159                 if (host->flags & USE_ADMA64)
 160                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 161                                      SDHCI_ADMA_ADDRESS_HI);
 162         }
 163 }
 164 #else
 165 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 166                               int *is_aligned, int trans_bytes)
 167 {}
 168 #endif
 169 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 170 {
 171         dma_addr_t start_addr = host->start_addr;
 172         unsigned int stat, rdy, mask, timeout, block = 0;
 173         bool transfer_done = false;
 174
 175         timeout = 1000000;
 176         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 177         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 178         do {
 179                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 180                 if (stat & SDHCI_INT_ERROR) {
 181                         pr_debug("%s: Error detected in status(0x%X)!\n",
 182                                  __func__, stat);
 183                         return -EIO;
 184                 }
 185                 if (!transfer_done && (stat & rdy)) {
 186                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 187                                 continue;
 188                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 189                         sdhci_transfer_pio(host, data);
 190                         data->dest += data->blocksize;
 191                         if (++block >= data->blocks) {
 192                                 /* Keep looping until the SDHCI_INT_DATA_END is
 193                                  * cleared, even if we finished sending all the
 194                                  * blocks.
 195                                  */
 196                                 transfer_done = true;
 197                                 continue;
 198                         }
 199                 }
 200                 if ((host->flags & USE_DMA) && !transfer_done &&
 201                     (stat & SDHCI_INT_DMA_END)) {
 202                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 203                         if (host->flags & USE_SDMA) {
 204                                 start_addr &=
 205                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 206                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 207                                 sdhci_writel(host, start_addr,
 208                                              SDHCI_DMA_ADDRESS);
 209                         }
 210                 }
 211                 if (timeout-- > 0)
 212                         udelay(10);
 213                 else {
 214                         printf("%s: Transfer data timeout\n", __func__);
 215                         return -ETIMEDOUT;
 216                 }
 217         } while (!(stat & SDHCI_INT_DATA_END));
 218
 219         dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
 220                          mmc_get_dma_dir(data));
 221
 222         return 0;
 223 }
 224
 225 /*
 226  * No command will be sent by driver if card is busy, so driver must wait
 227  * for card ready state.
 228  * Every time when card is busy after timeout then (last) timeout value will be
 229  * increased twice but only if it doesn't exceed global defined maximum.
 230  * Each function call will use last timeout value.
 231  */
 232 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 233 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 234 #define SDHCI_READ_STATUS_TIMEOUT               1000
 235
 236 #ifdef CONFIG_DM_MMC
 237 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 238                               struct mmc_data *data)
 239 {
 240         struct mmc *mmc = mmc_get_mmc_dev(dev);
 241
 242 #else
 243 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 244                               struct mmc_data *data)
 245 {
 246 #endif
 247         struct sdhci_host *host = mmc->priv;
 248         unsigned int stat = 0;
 249         int ret = 0;
 250         int trans_bytes = 0, is_aligned = 1;
 251         u32 mask, flags, mode;
 252         unsigned int time = 0;
 253         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 254         ulong start = get_timer(0);
 255
 256         host->start_addr = 0;
 257         /* Timeout unit - ms */
 258         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 259
 260         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 261
 262         /* We shouldn't wait for data inihibit for stop commands, even
 263            though they might use busy signaling */
 264         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 265             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 266               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 267                 mask &= ~SDHCI_DATA_INHIBIT;
 268
 269         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 270                 if (time >= cmd_timeout) {
 271                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 272                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 273                                 cmd_timeout += cmd_timeout;
 274                                 printf("timeout increasing to: %u ms.\n",
 275                                        cmd_timeout);
 276                         } else {
 277                                 puts("timeout.\n");
 278                                 return -ECOMM;
 279                         }
 280                 }
 281                 time++;
 282                 udelay(1000);
 283         }
 284
 285         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 286
 287         mask = SDHCI_INT_RESPONSE;
 288         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 289              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 290                 mask = SDHCI_INT_DATA_AVAIL;
 291
 292         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 293                 flags = SDHCI_CMD_RESP_NONE;
 294         else if (cmd->resp_type & MMC_RSP_136)
 295                 flags = SDHCI_CMD_RESP_LONG;
 296         else if (cmd->resp_type & MMC_RSP_BUSY) {
 297                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 298                 if (data)
 299                         mask |= SDHCI_INT_DATA_END;
 300         } else
 301                 flags = SDHCI_CMD_RESP_SHORT;
 302
 303         if (cmd->resp_type & MMC_RSP_CRC)
 304                 flags |= SDHCI_CMD_CRC;
 305         if (cmd->resp_type & MMC_RSP_OPCODE)
 306                 flags |= SDHCI_CMD_INDEX;
 307         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 308             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 309                 flags |= SDHCI_CMD_DATA;
 310
 311         /* Set Transfer mode regarding to data flag */
 312         if (data) {
 313                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 314                 mode = SDHCI_TRNS_BLK_CNT_EN;
 315                 trans_bytes = data->blocks * data->blocksize;
 316                 if (data->blocks > 1)
 317                         mode |= SDHCI_TRNS_MULTI;
 318
 319                 if (data->flags == MMC_DATA_READ)
 320                         mode |= SDHCI_TRNS_READ;
 321
 322                 if (host->flags & USE_DMA) {
 323                         mode |= SDHCI_TRNS_DMA;
 324                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 325                 }
 326
 327                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 328                                 data->blocksize),
 329                                 SDHCI_BLOCK_SIZE);
 330                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 331                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 332         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 333                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 334         }
 335
 336         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 337         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 338         start = get_timer(0);
 339         do {
 340                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 341                 if (stat & SDHCI_INT_ERROR)
 342                         break;
 343
 344                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 345                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 346                                 return 0;
 347                         } else {
 348                                 printf("%s: Timeout for status update!\n",
 349                                        __func__);
 350                                 return -ETIMEDOUT;
 351                         }
 352                 }
 353         } while ((stat & mask) != mask);
 354
 355         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 356                 sdhci_cmd_done(host, cmd);
 357                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 358         } else
 359                 ret = -1;
 360
 361         if (!ret && data)
 362                 ret = sdhci_transfer_data(host, data);
 363
 364         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 365                 udelay(1000);
 366
 367         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 368         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 369         if (!ret) {
 370                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 371                                 !is_aligned && (data->flags == MMC_DATA_READ))
 372                         memcpy(data->dest, host->align_buffer, trans_bytes);
 373                 return 0;
 374         }
 375
 376         sdhci_reset(host, SDHCI_RESET_CMD);
 377         sdhci_reset(host, SDHCI_RESET_DATA);
 378         if (stat & SDHCI_INT_TIMEOUT)
 379                 return -ETIMEDOUT;
 380         else
 381                 return -ECOMM;
 382 }
 383
 384 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 385 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 386 {
 387         int err;
 388         struct mmc *mmc = mmc_get_mmc_dev(dev);
 389         struct sdhci_host *host = mmc->priv;
 390
 391         debug("%s\n", __func__);
 392
 393         if (host->ops && host->ops->platform_execute_tuning) {
 394                 err = host->ops->platform_execute_tuning(mmc, opcode);
 395                 if (err)
 396                         return err;
 397                 return 0;
 398         }
 399         return 0;
 400 }
 401 #endif
 402 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 403 {
 404         struct sdhci_host *host = mmc->priv;
 405         unsigned int div, clk = 0, timeout;
 406
 407         /* Wait max 20 ms */
 408         timeout = 200;
 409         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 410                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 411                 if (timeout == 0) {
 412                         printf("%s: Timeout to wait cmd & data inhibit\n",
 413                                __func__);
 414                         return -EBUSY;
 415                 }
 416
 417                 timeout--;
 418                 udelay(100);
 419         }
 420
 421         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 422
 423         if (clock == 0)
 424                 return 0;
 425
 426         if (host->ops && host->ops->set_delay)
 427                 host->ops->set_delay(host);
 428
 429         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 430                 /*
 431                  * Check if the Host Controller supports Programmable Clock
 432                  * Mode.
 433                  */
 434                 if (host->clk_mul) {
 435                         for (div = 1; div <= 1024; div++) {
 436                                 if ((host->max_clk / div) <= clock)
 437                                         break;
 438                         }
 439
 440                         /*
 441                          * Set Programmable Clock Mode in the Clock
 442                          * Control register.
 443                          */
 444                         clk = SDHCI_PROG_CLOCK_MODE;
 445                         div--;
 446                 } else {
 447                         /* Version 3.00 divisors must be a multiple of 2. */
 448                         if (host->max_clk <= clock) {
 449                                 div = 1;
 450                         } else {
 451                                 for (div = 2;
 452                                      div < SDHCI_MAX_DIV_SPEC_300;
 453                                      div += 2) {
 454                                         if ((host->max_clk / div) <= clock)
 455                                                 break;
 456                                 }
 457                         }
 458                         div >>= 1;
 459                 }
 460         } else {
 461                 /* Version 2.00 divisors must be a power of 2. */
 462                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 463                         if ((host->max_clk / div) <= clock)
 464                                 break;
 465                 }
 466                 div >>= 1;
 467         }
 468
 469         if (host->ops && host->ops->set_clock)
 470                 host->ops->set_clock(host, div);
 471
 472         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 473         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 474                 << SDHCI_DIVIDER_HI_SHIFT;
 475         clk |= SDHCI_CLOCK_INT_EN;
 476         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 477
 478         /* Wait max 20 ms */
 479         timeout = 20;
 480         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 481                 & SDHCI_CLOCK_INT_STABLE)) {
 482                 if (timeout == 0) {
 483                         printf("%s: Internal clock never stabilised.\n",
 484                                __func__);
 485                         return -EBUSY;
 486                 }
 487                 timeout--;
 488                 udelay(1000);
 489         }
 490
 491         clk |= SDHCI_CLOCK_CARD_EN;
 492         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 493         return 0;
 494 }
 495
 496 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 497 {
 498         u8 pwr = 0;
 499
 500         if (power != (unsigned short)-1) {
 501                 switch (1 << power) {
 502                 case MMC_VDD_165_195:
 503                         pwr = SDHCI_POWER_180;
 504                         break;
 505                 case MMC_VDD_29_30:
 506                 case MMC_VDD_30_31:
 507                         pwr = SDHCI_POWER_300;
 508                         break;
 509                 case MMC_VDD_32_33:
 510                 case MMC_VDD_33_34:
 511                         pwr = SDHCI_POWER_330;
 512                         break;
 513                 }
 514         }
 515
 516         if (pwr == 0) {
 517                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 518                 return;
 519         }
 520
 521         pwr |= SDHCI_POWER_ON;
 522
 523         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 524 }
 525
 526 void sdhci_set_uhs_timing(struct sdhci_host *host)
 527 {
 528         struct mmc *mmc = host->mmc;
 529         u32 reg;
 530
 531         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 532         reg &= ~SDHCI_CTRL_UHS_MASK;
 533
 534         switch (mmc->selected_mode) {
 535         case UHS_SDR50:
 536         case MMC_HS_52:
 537                 reg |= SDHCI_CTRL_UHS_SDR50;
 538                 break;
 539         case UHS_DDR50:
 540         case MMC_DDR_52:
 541                 reg |= SDHCI_CTRL_UHS_DDR50;
 542                 break;
 543         case UHS_SDR104:
 544         case MMC_HS_200:
 545                 reg |= SDHCI_CTRL_UHS_SDR104;
 546                 break;
 547         default:
 548                 reg |= SDHCI_CTRL_UHS_SDR12;
 549         }
 550
 551         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 552 }
 553
 554 #ifdef CONFIG_DM_MMC
 555 static int sdhci_set_ios(struct udevice *dev)
 556 {
 557         struct mmc *mmc = mmc_get_mmc_dev(dev);
 558 #else
 559 static int sdhci_set_ios(struct mmc *mmc)
 560 {
 561 #endif
 562         u32 ctrl;
 563         struct sdhci_host *host = mmc->priv;
 564
 565         if (host->ops && host->ops->set_control_reg)
 566                 host->ops->set_control_reg(host);
 567
 568         if (mmc->clock != host->clock)
 569                 sdhci_set_clock(mmc, mmc->clock);
 570
 571         if (mmc->clk_disable)
 572                 sdhci_set_clock(mmc, 0);
 573
 574         /* Set bus width */
 575         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 576         if (mmc->bus_width == 8) {
 577                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 578                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 579                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 580                         ctrl |= SDHCI_CTRL_8BITBUS;
 581         } else {
 582                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 583                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 584                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 585                 if (mmc->bus_width == 4)
 586                         ctrl |= SDHCI_CTRL_4BITBUS;
 587                 else
 588                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 589         }
 590
 591         if (mmc->clock > 26000000)
 592                 ctrl |= SDHCI_CTRL_HISPD;
 593         else
 594                 ctrl &= ~SDHCI_CTRL_HISPD;
 595
 596         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 597             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 598                 ctrl &= ~SDHCI_CTRL_HISPD;
 599
 600         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 601
 602         /* If available, call the driver specific "post" set_ios() function */
 603         if (host->ops && host->ops->set_ios_post)
 604                 return host->ops->set_ios_post(host);
 605
 606         return 0;
 607 }
 608
 609 static int sdhci_init(struct mmc *mmc)
 610 {
 611         struct sdhci_host *host = mmc->priv;
 612 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 613         struct udevice *dev = mmc->dev;
 614
 615         gpio_request_by_name(dev, "cd-gpios", 0,
 616                              &host->cd_gpio, GPIOD_IS_IN);
 617 #endif
 618
 619         sdhci_reset(host, SDHCI_RESET_ALL);
 620
 621 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 622         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 623         /*
 624          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 625          * is defined.
 626          */
 627         host->force_align_buffer = true;
 628 #else
 629         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 630                 host->align_buffer = memalign(8, 512 * 1024);
 631                 if (!host->align_buffer) {
 632                         printf("%s: Aligned buffer alloc failed!!!\n",
 633                                __func__);
 634                         return -ENOMEM;
 635                 }
 636         }
 637 #endif
 638
 639         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 640
 641         if (host->ops && host->ops->get_cd)
 642                 host->ops->get_cd(host);
 643
 644         /* Enable only interrupts served by the SD controller */
 645         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 646                      SDHCI_INT_ENABLE);
 647         /* Mask all sdhci interrupt sources */
 648         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 649
 650         return 0;
 651 }
 652
 653 #ifdef CONFIG_DM_MMC
 654 int sdhci_probe(struct udevice *dev)
 655 {
 656         struct mmc *mmc = mmc_get_mmc_dev(dev);
 657
 658         return sdhci_init(mmc);
 659 }
 660
 661 static int sdhci_deferred_probe(struct udevice *dev)
 662 {
 663         int err;
 664         struct mmc *mmc = mmc_get_mmc_dev(dev);
 665         struct sdhci_host *host = mmc->priv;
 666
 667         if (host->ops && host->ops->deferred_probe) {
 668                 err = host->ops->deferred_probe(host);
 669                 if (err)
 670                         return err;
 671         }
 672         return 0;
 673 }
 674
 675 static int sdhci_get_cd(struct udevice *dev)
 676 {
 677         struct mmc *mmc = mmc_get_mmc_dev(dev);
 678         struct sdhci_host *host = mmc->priv;
 679         int value;
 680
 681         /* If nonremovable, assume that the card is always present. */
 682         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 683                 return 1;
 684         /* If polling, assume that the card is always present. */
 685         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 686                 return 1;
 687
 688 #if CONFIG_IS_ENABLED(DM_GPIO)
 689         value = dm_gpio_get_value(&host->cd_gpio);
 690         if (value >= 0) {
 691                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 692                         return !value;
 693                 else
 694                         return value;
 695         }
 696 #endif
 697         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 698                    SDHCI_CARD_PRESENT);
 699         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 700                 return !value;
 701         else
 702                 return value;
 703 }
 704
 705 const struct dm_mmc_ops sdhci_ops = {
 706         .send_cmd       = sdhci_send_command,
 707         .set_ios        = sdhci_set_ios,
 708         .get_cd         = sdhci_get_cd,
 709         .deferred_probe = sdhci_deferred_probe,
 710 #ifdef MMC_SUPPORTS_TUNING
 711         .execute_tuning = sdhci_execute_tuning,
 712 #endif
 713 };
 714 #else
 715 static const struct mmc_ops sdhci_ops = {
 716         .send_cmd       = sdhci_send_command,
 717         .set_ios        = sdhci_set_ios,
 718         .init           = sdhci_init,
 719 };
 720 #endif
 721
 722 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 723                 u32 f_max, u32 f_min)
 724 {
 725         u32 caps, caps_1 = 0;
 726 #if CONFIG_IS_ENABLED(DM_MMC)
 727         u64 dt_caps, dt_caps_mask;
 728
 729         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 730                                             "sdhci-caps-mask", 0);
 731         dt_caps = dev_read_u64_default(host->mmc->dev,
 732                                        "sdhci-caps", 0);
 733         caps = ~(u32)dt_caps_mask &
 734                sdhci_readl(host, SDHCI_CAPABILITIES);
 735         caps |= (u32)dt_caps;
 736 #else
 737         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 738 #endif
 739         debug("%s, caps: 0x%x\n", __func__, caps);
 740
 741 #ifdef CONFIG_MMC_SDHCI_SDMA
 742         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 743                 printf("%s: Your controller doesn't support SDMA!!\n",
 744                        __func__);
 745                 return -EINVAL;
 746         }
 747
 748         host->flags |= USE_SDMA;
 749 #endif
 750 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 751         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 752                 printf("%s: Your controller doesn't support SDMA!!\n",
 753                        __func__);
 754                 return -EINVAL;
 755         }
 756         host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
 757
 758         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 759 #ifdef CONFIG_DMA_ADDR_T_64BIT
 760         host->flags |= USE_ADMA64;
 761 #else
 762         host->flags |= USE_ADMA;
 763 #endif
 764 #endif
 765         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 766                 host->version =
 767                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 768         else
 769                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 770
 771         cfg->name = host->name;
 772 #ifndef CONFIG_DM_MMC
 773         cfg->ops = &sdhci_ops;
 774 #endif
 775
 776         /* Check whether the clock multiplier is supported or not */
 777         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 778 #if CONFIG_IS_ENABLED(DM_MMC)
 779                 caps_1 = ~(u32)(dt_caps_mask >> 32) &
 780                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 781                 caps_1 |= (u32)(dt_caps >> 32);
 782 #else
 783                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 784 #endif
 785                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 786                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 787                                 SDHCI_CLOCK_MUL_SHIFT;
 788         }
 789
 790         if (host->max_clk == 0) {
 791                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 792                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 793                                 SDHCI_CLOCK_BASE_SHIFT;
 794                 else
 795                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 796                                 SDHCI_CLOCK_BASE_SHIFT;
 797                 host->max_clk *= 1000000;
 798                 if (host->clk_mul)
 799                         host->max_clk *= host->clk_mul;
 800         }
 801         if (host->max_clk == 0) {
 802                 printf("%s: Hardware doesn't specify base clock frequency\n",
 803                        __func__);
 804                 return -EINVAL;
 805         }
 806         if (f_max && (f_max < host->max_clk))
 807                 cfg->f_max = f_max;
 808         else
 809                 cfg->f_max = host->max_clk;
 810         if (f_min)
 811                 cfg->f_min = f_min;
 812         else {
 813                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 814                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 815                 else
 816                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 817         }
 818         cfg->voltages = 0;
 819         if (caps & SDHCI_CAN_VDD_330)
 820                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 821         if (caps & SDHCI_CAN_VDD_300)
 822                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 823         if (caps & SDHCI_CAN_VDD_180)
 824                 cfg->voltages |= MMC_VDD_165_195;
 825
 826         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 827                 cfg->voltages |= host->voltages;
 828
 829         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 830
 831         /* Since Host Controller Version3.0 */
 832         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 833                 if (!(caps & SDHCI_CAN_DO_8BIT))
 834                         cfg->host_caps &= ~MMC_MODE_8BIT;
 835         }
 836
 837         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 838                 cfg->host_caps &= ~MMC_MODE_HS;
 839                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 840         }
 841
 842         if (!(cfg->voltages & MMC_VDD_165_195) ||
 843             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 844                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 845                             SDHCI_SUPPORT_DDR50);
 846
 847         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 848                       SDHCI_SUPPORT_DDR50))
 849                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 850
 851         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 852                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 853                 /*
 854                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 855                  * field can be promoted to support HS200.
 856                  */
 857                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 858         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 859                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 860         }
 861
 862         if (caps_1 & SDHCI_SUPPORT_DDR50)
 863                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 864
 865         if (host->host_caps)
 866                 cfg->host_caps |= host->host_caps;
 867
 868         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 869
 870         return 0;
 871 }
 872
 873 #ifdef CONFIG_BLK
 874 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 875 {
 876         return mmc_bind(dev, mmc, cfg);
 877 }
 878 #else
 879 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 880 {
 881         int ret;
 882
 883         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 884         if (ret)
 885                 return ret;
 886
 887         host->mmc = mmc_create(&host->cfg, host);
 888         if (host->mmc == NULL) {
 889                 printf("%s: mmc create fail!\n", __func__);
 890                 return -ENOMEM;
 891         }
 892
 893         return 0;
 894 }
 895 #endif