drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <sdhci.h>
  17 #include <dm.h>
  18
  19 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  20 {
  21         unsigned long timeout;
  22
  23         /* Wait max 100 ms */
  24         timeout = 100;
  25         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  26         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  27                 if (timeout == 0) {
  28                         printf("%s: Reset 0x%x never completed.\n",
  29                                __func__, (int)mask);
  30                         return;
  31                 }
  32                 timeout--;
  33                 udelay(1000);
  34         }
  35 }
  36
  37 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  38 {
  39         int i;
  40         if (cmd->resp_type & MMC_RSP_136) {
  41                 /* CRC is stripped so we need to do some shifting. */
  42                 for (i = 0; i < 4; i++) {
  43                         cmd->response[i] = sdhci_readl(host,
  44                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  45                         if (i != 3)
  46                                 cmd->response[i] |= sdhci_readb(host,
  47                                                 SDHCI_RESPONSE + (3-i)*4-1);
  48                 }
  49         } else {
  50                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  51         }
  52 }
  53
  54 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  55 {
  56         int i;
  57         char *offs;
  58         for (i = 0; i < data->blocksize; i += 4) {
  59                 offs = data->dest + i;
  60                 if (data->flags == MMC_DATA_READ)
  61                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  62                 else
  63                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  64         }
  65 }
  66
  67 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  68 static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len,
  69                             bool end)
  70 {
  71         struct sdhci_adma_desc *desc;
  72         u8 attr;
  73
  74         desc = &host->adma_desc_table[host->desc_slot];
  75
  76         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  77         if (!end)
  78                 host->desc_slot++;
  79         else
  80                 attr |= ADMA_DESC_ATTR_END;
  81
  82         desc->attr = attr;
  83         desc->len = len;
  84         desc->reserved = 0;
  85         desc->addr_lo = (dma_addr_t)buf;
  86 #ifdef CONFIG_DMA_ADDR_T_64BIT
  87         desc->addr_hi = (u64)buf >> 32;
  88 #endif
  89 }
  90
  91 static void sdhci_prepare_adma_table(struct sdhci_host *host,
  92                                      struct mmc_data *data)
  93 {
  94         uint trans_bytes = data->blocksize * data->blocks;
  95         uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
  96         int i = desc_count;
  97         char *buf;
  98
  99         host->desc_slot = 0;
 100
 101         if (data->flags & MMC_DATA_READ)
 102                 buf = data->dest;
 103         else
 104                 buf = (char *)data->src;
 105
 106         while (--i) {
 107                 sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false);
 108                 buf += ADMA_MAX_LEN;
 109                 trans_bytes -= ADMA_MAX_LEN;
 110         }
 111
 112         sdhci_adma_desc(host, buf, trans_bytes, true);
 113
 114         flush_cache((dma_addr_t)host->adma_desc_table,
 115                     ROUND(desc_count * sizeof(struct sdhci_adma_desc),
 116                           ARCH_DMA_MINALIGN));
 117 }
 118 #elif defined(CONFIG_MMC_SDHCI_SDMA)
 119 static void sdhci_prepare_adma_table(struct sdhci_host *host,
 120                                      struct mmc_data *data)
 121 {}
 122 #endif
 123 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 124 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 125                               int *is_aligned, int trans_bytes)
 126 {
 127         unsigned char ctrl;
 128
 129         if (data->flags == MMC_DATA_READ)
 130                 host->start_addr = (dma_addr_t)data->dest;
 131         else
 132                 host->start_addr = (dma_addr_t)data->src;
 133
 134         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 135         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 136         if (host->flags & USE_ADMA64)
 137                 ctrl |= SDHCI_CTRL_ADMA64;
 138         else if (host->flags & USE_ADMA)
 139                 ctrl |= SDHCI_CTRL_ADMA32;
 140         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 141
 142         if (host->flags & USE_SDMA) {
 143                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 144                     (host->start_addr & 0x7) != 0x0) {
 145                         *is_aligned = 0;
 146                         host->start_addr = (unsigned long)host->align_buffer;
 147                         if (data->flags != MMC_DATA_READ)
 148                                 memcpy(host->align_buffer, data->src,
 149                                        trans_bytes);
 150                 }
 151
 152 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 153                 /*
 154                  * Always use this bounce-buffer when
 155                  * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
 156                  */
 157                 *is_aligned = 0;
 158                 host->start_addr = (unsigned long)host->align_buffer;
 159                 if (data->flags != MMC_DATA_READ)
 160                         memcpy(host->align_buffer, data->src, trans_bytes);
 161 #endif
 162                 sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
 163
 164         } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 165                 sdhci_prepare_adma_table(host, data);
 166
 167                 sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS);
 168                 if (host->flags & USE_ADMA64)
 169                         sdhci_writel(host, (u64)host->adma_addr >> 32,
 170                                      SDHCI_ADMA_ADDRESS_HI);
 171         }
 172
 173         flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
 174 }
 175 #else
 176 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 177                               int *is_aligned, int trans_bytes)
 178 {}
 179 #endif
 180 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 181 {
 182         dma_addr_t start_addr = host->start_addr;
 183         unsigned int stat, rdy, mask, timeout, block = 0;
 184         bool transfer_done = false;
 185
 186         timeout = 1000000;
 187         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 188         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 189         do {
 190                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 191                 if (stat & SDHCI_INT_ERROR) {
 192                         pr_debug("%s: Error detected in status(0x%X)!\n",
 193                                  __func__, stat);
 194                         return -EIO;
 195                 }
 196                 if (!transfer_done && (stat & rdy)) {
 197                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 198                                 continue;
 199                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 200                         sdhci_transfer_pio(host, data);
 201                         data->dest += data->blocksize;
 202                         if (++block >= data->blocks) {
 203                                 /* Keep looping until the SDHCI_INT_DATA_END is
 204                                  * cleared, even if we finished sending all the
 205                                  * blocks.
 206                                  */
 207                                 transfer_done = true;
 208                                 continue;
 209                         }
 210                 }
 211                 if ((host->flags & USE_DMA) && !transfer_done &&
 212                     (stat & SDHCI_INT_DMA_END)) {
 213                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 214                         if (host->flags & USE_SDMA) {
 215                                 start_addr &=
 216                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 217                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 218                                 sdhci_writel(host, start_addr,
 219                                              SDHCI_DMA_ADDRESS);
 220                         }
 221                 }
 222                 if (timeout-- > 0)
 223                         udelay(10);
 224                 else {
 225                         printf("%s: Transfer data timeout\n", __func__);
 226                         return -ETIMEDOUT;
 227                 }
 228         } while (!(stat & SDHCI_INT_DATA_END));
 229         return 0;
 230 }
 231
 232 /*
 233  * No command will be sent by driver if card is busy, so driver must wait
 234  * for card ready state.
 235  * Every time when card is busy after timeout then (last) timeout value will be
 236  * increased twice but only if it doesn't exceed global defined maximum.
 237  * Each function call will use last timeout value.
 238  */
 239 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 240 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 241 #define SDHCI_READ_STATUS_TIMEOUT               1000
 242
 243 #ifdef CONFIG_DM_MMC
 244 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 245                               struct mmc_data *data)
 246 {
 247         struct mmc *mmc = mmc_get_mmc_dev(dev);
 248
 249 #else
 250 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 251                               struct mmc_data *data)
 252 {
 253 #endif
 254         struct sdhci_host *host = mmc->priv;
 255         unsigned int stat = 0;
 256         int ret = 0;
 257         int trans_bytes = 0, is_aligned = 1;
 258         u32 mask, flags, mode;
 259         unsigned int time = 0;
 260         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 261         ulong start = get_timer(0);
 262
 263         host->start_addr = 0;
 264         /* Timeout unit - ms */
 265         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 266
 267         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 268
 269         /* We shouldn't wait for data inihibit for stop commands, even
 270            though they might use busy signaling */
 271         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 272             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 273               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 274                 mask &= ~SDHCI_DATA_INHIBIT;
 275
 276         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 277                 if (time >= cmd_timeout) {
 278                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 279                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 280                                 cmd_timeout += cmd_timeout;
 281                                 printf("timeout increasing to: %u ms.\n",
 282                                        cmd_timeout);
 283                         } else {
 284                                 puts("timeout.\n");
 285                                 return -ECOMM;
 286                         }
 287                 }
 288                 time++;
 289                 udelay(1000);
 290         }
 291
 292         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 293
 294         mask = SDHCI_INT_RESPONSE;
 295         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 296              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 297                 mask = SDHCI_INT_DATA_AVAIL;
 298
 299         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 300                 flags = SDHCI_CMD_RESP_NONE;
 301         else if (cmd->resp_type & MMC_RSP_136)
 302                 flags = SDHCI_CMD_RESP_LONG;
 303         else if (cmd->resp_type & MMC_RSP_BUSY) {
 304                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 305                 if (data)
 306                         mask |= SDHCI_INT_DATA_END;
 307         } else
 308                 flags = SDHCI_CMD_RESP_SHORT;
 309
 310         if (cmd->resp_type & MMC_RSP_CRC)
 311                 flags |= SDHCI_CMD_CRC;
 312         if (cmd->resp_type & MMC_RSP_OPCODE)
 313                 flags |= SDHCI_CMD_INDEX;
 314         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 315             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 316                 flags |= SDHCI_CMD_DATA;
 317
 318         /* Set Transfer mode regarding to data flag */
 319         if (data) {
 320                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 321                 mode = SDHCI_TRNS_BLK_CNT_EN;
 322                 trans_bytes = data->blocks * data->blocksize;
 323                 if (data->blocks > 1)
 324                         mode |= SDHCI_TRNS_MULTI;
 325
 326                 if (data->flags == MMC_DATA_READ)
 327                         mode |= SDHCI_TRNS_READ;
 328
 329                 if (host->flags & USE_DMA) {
 330                         mode |= SDHCI_TRNS_DMA;
 331                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 332                 }
 333
 334                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 335                                 data->blocksize),
 336                                 SDHCI_BLOCK_SIZE);
 337                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 338                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 339         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 340                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 341         }
 342
 343         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 344         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 345         start = get_timer(0);
 346         do {
 347                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 348                 if (stat & SDHCI_INT_ERROR)
 349                         break;
 350
 351                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 352                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 353                                 return 0;
 354                         } else {
 355                                 printf("%s: Timeout for status update!\n",
 356                                        __func__);
 357                                 return -ETIMEDOUT;
 358                         }
 359                 }
 360         } while ((stat & mask) != mask);
 361
 362         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 363                 sdhci_cmd_done(host, cmd);
 364                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 365         } else
 366                 ret = -1;
 367
 368         if (!ret && data)
 369                 ret = sdhci_transfer_data(host, data);
 370
 371         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 372                 udelay(1000);
 373
 374         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 375         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 376         if (!ret) {
 377                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 378                                 !is_aligned && (data->flags == MMC_DATA_READ))
 379                         memcpy(data->dest, host->align_buffer, trans_bytes);
 380                 return 0;
 381         }
 382
 383         sdhci_reset(host, SDHCI_RESET_CMD);
 384         sdhci_reset(host, SDHCI_RESET_DATA);
 385         if (stat & SDHCI_INT_TIMEOUT)
 386                 return -ETIMEDOUT;
 387         else
 388                 return -ECOMM;
 389 }
 390
 391 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 392 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 393 {
 394         int err;
 395         struct mmc *mmc = mmc_get_mmc_dev(dev);
 396         struct sdhci_host *host = mmc->priv;
 397
 398         debug("%s\n", __func__);
 399
 400         if (host->ops && host->ops->platform_execute_tuning) {
 401                 err = host->ops->platform_execute_tuning(mmc, opcode);
 402                 if (err)
 403                         return err;
 404                 return 0;
 405         }
 406         return 0;
 407 }
 408 #endif
 409 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 410 {
 411         struct sdhci_host *host = mmc->priv;
 412         unsigned int div, clk = 0, timeout;
 413
 414         /* Wait max 20 ms */
 415         timeout = 200;
 416         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 417                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 418                 if (timeout == 0) {
 419                         printf("%s: Timeout to wait cmd & data inhibit\n",
 420                                __func__);
 421                         return -EBUSY;
 422                 }
 423
 424                 timeout--;
 425                 udelay(100);
 426         }
 427
 428         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 429
 430         if (clock == 0)
 431                 return 0;
 432
 433         if (host->ops && host->ops->set_delay)
 434                 host->ops->set_delay(host);
 435
 436         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 437                 /*
 438                  * Check if the Host Controller supports Programmable Clock
 439                  * Mode.
 440                  */
 441                 if (host->clk_mul) {
 442                         for (div = 1; div <= 1024; div++) {
 443                                 if ((host->max_clk / div) <= clock)
 444                                         break;
 445                         }
 446
 447                         /*
 448                          * Set Programmable Clock Mode in the Clock
 449                          * Control register.
 450                          */
 451                         clk = SDHCI_PROG_CLOCK_MODE;
 452                         div--;
 453                 } else {
 454                         /* Version 3.00 divisors must be a multiple of 2. */
 455                         if (host->max_clk <= clock) {
 456                                 div = 1;
 457                         } else {
 458                                 for (div = 2;
 459                                      div < SDHCI_MAX_DIV_SPEC_300;
 460                                      div += 2) {
 461                                         if ((host->max_clk / div) <= clock)
 462                                                 break;
 463                                 }
 464                         }
 465                         div >>= 1;
 466                 }
 467         } else {
 468                 /* Version 2.00 divisors must be a power of 2. */
 469                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 470                         if ((host->max_clk / div) <= clock)
 471                                 break;
 472                 }
 473                 div >>= 1;
 474         }
 475
 476         if (host->ops && host->ops->set_clock)
 477                 host->ops->set_clock(host, div);
 478
 479         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 480         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 481                 << SDHCI_DIVIDER_HI_SHIFT;
 482         clk |= SDHCI_CLOCK_INT_EN;
 483         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 484
 485         /* Wait max 20 ms */
 486         timeout = 20;
 487         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 488                 & SDHCI_CLOCK_INT_STABLE)) {
 489                 if (timeout == 0) {
 490                         printf("%s: Internal clock never stabilised.\n",
 491                                __func__);
 492                         return -EBUSY;
 493                 }
 494                 timeout--;
 495                 udelay(1000);
 496         }
 497
 498         clk |= SDHCI_CLOCK_CARD_EN;
 499         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 500         return 0;
 501 }
 502
 503 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 504 {
 505         u8 pwr = 0;
 506
 507         if (power != (unsigned short)-1) {
 508                 switch (1 << power) {
 509                 case MMC_VDD_165_195:
 510                         pwr = SDHCI_POWER_180;
 511                         break;
 512                 case MMC_VDD_29_30:
 513                 case MMC_VDD_30_31:
 514                         pwr = SDHCI_POWER_300;
 515                         break;
 516                 case MMC_VDD_32_33:
 517                 case MMC_VDD_33_34:
 518                         pwr = SDHCI_POWER_330;
 519                         break;
 520                 }
 521         }
 522
 523         if (pwr == 0) {
 524                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 525                 return;
 526         }
 527
 528         pwr |= SDHCI_POWER_ON;
 529
 530         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 531 }
 532
 533 void sdhci_set_uhs_timing(struct sdhci_host *host)
 534 {
 535         struct mmc *mmc = (struct mmc *)host->mmc;
 536         u32 reg;
 537
 538         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 539         reg &= ~SDHCI_CTRL_UHS_MASK;
 540
 541         switch (mmc->selected_mode) {
 542         case UHS_SDR50:
 543         case MMC_HS_52:
 544                 reg |= SDHCI_CTRL_UHS_SDR50;
 545                 break;
 546         case UHS_DDR50:
 547         case MMC_DDR_52:
 548                 reg |= SDHCI_CTRL_UHS_DDR50;
 549                 break;
 550         case UHS_SDR104:
 551         case MMC_HS_200:
 552                 reg |= SDHCI_CTRL_UHS_SDR104;
 553                 break;
 554         default:
 555                 reg |= SDHCI_CTRL_UHS_SDR12;
 556         }
 557
 558         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 559 }
 560
 561 #ifdef CONFIG_DM_MMC
 562 static int sdhci_set_ios(struct udevice *dev)
 563 {
 564         struct mmc *mmc = mmc_get_mmc_dev(dev);
 565 #else
 566 static int sdhci_set_ios(struct mmc *mmc)
 567 {
 568 #endif
 569         u32 ctrl;
 570         struct sdhci_host *host = mmc->priv;
 571
 572         if (host->ops && host->ops->set_control_reg)
 573                 host->ops->set_control_reg(host);
 574
 575         if (mmc->clock != host->clock)
 576                 sdhci_set_clock(mmc, mmc->clock);
 577
 578         if (mmc->clk_disable)
 579                 sdhci_set_clock(mmc, 0);
 580
 581         /* Set bus width */
 582         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 583         if (mmc->bus_width == 8) {
 584                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 585                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 586                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 587                         ctrl |= SDHCI_CTRL_8BITBUS;
 588         } else {
 589                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 590                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 591                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 592                 if (mmc->bus_width == 4)
 593                         ctrl |= SDHCI_CTRL_4BITBUS;
 594                 else
 595                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 596         }
 597
 598         if (mmc->clock > 26000000)
 599                 ctrl |= SDHCI_CTRL_HISPD;
 600         else
 601                 ctrl &= ~SDHCI_CTRL_HISPD;
 602
 603         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 604             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 605                 ctrl &= ~SDHCI_CTRL_HISPD;
 606
 607         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 608
 609         /* If available, call the driver specific "post" set_ios() function */
 610         if (host->ops && host->ops->set_ios_post)
 611                 return host->ops->set_ios_post(host);
 612
 613         return 0;
 614 }
 615
 616 static int sdhci_init(struct mmc *mmc)
 617 {
 618         struct sdhci_host *host = mmc->priv;
 619 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 620         struct udevice *dev = mmc->dev;
 621
 622         gpio_request_by_name(dev, "cd-gpios", 0,
 623                              &host->cd_gpio, GPIOD_IS_IN);
 624 #endif
 625
 626         sdhci_reset(host, SDHCI_RESET_ALL);
 627
 628 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 629         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 630 #else
 631         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 632                 host->align_buffer = memalign(8, 512 * 1024);
 633                 if (!host->align_buffer) {
 634                         printf("%s: Aligned buffer alloc failed!!!\n",
 635                                __func__);
 636                         return -ENOMEM;
 637                 }
 638         }
 639 #endif
 640
 641         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 642
 643         if (host->ops && host->ops->get_cd)
 644                 host->ops->get_cd(host);
 645
 646         /* Enable only interrupts served by the SD controller */
 647         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 648                      SDHCI_INT_ENABLE);
 649         /* Mask all sdhci interrupt sources */
 650         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 651
 652         return 0;
 653 }
 654
 655 #ifdef CONFIG_DM_MMC
 656 int sdhci_probe(struct udevice *dev)
 657 {
 658         struct mmc *mmc = mmc_get_mmc_dev(dev);
 659
 660         return sdhci_init(mmc);
 661 }
 662
 663 static int sdhci_get_cd(struct udevice *dev)
 664 {
 665         struct mmc *mmc = mmc_get_mmc_dev(dev);
 666         struct sdhci_host *host = mmc->priv;
 667         int value;
 668
 669         /* If nonremovable, assume that the card is always present. */
 670         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 671                 return 1;
 672         /* If polling, assume that the card is always present. */
 673         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 674                 return 1;
 675
 676 #if CONFIG_IS_ENABLED(DM_GPIO)
 677         value = dm_gpio_get_value(&host->cd_gpio);
 678         if (value >= 0) {
 679                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 680                         return !value;
 681                 else
 682                         return value;
 683         }
 684 #endif
 685         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 686                    SDHCI_CARD_PRESENT);
 687         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 688                 return !value;
 689         else
 690                 return value;
 691 }
 692
 693 const struct dm_mmc_ops sdhci_ops = {
 694         .send_cmd       = sdhci_send_command,
 695         .set_ios        = sdhci_set_ios,
 696         .get_cd         = sdhci_get_cd,
 697 #ifdef MMC_SUPPORTS_TUNING
 698         .execute_tuning = sdhci_execute_tuning,
 699 #endif
 700 };
 701 #else
 702 static const struct mmc_ops sdhci_ops = {
 703         .send_cmd       = sdhci_send_command,
 704         .set_ios        = sdhci_set_ios,
 705         .init           = sdhci_init,
 706 };
 707 #endif
 708
 709 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 710                 u32 f_max, u32 f_min)
 711 {
 712         u32 caps, caps_1 = 0;
 713 #if CONFIG_IS_ENABLED(DM_MMC)
 714         u64 dt_caps, dt_caps_mask;
 715
 716         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 717                                             "sdhci-caps-mask", 0);
 718         dt_caps = dev_read_u64_default(host->mmc->dev,
 719                                        "sdhci-caps", 0);
 720         caps = ~(u32)dt_caps_mask &
 721                sdhci_readl(host, SDHCI_CAPABILITIES);
 722         caps |= (u32)dt_caps;
 723 #else
 724         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 725 #endif
 726         debug("%s, caps: 0x%x\n", __func__, caps);
 727
 728 #ifdef CONFIG_MMC_SDHCI_SDMA
 729         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 730                 printf("%s: Your controller doesn't support SDMA!!\n",
 731                        __func__);
 732                 return -EINVAL;
 733         }
 734
 735         host->flags |= USE_SDMA;
 736 #endif
 737 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 738         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 739                 printf("%s: Your controller doesn't support SDMA!!\n",
 740                        __func__);
 741                 return -EINVAL;
 742         }
 743         host->adma_desc_table = (struct sdhci_adma_desc *)
 744                                 memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
 745
 746         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 747 #ifdef CONFIG_DMA_ADDR_T_64BIT
 748         host->flags |= USE_ADMA64;
 749 #else
 750         host->flags |= USE_ADMA;
 751 #endif
 752 #endif
 753         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 754                 host->version =
 755                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 756         else
 757                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 758
 759         cfg->name = host->name;
 760 #ifndef CONFIG_DM_MMC
 761         cfg->ops = &sdhci_ops;
 762 #endif
 763
 764         /* Check whether the clock multiplier is supported or not */
 765         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 766 #if CONFIG_IS_ENABLED(DM_MMC)
 767                 caps_1 = ~(u32)(dt_caps_mask >> 32) &
 768                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 769                 caps_1 |= (u32)(dt_caps >> 32);
 770 #else
 771                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 772 #endif
 773                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 774                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 775                                 SDHCI_CLOCK_MUL_SHIFT;
 776         }
 777
 778         if (host->max_clk == 0) {
 779                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 780                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 781                                 SDHCI_CLOCK_BASE_SHIFT;
 782                 else
 783                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 784                                 SDHCI_CLOCK_BASE_SHIFT;
 785                 host->max_clk *= 1000000;
 786                 if (host->clk_mul)
 787                         host->max_clk *= host->clk_mul;
 788         }
 789         if (host->max_clk == 0) {
 790                 printf("%s: Hardware doesn't specify base clock frequency\n",
 791                        __func__);
 792                 return -EINVAL;
 793         }
 794         if (f_max && (f_max < host->max_clk))
 795                 cfg->f_max = f_max;
 796         else
 797                 cfg->f_max = host->max_clk;
 798         if (f_min)
 799                 cfg->f_min = f_min;
 800         else {
 801                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 802                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 803                 else
 804                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 805         }
 806         cfg->voltages = 0;
 807         if (caps & SDHCI_CAN_VDD_330)
 808                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 809         if (caps & SDHCI_CAN_VDD_300)
 810                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 811         if (caps & SDHCI_CAN_VDD_180)
 812                 cfg->voltages |= MMC_VDD_165_195;
 813
 814         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 815                 cfg->voltages |= host->voltages;
 816
 817         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 818
 819         /* Since Host Controller Version3.0 */
 820         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 821                 if (!(caps & SDHCI_CAN_DO_8BIT))
 822                         cfg->host_caps &= ~MMC_MODE_8BIT;
 823         }
 824
 825         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 826                 cfg->host_caps &= ~MMC_MODE_HS;
 827                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 828         }
 829
 830         if (!(cfg->voltages & MMC_VDD_165_195) ||
 831             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 832                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 833                             SDHCI_SUPPORT_DDR50);
 834
 835         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 836                       SDHCI_SUPPORT_DDR50))
 837                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 838
 839         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 840                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 841                 /*
 842                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 843                  * field can be promoted to support HS200.
 844                  */
 845                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 846         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 847                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 848         }
 849
 850         if (caps_1 & SDHCI_SUPPORT_DDR50)
 851                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 852
 853         if (host->host_caps)
 854                 cfg->host_caps |= host->host_caps;
 855
 856         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 857
 858         return 0;
 859 }
 860
 861 #ifdef CONFIG_BLK
 862 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 863 {
 864         return mmc_bind(dev, mmc, cfg);
 865 }
 866 #else
 867 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 868 {
 869         int ret;
 870
 871         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 872         if (ret)
 873                 return ret;
 874
 875         host->mmc = mmc_create(&host->cfg, host);
 876         if (host->mmc == NULL) {
 877                 printf("%s: mmc create fail!\n", __func__);
 878                 return -ENOMEM;
 879         }
 880
 881         return 0;
 882 }
 883 #endif