1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
18 #include <asm/cache.h>
19 #include <linux/bitops.h>
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
24 static void sdhci_reset(struct sdhci_host *host, u8 mask)
26 unsigned long timeout;
30 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
31 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
33 printf("%s: Reset 0x%x never completed.\n",
42 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
45 if (cmd->resp_type & MMC_RSP_136) {
46 /* CRC is stripped so we need to do some shifting. */
47 for (i = 0; i < 4; i++) {
48 cmd->response[i] = sdhci_readl(host,
49 SDHCI_RESPONSE + (3-i)*4) << 8;
51 cmd->response[i] |= sdhci_readb(host,
52 SDHCI_RESPONSE + (3-i)*4-1);
55 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
59 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
63 for (i = 0; i < data->blocksize; i += 4) {
64 offs = data->dest + i;
65 if (data->flags == MMC_DATA_READ)
66 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
68 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
72 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
73 static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
76 struct sdhci_adma_desc *desc;
79 desc = &host->adma_desc_table[host->desc_slot];
81 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
85 attr |= ADMA_DESC_ATTR_END;
90 desc->addr_lo = lower_32_bits(dma_addr);
91 #ifdef CONFIG_DMA_ADDR_T_64BIT
92 desc->addr_hi = upper_32_bits(dma_addr);
96 static void sdhci_prepare_adma_table(struct sdhci_host *host,
97 struct mmc_data *data)
99 uint trans_bytes = data->blocksize * data->blocks;
100 uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
102 dma_addr_t dma_addr = host->start_addr;
107 sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
108 dma_addr += ADMA_MAX_LEN;
109 trans_bytes -= ADMA_MAX_LEN;
112 sdhci_adma_desc(host, dma_addr, trans_bytes, true);
114 flush_cache((dma_addr_t)host->adma_desc_table,
115 ROUND(desc_count * sizeof(struct sdhci_adma_desc),
118 #elif defined(CONFIG_MMC_SDHCI_SDMA)
119 static void sdhci_prepare_adma_table(struct sdhci_host *host,
120 struct mmc_data *data)
123 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
124 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
125 int *is_aligned, int trans_bytes)
130 if (data->flags == MMC_DATA_READ)
133 buf = (void *)data->src;
135 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
136 ctrl &= ~SDHCI_CTRL_DMA_MASK;
137 if (host->flags & USE_ADMA64)
138 ctrl |= SDHCI_CTRL_ADMA64;
139 else if (host->flags & USE_ADMA)
140 ctrl |= SDHCI_CTRL_ADMA32;
141 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
143 if (host->flags & USE_SDMA &&
144 (host->force_align_buffer ||
145 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
146 ((unsigned long)buf & 0x7) != 0x0))) {
148 if (data->flags != MMC_DATA_READ)
149 memcpy(host->align_buffer, buf, trans_bytes);
150 buf = host->align_buffer;
153 host->start_addr = dma_map_single(buf, trans_bytes,
154 mmc_get_dma_dir(data));
156 if (host->flags & USE_SDMA) {
157 sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
159 } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
160 sdhci_prepare_adma_table(host, data);
162 sdhci_writel(host, lower_32_bits(host->adma_addr),
164 if (host->flags & USE_ADMA64)
165 sdhci_writel(host, upper_32_bits(host->adma_addr),
166 SDHCI_ADMA_ADDRESS_HI);
170 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
171 int *is_aligned, int trans_bytes)
174 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
176 dma_addr_t start_addr = host->start_addr;
177 unsigned int stat, rdy, mask, timeout, block = 0;
178 bool transfer_done = false;
181 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
182 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
184 stat = sdhci_readl(host, SDHCI_INT_STATUS);
185 if (stat & SDHCI_INT_ERROR) {
186 pr_debug("%s: Error detected in status(0x%X)!\n",
190 if (!transfer_done && (stat & rdy)) {
191 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
193 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
194 sdhci_transfer_pio(host, data);
195 data->dest += data->blocksize;
196 if (++block >= data->blocks) {
197 /* Keep looping until the SDHCI_INT_DATA_END is
198 * cleared, even if we finished sending all the
201 transfer_done = true;
205 if ((host->flags & USE_DMA) && !transfer_done &&
206 (stat & SDHCI_INT_DMA_END)) {
207 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
208 if (host->flags & USE_SDMA) {
210 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
211 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
212 sdhci_writel(host, phys_to_bus((ulong)start_addr),
219 printf("%s: Transfer data timeout\n", __func__);
222 } while (!(stat & SDHCI_INT_DATA_END));
224 dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
225 mmc_get_dma_dir(data));
231 * No command will be sent by driver if card is busy, so driver must wait
232 * for card ready state.
233 * Every time when card is busy after timeout then (last) timeout value will be
234 * increased twice but only if it doesn't exceed global defined maximum.
235 * Each function call will use last timeout value.
237 #define SDHCI_CMD_MAX_TIMEOUT 3200
238 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
239 #define SDHCI_READ_STATUS_TIMEOUT 1000
242 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
243 struct mmc_data *data)
245 struct mmc *mmc = mmc_get_mmc_dev(dev);
248 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
249 struct mmc_data *data)
252 struct sdhci_host *host = mmc->priv;
253 unsigned int stat = 0;
255 int trans_bytes = 0, is_aligned = 1;
256 u32 mask, flags, mode;
257 unsigned int time = 0;
258 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
259 ulong start = get_timer(0);
261 host->start_addr = 0;
262 /* Timeout unit - ms */
263 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
265 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
267 /* We shouldn't wait for data inihibit for stop commands, even
268 though they might use busy signaling */
269 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
270 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
271 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
272 mask &= ~SDHCI_DATA_INHIBIT;
274 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
275 if (time >= cmd_timeout) {
276 printf("%s: MMC: %d busy ", __func__, mmc_dev);
277 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
278 cmd_timeout += cmd_timeout;
279 printf("timeout increasing to: %u ms.\n",
290 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
292 mask = SDHCI_INT_RESPONSE;
293 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
294 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
295 mask = SDHCI_INT_DATA_AVAIL;
297 if (!(cmd->resp_type & MMC_RSP_PRESENT))
298 flags = SDHCI_CMD_RESP_NONE;
299 else if (cmd->resp_type & MMC_RSP_136)
300 flags = SDHCI_CMD_RESP_LONG;
301 else if (cmd->resp_type & MMC_RSP_BUSY) {
302 flags = SDHCI_CMD_RESP_SHORT_BUSY;
304 mask |= SDHCI_INT_DATA_END;
306 flags = SDHCI_CMD_RESP_SHORT;
308 if (cmd->resp_type & MMC_RSP_CRC)
309 flags |= SDHCI_CMD_CRC;
310 if (cmd->resp_type & MMC_RSP_OPCODE)
311 flags |= SDHCI_CMD_INDEX;
312 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
313 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
314 flags |= SDHCI_CMD_DATA;
316 /* Set Transfer mode regarding to data flag */
318 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
319 mode = SDHCI_TRNS_BLK_CNT_EN;
320 trans_bytes = data->blocks * data->blocksize;
321 if (data->blocks > 1)
322 mode |= SDHCI_TRNS_MULTI;
324 if (data->flags == MMC_DATA_READ)
325 mode |= SDHCI_TRNS_READ;
327 if (host->flags & USE_DMA) {
328 mode |= SDHCI_TRNS_DMA;
329 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
332 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
335 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
336 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
337 } else if (cmd->resp_type & MMC_RSP_BUSY) {
338 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
341 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
342 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
343 start = get_timer(0);
345 stat = sdhci_readl(host, SDHCI_INT_STATUS);
346 if (stat & SDHCI_INT_ERROR)
349 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
350 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
353 printf("%s: Timeout for status update!\n",
358 } while ((stat & mask) != mask);
360 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
361 sdhci_cmd_done(host, cmd);
362 sdhci_writel(host, mask, SDHCI_INT_STATUS);
367 ret = sdhci_transfer_data(host, data);
369 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
372 stat = sdhci_readl(host, SDHCI_INT_STATUS);
373 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
375 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
376 !is_aligned && (data->flags == MMC_DATA_READ))
377 memcpy(data->dest, host->align_buffer, trans_bytes);
381 sdhci_reset(host, SDHCI_RESET_CMD);
382 sdhci_reset(host, SDHCI_RESET_DATA);
383 if (stat & SDHCI_INT_TIMEOUT)
389 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
390 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
393 struct mmc *mmc = mmc_get_mmc_dev(dev);
394 struct sdhci_host *host = mmc->priv;
396 debug("%s\n", __func__);
398 if (host->ops && host->ops->platform_execute_tuning) {
399 err = host->ops->platform_execute_tuning(mmc, opcode);
407 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
409 struct sdhci_host *host = mmc->priv;
410 unsigned int div, clk = 0, timeout;
414 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
415 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
417 printf("%s: Timeout to wait cmd & data inhibit\n",
426 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
431 if (host->ops && host->ops->set_delay)
432 host->ops->set_delay(host);
434 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
436 * Check if the Host Controller supports Programmable Clock
440 for (div = 1; div <= 1024; div++) {
441 if ((host->max_clk / div) <= clock)
446 * Set Programmable Clock Mode in the Clock
449 clk = SDHCI_PROG_CLOCK_MODE;
452 /* Version 3.00 divisors must be a multiple of 2. */
453 if (host->max_clk <= clock) {
457 div < SDHCI_MAX_DIV_SPEC_300;
459 if ((host->max_clk / div) <= clock)
466 /* Version 2.00 divisors must be a power of 2. */
467 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
468 if ((host->max_clk / div) <= clock)
474 if (host->ops && host->ops->set_clock)
475 host->ops->set_clock(host, div);
477 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
478 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
479 << SDHCI_DIVIDER_HI_SHIFT;
480 clk |= SDHCI_CLOCK_INT_EN;
481 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
485 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
486 & SDHCI_CLOCK_INT_STABLE)) {
488 printf("%s: Internal clock never stabilised.\n",
496 clk |= SDHCI_CLOCK_CARD_EN;
497 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
501 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
505 if (power != (unsigned short)-1) {
506 switch (1 << power) {
507 case MMC_VDD_165_195:
508 pwr = SDHCI_POWER_180;
512 pwr = SDHCI_POWER_300;
516 pwr = SDHCI_POWER_330;
522 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
526 pwr |= SDHCI_POWER_ON;
528 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
531 void sdhci_set_uhs_timing(struct sdhci_host *host)
533 struct mmc *mmc = host->mmc;
536 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
537 reg &= ~SDHCI_CTRL_UHS_MASK;
539 switch (mmc->selected_mode) {
542 reg |= SDHCI_CTRL_UHS_SDR50;
546 reg |= SDHCI_CTRL_UHS_DDR50;
550 reg |= SDHCI_CTRL_UHS_SDR104;
553 reg |= SDHCI_CTRL_UHS_SDR12;
556 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
560 static int sdhci_set_ios(struct udevice *dev)
562 struct mmc *mmc = mmc_get_mmc_dev(dev);
564 static int sdhci_set_ios(struct mmc *mmc)
568 struct sdhci_host *host = mmc->priv;
569 bool no_hispd_bit = false;
571 if (host->ops && host->ops->set_control_reg)
572 host->ops->set_control_reg(host);
574 if (mmc->clock != host->clock)
575 sdhci_set_clock(mmc, mmc->clock);
577 if (mmc->clk_disable)
578 sdhci_set_clock(mmc, 0);
581 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
582 if (mmc->bus_width == 8) {
583 ctrl &= ~SDHCI_CTRL_4BITBUS;
584 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
585 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
586 ctrl |= SDHCI_CTRL_8BITBUS;
588 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
589 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
590 ctrl &= ~SDHCI_CTRL_8BITBUS;
591 if (mmc->bus_width == 4)
592 ctrl |= SDHCI_CTRL_4BITBUS;
594 ctrl &= ~SDHCI_CTRL_4BITBUS;
597 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
598 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
599 ctrl &= ~SDHCI_CTRL_HISPD;
604 if (mmc->selected_mode == MMC_HS ||
605 mmc->selected_mode == SD_HS ||
606 mmc->selected_mode == MMC_DDR_52 ||
607 mmc->selected_mode == MMC_HS_200 ||
608 mmc->selected_mode == MMC_HS_400 ||
609 mmc->selected_mode == UHS_SDR25 ||
610 mmc->selected_mode == UHS_SDR50 ||
611 mmc->selected_mode == UHS_SDR104 ||
612 mmc->selected_mode == UHS_DDR50)
613 ctrl |= SDHCI_CTRL_HISPD;
615 ctrl &= ~SDHCI_CTRL_HISPD;
618 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
620 /* If available, call the driver specific "post" set_ios() function */
621 if (host->ops && host->ops->set_ios_post)
622 return host->ops->set_ios_post(host);
627 static int sdhci_init(struct mmc *mmc)
629 struct sdhci_host *host = mmc->priv;
630 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
631 struct udevice *dev = mmc->dev;
633 gpio_request_by_name(dev, "cd-gpios", 0,
634 &host->cd_gpio, GPIOD_IS_IN);
637 sdhci_reset(host, SDHCI_RESET_ALL);
639 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
640 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
642 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
645 host->force_align_buffer = true;
647 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
648 host->align_buffer = memalign(8, 512 * 1024);
649 if (!host->align_buffer) {
650 printf("%s: Aligned buffer alloc failed!!!\n",
657 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
659 if (host->ops && host->ops->get_cd)
660 host->ops->get_cd(host);
662 /* Enable only interrupts served by the SD controller */
663 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
665 /* Mask all sdhci interrupt sources */
666 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
672 int sdhci_probe(struct udevice *dev)
674 struct mmc *mmc = mmc_get_mmc_dev(dev);
676 return sdhci_init(mmc);
679 static int sdhci_deferred_probe(struct udevice *dev)
682 struct mmc *mmc = mmc_get_mmc_dev(dev);
683 struct sdhci_host *host = mmc->priv;
685 if (host->ops && host->ops->deferred_probe) {
686 err = host->ops->deferred_probe(host);
693 static int sdhci_get_cd(struct udevice *dev)
695 struct mmc *mmc = mmc_get_mmc_dev(dev);
696 struct sdhci_host *host = mmc->priv;
699 /* If nonremovable, assume that the card is always present. */
700 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
702 /* If polling, assume that the card is always present. */
703 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
706 #if CONFIG_IS_ENABLED(DM_GPIO)
707 value = dm_gpio_get_value(&host->cd_gpio);
709 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
715 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
717 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
723 const struct dm_mmc_ops sdhci_ops = {
724 .send_cmd = sdhci_send_command,
725 .set_ios = sdhci_set_ios,
726 .get_cd = sdhci_get_cd,
727 .deferred_probe = sdhci_deferred_probe,
728 #ifdef MMC_SUPPORTS_TUNING
729 .execute_tuning = sdhci_execute_tuning,
733 static const struct mmc_ops sdhci_ops = {
734 .send_cmd = sdhci_send_command,
735 .set_ios = sdhci_set_ios,
740 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
741 u32 f_max, u32 f_min)
743 u32 caps, caps_1 = 0;
744 #if CONFIG_IS_ENABLED(DM_MMC)
745 u64 dt_caps, dt_caps_mask;
747 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
748 "sdhci-caps-mask", 0);
749 dt_caps = dev_read_u64_default(host->mmc->dev,
751 caps = ~(u32)dt_caps_mask &
752 sdhci_readl(host, SDHCI_CAPABILITIES);
753 caps |= (u32)dt_caps;
755 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
757 debug("%s, caps: 0x%x\n", __func__, caps);
759 #ifdef CONFIG_MMC_SDHCI_SDMA
760 if ((caps & SDHCI_CAN_DO_SDMA)) {
761 host->flags |= USE_SDMA;
763 debug("%s: Your controller doesn't support SDMA!!\n",
767 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
768 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
769 printf("%s: Your controller doesn't support SDMA!!\n",
773 host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
775 host->adma_addr = (dma_addr_t)host->adma_desc_table;
776 #ifdef CONFIG_DMA_ADDR_T_64BIT
777 host->flags |= USE_ADMA64;
779 host->flags |= USE_ADMA;
782 if (host->quirks & SDHCI_QUIRK_REG32_RW)
784 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
786 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
788 cfg->name = host->name;
789 #ifndef CONFIG_DM_MMC
790 cfg->ops = &sdhci_ops;
793 /* Check whether the clock multiplier is supported or not */
794 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
795 #if CONFIG_IS_ENABLED(DM_MMC)
796 caps_1 = ~(u32)(dt_caps_mask >> 32) &
797 sdhci_readl(host, SDHCI_CAPABILITIES_1);
798 caps_1 |= (u32)(dt_caps >> 32);
800 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
802 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
803 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
804 SDHCI_CLOCK_MUL_SHIFT;
807 if (host->max_clk == 0) {
808 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
809 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
810 SDHCI_CLOCK_BASE_SHIFT;
812 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
813 SDHCI_CLOCK_BASE_SHIFT;
814 host->max_clk *= 1000000;
816 host->max_clk *= host->clk_mul;
818 if (host->max_clk == 0) {
819 printf("%s: Hardware doesn't specify base clock frequency\n",
823 if (f_max && (f_max < host->max_clk))
826 cfg->f_max = host->max_clk;
830 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
831 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
833 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
836 if (caps & SDHCI_CAN_VDD_330)
837 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
838 if (caps & SDHCI_CAN_VDD_300)
839 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
840 if (caps & SDHCI_CAN_VDD_180)
841 cfg->voltages |= MMC_VDD_165_195;
843 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
844 cfg->voltages |= host->voltages;
846 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
848 /* Since Host Controller Version3.0 */
849 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
850 if (!(caps & SDHCI_CAN_DO_8BIT))
851 cfg->host_caps &= ~MMC_MODE_8BIT;
854 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
855 cfg->host_caps &= ~MMC_MODE_HS;
856 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
859 if (!(cfg->voltages & MMC_VDD_165_195))
860 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
861 SDHCI_SUPPORT_DDR50);
863 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
864 SDHCI_SUPPORT_DDR50))
865 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
867 if (caps_1 & SDHCI_SUPPORT_SDR104) {
868 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
870 * SD3.0: SDR104 is supported so (for eMMC) the caps2
871 * field can be promoted to support HS200.
873 cfg->host_caps |= MMC_CAP(MMC_HS_200);
874 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
875 cfg->host_caps |= MMC_CAP(UHS_SDR50);
878 if (caps_1 & SDHCI_SUPPORT_DDR50)
879 cfg->host_caps |= MMC_CAP(UHS_DDR50);
882 cfg->host_caps |= host->host_caps;
884 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
890 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
892 return mmc_bind(dev, mmc, cfg);
895 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
899 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
903 host->mmc = mmc_create(&host->cfg, host);
904 if (host->mmc == NULL) {
905 printf("%s: mmc create fail!\n", __func__);