drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <sdhci.h>
  17 #include <dm.h>
  18
  19 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  20 {
  21         unsigned long timeout;
  22
  23         /* Wait max 100 ms */
  24         timeout = 100;
  25         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  26         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  27                 if (timeout == 0) {
  28                         printf("%s: Reset 0x%x never completed.\n",
  29                                __func__, (int)mask);
  30                         return;
  31                 }
  32                 timeout--;
  33                 udelay(1000);
  34         }
  35 }
  36
  37 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  38 {
  39         int i;
  40         if (cmd->resp_type & MMC_RSP_136) {
  41                 /* CRC is stripped so we need to do some shifting. */
  42                 for (i = 0; i < 4; i++) {
  43                         cmd->response[i] = sdhci_readl(host,
  44                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  45                         if (i != 3)
  46                                 cmd->response[i] |= sdhci_readb(host,
  47                                                 SDHCI_RESPONSE + (3-i)*4-1);
  48                 }
  49         } else {
  50                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  51         }
  52 }
  53
  54 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  55 {
  56         int i;
  57         char *offs;
  58         for (i = 0; i < data->blocksize; i += 4) {
  59                 offs = data->dest + i;
  60                 if (data->flags == MMC_DATA_READ)
  61                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  62                 else
  63                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  64         }
  65 }
  66
  67 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  68 static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len,
  69                             bool end)
  70 {
  71         struct sdhci_adma_desc *desc;
  72         u8 attr;
  73
  74         desc = &host->adma_desc_table[host->desc_slot];
  75
  76         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  77         if (!end)
  78                 host->desc_slot++;
  79         else
  80                 attr |= ADMA_DESC_ATTR_END;
  81
  82         desc->attr = attr;
  83         desc->len = len;
  84         desc->reserved = 0;
  85         desc->addr_lo = (dma_addr_t)buf;
  86 #ifdef CONFIG_DMA_ADDR_T_64BIT
  87         desc->addr_hi = (u64)buf >> 32;
  88 #endif
  89 }
  90
  91 static void sdhci_prepare_adma_table(struct sdhci_host *host,
  92                                      struct mmc_data *data)
  93 {
  94         uint trans_bytes = data->blocksize * data->blocks;
  95         uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
  96         int i = desc_count;
  97         char *buf;
  98
  99         host->desc_slot = 0;
 100
 101         if (data->flags & MMC_DATA_READ)
 102                 buf = data->dest;
 103         else
 104                 buf = (char *)data->src;
 105
 106         while (--i) {
 107                 sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false);
 108                 buf += ADMA_MAX_LEN;
 109                 trans_bytes -= ADMA_MAX_LEN;
 110         }
 111
 112         sdhci_adma_desc(host, buf, trans_bytes, true);
 113
 114         flush_cache((dma_addr_t)host->adma_desc_table,
 115                     ROUND(desc_count * sizeof(struct sdhci_adma_desc),
 116                           ARCH_DMA_MINALIGN));
 117 }
 118 #elif defined(CONFIG_MMC_SDHCI_SDMA)
 119 static void sdhci_prepare_adma_table(struct sdhci_host *host,
 120                                      struct mmc_data *data)
 121 {}
 122 #endif
 123 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 124 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 125                               int *is_aligned, int trans_bytes)
 126 {
 127         unsigned char ctrl;
 128
 129         if (data->flags == MMC_DATA_READ)
 130                 host->start_addr = (dma_addr_t)data->dest;
 131         else
 132                 host->start_addr = (dma_addr_t)data->src;
 133
 134         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 135         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 136         if (host->flags & USE_ADMA64)
 137                 ctrl |= SDHCI_CTRL_ADMA64;
 138         else if (host->flags & USE_ADMA)
 139                 ctrl |= SDHCI_CTRL_ADMA32;
 140         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 141
 142         if (host->flags & USE_SDMA) {
 143                 if (host->force_align_buffer ||
 144                     (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
 145                      (host->start_addr & 0x7) != 0x0)) {
 146                         *is_aligned = 0;
 147                         host->start_addr = (unsigned long)host->align_buffer;
 148                         if (data->flags != MMC_DATA_READ)
 149                                 memcpy(host->align_buffer, data->src,
 150                                        trans_bytes);
 151                 }
 152                 sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
 153         } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 154                 sdhci_prepare_adma_table(host, data);
 155
 156                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 157                              SDHCI_ADMA_ADDRESS);
 158                 if (host->flags & USE_ADMA64)
 159                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 160                                      SDHCI_ADMA_ADDRESS_HI);
 161         }
 162
 163         flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
 164 }
 165 #else
 166 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 167                               int *is_aligned, int trans_bytes)
 168 {}
 169 #endif
 170 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 171 {
 172         dma_addr_t start_addr = host->start_addr;
 173         unsigned int stat, rdy, mask, timeout, block = 0;
 174         bool transfer_done = false;
 175
 176         timeout = 1000000;
 177         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 178         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 179         do {
 180                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 181                 if (stat & SDHCI_INT_ERROR) {
 182                         pr_debug("%s: Error detected in status(0x%X)!\n",
 183                                  __func__, stat);
 184                         return -EIO;
 185                 }
 186                 if (!transfer_done && (stat & rdy)) {
 187                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 188                                 continue;
 189                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 190                         sdhci_transfer_pio(host, data);
 191                         data->dest += data->blocksize;
 192                         if (++block >= data->blocks) {
 193                                 /* Keep looping until the SDHCI_INT_DATA_END is
 194                                  * cleared, even if we finished sending all the
 195                                  * blocks.
 196                                  */
 197                                 transfer_done = true;
 198                                 continue;
 199                         }
 200                 }
 201                 if ((host->flags & USE_DMA) && !transfer_done &&
 202                     (stat & SDHCI_INT_DMA_END)) {
 203                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 204                         if (host->flags & USE_SDMA) {
 205                                 start_addr &=
 206                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 207                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 208                                 sdhci_writel(host, start_addr,
 209                                              SDHCI_DMA_ADDRESS);
 210                         }
 211                 }
 212                 if (timeout-- > 0)
 213                         udelay(10);
 214                 else {
 215                         printf("%s: Transfer data timeout\n", __func__);
 216                         return -ETIMEDOUT;
 217                 }
 218         } while (!(stat & SDHCI_INT_DATA_END));
 219         return 0;
 220 }
 221
 222 /*
 223  * No command will be sent by driver if card is busy, so driver must wait
 224  * for card ready state.
 225  * Every time when card is busy after timeout then (last) timeout value will be
 226  * increased twice but only if it doesn't exceed global defined maximum.
 227  * Each function call will use last timeout value.
 228  */
 229 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 230 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 231 #define SDHCI_READ_STATUS_TIMEOUT               1000
 232
 233 #ifdef CONFIG_DM_MMC
 234 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 235                               struct mmc_data *data)
 236 {
 237         struct mmc *mmc = mmc_get_mmc_dev(dev);
 238
 239 #else
 240 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 241                               struct mmc_data *data)
 242 {
 243 #endif
 244         struct sdhci_host *host = mmc->priv;
 245         unsigned int stat = 0;
 246         int ret = 0;
 247         int trans_bytes = 0, is_aligned = 1;
 248         u32 mask, flags, mode;
 249         unsigned int time = 0;
 250         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 251         ulong start = get_timer(0);
 252
 253         host->start_addr = 0;
 254         /* Timeout unit - ms */
 255         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 256
 257         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 258
 259         /* We shouldn't wait for data inihibit for stop commands, even
 260            though they might use busy signaling */
 261         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 262             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 263               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 264                 mask &= ~SDHCI_DATA_INHIBIT;
 265
 266         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 267                 if (time >= cmd_timeout) {
 268                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 269                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 270                                 cmd_timeout += cmd_timeout;
 271                                 printf("timeout increasing to: %u ms.\n",
 272                                        cmd_timeout);
 273                         } else {
 274                                 puts("timeout.\n");
 275                                 return -ECOMM;
 276                         }
 277                 }
 278                 time++;
 279                 udelay(1000);
 280         }
 281
 282         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 283
 284         mask = SDHCI_INT_RESPONSE;
 285         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 286              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 287                 mask = SDHCI_INT_DATA_AVAIL;
 288
 289         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 290                 flags = SDHCI_CMD_RESP_NONE;
 291         else if (cmd->resp_type & MMC_RSP_136)
 292                 flags = SDHCI_CMD_RESP_LONG;
 293         else if (cmd->resp_type & MMC_RSP_BUSY) {
 294                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 295                 if (data)
 296                         mask |= SDHCI_INT_DATA_END;
 297         } else
 298                 flags = SDHCI_CMD_RESP_SHORT;
 299
 300         if (cmd->resp_type & MMC_RSP_CRC)
 301                 flags |= SDHCI_CMD_CRC;
 302         if (cmd->resp_type & MMC_RSP_OPCODE)
 303                 flags |= SDHCI_CMD_INDEX;
 304         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 305             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 306                 flags |= SDHCI_CMD_DATA;
 307
 308         /* Set Transfer mode regarding to data flag */
 309         if (data) {
 310                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 311                 mode = SDHCI_TRNS_BLK_CNT_EN;
 312                 trans_bytes = data->blocks * data->blocksize;
 313                 if (data->blocks > 1)
 314                         mode |= SDHCI_TRNS_MULTI;
 315
 316                 if (data->flags == MMC_DATA_READ)
 317                         mode |= SDHCI_TRNS_READ;
 318
 319                 if (host->flags & USE_DMA) {
 320                         mode |= SDHCI_TRNS_DMA;
 321                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 322                 }
 323
 324                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 325                                 data->blocksize),
 326                                 SDHCI_BLOCK_SIZE);
 327                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 328                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 329         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 330                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 331         }
 332
 333         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 334         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 335         start = get_timer(0);
 336         do {
 337                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 338                 if (stat & SDHCI_INT_ERROR)
 339                         break;
 340
 341                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 342                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 343                                 return 0;
 344                         } else {
 345                                 printf("%s: Timeout for status update!\n",
 346                                        __func__);
 347                                 return -ETIMEDOUT;
 348                         }
 349                 }
 350         } while ((stat & mask) != mask);
 351
 352         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 353                 sdhci_cmd_done(host, cmd);
 354                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 355         } else
 356                 ret = -1;
 357
 358         if (!ret && data)
 359                 ret = sdhci_transfer_data(host, data);
 360
 361         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 362                 udelay(1000);
 363
 364         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 365         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 366         if (!ret) {
 367                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 368                                 !is_aligned && (data->flags == MMC_DATA_READ))
 369                         memcpy(data->dest, host->align_buffer, trans_bytes);
 370                 return 0;
 371         }
 372
 373         sdhci_reset(host, SDHCI_RESET_CMD);
 374         sdhci_reset(host, SDHCI_RESET_DATA);
 375         if (stat & SDHCI_INT_TIMEOUT)
 376                 return -ETIMEDOUT;
 377         else
 378                 return -ECOMM;
 379 }
 380
 381 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 382 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 383 {
 384         int err;
 385         struct mmc *mmc = mmc_get_mmc_dev(dev);
 386         struct sdhci_host *host = mmc->priv;
 387
 388         debug("%s\n", __func__);
 389
 390         if (host->ops && host->ops->platform_execute_tuning) {
 391                 err = host->ops->platform_execute_tuning(mmc, opcode);
 392                 if (err)
 393                         return err;
 394                 return 0;
 395         }
 396         return 0;
 397 }
 398 #endif
 399 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 400 {
 401         struct sdhci_host *host = mmc->priv;
 402         unsigned int div, clk = 0, timeout;
 403
 404         /* Wait max 20 ms */
 405         timeout = 200;
 406         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 407                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 408                 if (timeout == 0) {
 409                         printf("%s: Timeout to wait cmd & data inhibit\n",
 410                                __func__);
 411                         return -EBUSY;
 412                 }
 413
 414                 timeout--;
 415                 udelay(100);
 416         }
 417
 418         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 419
 420         if (clock == 0)
 421                 return 0;
 422
 423         if (host->ops && host->ops->set_delay)
 424                 host->ops->set_delay(host);
 425
 426         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 427                 /*
 428                  * Check if the Host Controller supports Programmable Clock
 429                  * Mode.
 430                  */
 431                 if (host->clk_mul) {
 432                         for (div = 1; div <= 1024; div++) {
 433                                 if ((host->max_clk / div) <= clock)
 434                                         break;
 435                         }
 436
 437                         /*
 438                          * Set Programmable Clock Mode in the Clock
 439                          * Control register.
 440                          */
 441                         clk = SDHCI_PROG_CLOCK_MODE;
 442                         div--;
 443                 } else {
 444                         /* Version 3.00 divisors must be a multiple of 2. */
 445                         if (host->max_clk <= clock) {
 446                                 div = 1;
 447                         } else {
 448                                 for (div = 2;
 449                                      div < SDHCI_MAX_DIV_SPEC_300;
 450                                      div += 2) {
 451                                         if ((host->max_clk / div) <= clock)
 452                                                 break;
 453                                 }
 454                         }
 455                         div >>= 1;
 456                 }
 457         } else {
 458                 /* Version 2.00 divisors must be a power of 2. */
 459                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 460                         if ((host->max_clk / div) <= clock)
 461                                 break;
 462                 }
 463                 div >>= 1;
 464         }
 465
 466         if (host->ops && host->ops->set_clock)
 467                 host->ops->set_clock(host, div);
 468
 469         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 470         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 471                 << SDHCI_DIVIDER_HI_SHIFT;
 472         clk |= SDHCI_CLOCK_INT_EN;
 473         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 474
 475         /* Wait max 20 ms */
 476         timeout = 20;
 477         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 478                 & SDHCI_CLOCK_INT_STABLE)) {
 479                 if (timeout == 0) {
 480                         printf("%s: Internal clock never stabilised.\n",
 481                                __func__);
 482                         return -EBUSY;
 483                 }
 484                 timeout--;
 485                 udelay(1000);
 486         }
 487
 488         clk |= SDHCI_CLOCK_CARD_EN;
 489         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 490         return 0;
 491 }
 492
 493 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 494 {
 495         u8 pwr = 0;
 496
 497         if (power != (unsigned short)-1) {
 498                 switch (1 << power) {
 499                 case MMC_VDD_165_195:
 500                         pwr = SDHCI_POWER_180;
 501                         break;
 502                 case MMC_VDD_29_30:
 503                 case MMC_VDD_30_31:
 504                         pwr = SDHCI_POWER_300;
 505                         break;
 506                 case MMC_VDD_32_33:
 507                 case MMC_VDD_33_34:
 508                         pwr = SDHCI_POWER_330;
 509                         break;
 510                 }
 511         }
 512
 513         if (pwr == 0) {
 514                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 515                 return;
 516         }
 517
 518         pwr |= SDHCI_POWER_ON;
 519
 520         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 521 }
 522
 523 void sdhci_set_uhs_timing(struct sdhci_host *host)
 524 {
 525         struct mmc *mmc = (struct mmc *)host->mmc;
 526         u32 reg;
 527
 528         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 529         reg &= ~SDHCI_CTRL_UHS_MASK;
 530
 531         switch (mmc->selected_mode) {
 532         case UHS_SDR50:
 533         case MMC_HS_52:
 534                 reg |= SDHCI_CTRL_UHS_SDR50;
 535                 break;
 536         case UHS_DDR50:
 537         case MMC_DDR_52:
 538                 reg |= SDHCI_CTRL_UHS_DDR50;
 539                 break;
 540         case UHS_SDR104:
 541         case MMC_HS_200:
 542                 reg |= SDHCI_CTRL_UHS_SDR104;
 543                 break;
 544         default:
 545                 reg |= SDHCI_CTRL_UHS_SDR12;
 546         }
 547
 548         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 549 }
 550
 551 #ifdef CONFIG_DM_MMC
 552 static int sdhci_set_ios(struct udevice *dev)
 553 {
 554         struct mmc *mmc = mmc_get_mmc_dev(dev);
 555 #else
 556 static int sdhci_set_ios(struct mmc *mmc)
 557 {
 558 #endif
 559         u32 ctrl;
 560         struct sdhci_host *host = mmc->priv;
 561
 562         if (host->ops && host->ops->set_control_reg)
 563                 host->ops->set_control_reg(host);
 564
 565         if (mmc->clock != host->clock)
 566                 sdhci_set_clock(mmc, mmc->clock);
 567
 568         if (mmc->clk_disable)
 569                 sdhci_set_clock(mmc, 0);
 570
 571         /* Set bus width */
 572         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 573         if (mmc->bus_width == 8) {
 574                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 575                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 576                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 577                         ctrl |= SDHCI_CTRL_8BITBUS;
 578         } else {
 579                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 580                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 581                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 582                 if (mmc->bus_width == 4)
 583                         ctrl |= SDHCI_CTRL_4BITBUS;
 584                 else
 585                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 586         }
 587
 588         if (mmc->clock > 26000000)
 589                 ctrl |= SDHCI_CTRL_HISPD;
 590         else
 591                 ctrl &= ~SDHCI_CTRL_HISPD;
 592
 593         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 594             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 595                 ctrl &= ~SDHCI_CTRL_HISPD;
 596
 597         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 598
 599         /* If available, call the driver specific "post" set_ios() function */
 600         if (host->ops && host->ops->set_ios_post)
 601                 return host->ops->set_ios_post(host);
 602
 603         return 0;
 604 }
 605
 606 static int sdhci_init(struct mmc *mmc)
 607 {
 608         struct sdhci_host *host = mmc->priv;
 609 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 610         struct udevice *dev = mmc->dev;
 611
 612         gpio_request_by_name(dev, "cd-gpios", 0,
 613                              &host->cd_gpio, GPIOD_IS_IN);
 614 #endif
 615
 616         sdhci_reset(host, SDHCI_RESET_ALL);
 617
 618 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 619         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 620         /*
 621          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 622          * is defined.
 623          */
 624         host->force_align_buffer = true;
 625 #else
 626         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 627                 host->align_buffer = memalign(8, 512 * 1024);
 628                 if (!host->align_buffer) {
 629                         printf("%s: Aligned buffer alloc failed!!!\n",
 630                                __func__);
 631                         return -ENOMEM;
 632                 }
 633         }
 634 #endif
 635
 636         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 637
 638         if (host->ops && host->ops->get_cd)
 639                 host->ops->get_cd(host);
 640
 641         /* Enable only interrupts served by the SD controller */
 642         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 643                      SDHCI_INT_ENABLE);
 644         /* Mask all sdhci interrupt sources */
 645         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 646
 647         return 0;
 648 }
 649
 650 #ifdef CONFIG_DM_MMC
 651 int sdhci_probe(struct udevice *dev)
 652 {
 653         struct mmc *mmc = mmc_get_mmc_dev(dev);
 654
 655         return sdhci_init(mmc);
 656 }
 657
 658 static int sdhci_get_cd(struct udevice *dev)
 659 {
 660         struct mmc *mmc = mmc_get_mmc_dev(dev);
 661         struct sdhci_host *host = mmc->priv;
 662         int value;
 663
 664         /* If nonremovable, assume that the card is always present. */
 665         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 666                 return 1;
 667         /* If polling, assume that the card is always present. */
 668         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 669                 return 1;
 670
 671 #if CONFIG_IS_ENABLED(DM_GPIO)
 672         value = dm_gpio_get_value(&host->cd_gpio);
 673         if (value >= 0) {
 674                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 675                         return !value;
 676                 else
 677                         return value;
 678         }
 679 #endif
 680         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 681                    SDHCI_CARD_PRESENT);
 682         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 683                 return !value;
 684         else
 685                 return value;
 686 }
 687
 688 const struct dm_mmc_ops sdhci_ops = {
 689         .send_cmd       = sdhci_send_command,
 690         .set_ios        = sdhci_set_ios,
 691         .get_cd         = sdhci_get_cd,
 692 #ifdef MMC_SUPPORTS_TUNING
 693         .execute_tuning = sdhci_execute_tuning,
 694 #endif
 695 };
 696 #else
 697 static const struct mmc_ops sdhci_ops = {
 698         .send_cmd       = sdhci_send_command,
 699         .set_ios        = sdhci_set_ios,
 700         .init           = sdhci_init,
 701 };
 702 #endif
 703
 704 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 705                 u32 f_max, u32 f_min)
 706 {
 707         u32 caps, caps_1 = 0;
 708 #if CONFIG_IS_ENABLED(DM_MMC)
 709         u64 dt_caps, dt_caps_mask;
 710
 711         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 712                                             "sdhci-caps-mask", 0);
 713         dt_caps = dev_read_u64_default(host->mmc->dev,
 714                                        "sdhci-caps", 0);
 715         caps = ~(u32)dt_caps_mask &
 716                sdhci_readl(host, SDHCI_CAPABILITIES);
 717         caps |= (u32)dt_caps;
 718 #else
 719         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 720 #endif
 721         debug("%s, caps: 0x%x\n", __func__, caps);
 722
 723 #ifdef CONFIG_MMC_SDHCI_SDMA
 724         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 725                 printf("%s: Your controller doesn't support SDMA!!\n",
 726                        __func__);
 727                 return -EINVAL;
 728         }
 729
 730         host->flags |= USE_SDMA;
 731 #endif
 732 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 733         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 734                 printf("%s: Your controller doesn't support SDMA!!\n",
 735                        __func__);
 736                 return -EINVAL;
 737         }
 738         host->adma_desc_table = (struct sdhci_adma_desc *)
 739                                 memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
 740
 741         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 742 #ifdef CONFIG_DMA_ADDR_T_64BIT
 743         host->flags |= USE_ADMA64;
 744 #else
 745         host->flags |= USE_ADMA;
 746 #endif
 747 #endif
 748         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 749                 host->version =
 750                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 751         else
 752                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 753
 754         cfg->name = host->name;
 755 #ifndef CONFIG_DM_MMC
 756         cfg->ops = &sdhci_ops;
 757 #endif
 758
 759         /* Check whether the clock multiplier is supported or not */
 760         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 761 #if CONFIG_IS_ENABLED(DM_MMC)
 762                 caps_1 = ~(u32)(dt_caps_mask >> 32) &
 763                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 764                 caps_1 |= (u32)(dt_caps >> 32);
 765 #else
 766                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 767 #endif
 768                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 769                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 770                                 SDHCI_CLOCK_MUL_SHIFT;
 771         }
 772
 773         if (host->max_clk == 0) {
 774                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 775                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 776                                 SDHCI_CLOCK_BASE_SHIFT;
 777                 else
 778                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 779                                 SDHCI_CLOCK_BASE_SHIFT;
 780                 host->max_clk *= 1000000;
 781                 if (host->clk_mul)
 782                         host->max_clk *= host->clk_mul;
 783         }
 784         if (host->max_clk == 0) {
 785                 printf("%s: Hardware doesn't specify base clock frequency\n",
 786                        __func__);
 787                 return -EINVAL;
 788         }
 789         if (f_max && (f_max < host->max_clk))
 790                 cfg->f_max = f_max;
 791         else
 792                 cfg->f_max = host->max_clk;
 793         if (f_min)
 794                 cfg->f_min = f_min;
 795         else {
 796                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 797                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 798                 else
 799                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 800         }
 801         cfg->voltages = 0;
 802         if (caps & SDHCI_CAN_VDD_330)
 803                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 804         if (caps & SDHCI_CAN_VDD_300)
 805                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 806         if (caps & SDHCI_CAN_VDD_180)
 807                 cfg->voltages |= MMC_VDD_165_195;
 808
 809         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 810                 cfg->voltages |= host->voltages;
 811
 812         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 813
 814         /* Since Host Controller Version3.0 */
 815         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 816                 if (!(caps & SDHCI_CAN_DO_8BIT))
 817                         cfg->host_caps &= ~MMC_MODE_8BIT;
 818         }
 819
 820         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 821                 cfg->host_caps &= ~MMC_MODE_HS;
 822                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 823         }
 824
 825         if (!(cfg->voltages & MMC_VDD_165_195) ||
 826             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 827                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 828                             SDHCI_SUPPORT_DDR50);
 829
 830         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 831                       SDHCI_SUPPORT_DDR50))
 832                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 833
 834         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 835                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 836                 /*
 837                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 838                  * field can be promoted to support HS200.
 839                  */
 840                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 841         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 842                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 843         }
 844
 845         if (caps_1 & SDHCI_SUPPORT_DDR50)
 846                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 847
 848         if (host->host_caps)
 849                 cfg->host_caps |= host->host_caps;
 850
 851         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 852
 853         return 0;
 854 }
 855
 856 #ifdef CONFIG_BLK
 857 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 858 {
 859         return mmc_bind(dev, mmc, cfg);
 860 }
 861 #else
 862 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 863 {
 864         int ret;
 865
 866         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 867         if (ret)
 868                 return ret;
 869
 870         host->mmc = mmc_create(&host->cfg, host);
 871         if (host->mmc == NULL) {
 872                 printf("%s: mmc create fail!\n", __func__);
 873                 return -ENOMEM;
 874         }
 875
 876         return 0;
 877 }
 878 #endif