drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <log.h>
  15 #include <malloc.h>
  16 #include <mmc.h>
  17 #include <sdhci.h>
  18 #include <asm/cache.h>
  19 #include <linux/bitops.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <phys2bus.h>
  23
  24 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  25 {
  26         unsigned long timeout;
  27
  28         /* Wait max 100 ms */
  29         timeout = 100;
  30         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  31         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  32                 if (timeout == 0) {
  33                         printf("%s: Reset 0x%x never completed.\n",
  34                                __func__, (int)mask);
  35                         return;
  36                 }
  37                 timeout--;
  38                 udelay(1000);
  39         }
  40 }
  41
  42 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  43 {
  44         int i;
  45         if (cmd->resp_type & MMC_RSP_136) {
  46                 /* CRC is stripped so we need to do some shifting. */
  47                 for (i = 0; i < 4; i++) {
  48                         cmd->response[i] = sdhci_readl(host,
  49                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  50                         if (i != 3)
  51                                 cmd->response[i] |= sdhci_readb(host,
  52                                                 SDHCI_RESPONSE + (3-i)*4-1);
  53                 }
  54         } else {
  55                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  56         }
  57 }
  58
  59 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  60 {
  61         int i;
  62         char *offs;
  63         for (i = 0; i < data->blocksize; i += 4) {
  64                 offs = data->dest + i;
  65                 if (data->flags == MMC_DATA_READ)
  66                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  67                 else
  68                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  69         }
  70 }
  71
  72 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  73 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  74                               int *is_aligned, int trans_bytes)
  75 {
  76         unsigned char ctrl;
  77         void *buf;
  78
  79         if (data->flags == MMC_DATA_READ)
  80                 buf = data->dest;
  81         else
  82                 buf = (void *)data->src;
  83
  84         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  85         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  86         if (host->flags & USE_ADMA64)
  87                 ctrl |= SDHCI_CTRL_ADMA64;
  88         else if (host->flags & USE_ADMA)
  89                 ctrl |= SDHCI_CTRL_ADMA32;
  90         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  91
  92         if (host->flags & USE_SDMA &&
  93             (host->force_align_buffer ||
  94              (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
  95               ((unsigned long)buf & 0x7) != 0x0))) {
  96                 *is_aligned = 0;
  97                 if (data->flags != MMC_DATA_READ)
  98                         memcpy(host->align_buffer, buf, trans_bytes);
  99                 buf = host->align_buffer;
 100         }
 101
 102         host->start_addr = dma_map_single(buf, trans_bytes,
 103                                           mmc_get_dma_dir(data));
 104
 105         if (host->flags & USE_SDMA) {
 106                 sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
 107                                 SDHCI_DMA_ADDRESS);
 108         }
 109 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 110         else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 111                 sdhci_prepare_adma_table(host->adma_desc_table, data,
 112                                          host->start_addr);
 113
 114                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 115                              SDHCI_ADMA_ADDRESS);
 116                 if (host->flags & USE_ADMA64)
 117                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 118                                      SDHCI_ADMA_ADDRESS_HI);
 119         }
 120 #endif
 121 }
 122 #else
 123 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 124                               int *is_aligned, int trans_bytes)
 125 {}
 126 #endif
 127 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 128 {
 129         dma_addr_t start_addr = host->start_addr;
 130         unsigned int stat, rdy, mask, timeout, block = 0;
 131         bool transfer_done = false;
 132
 133         timeout = 1000000;
 134         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 135         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 136         do {
 137                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 138                 if (stat & SDHCI_INT_ERROR) {
 139                         pr_debug("%s: Error detected in status(0x%X)!\n",
 140                                  __func__, stat);
 141                         return -EIO;
 142                 }
 143                 if (!transfer_done && (stat & rdy)) {
 144                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 145                                 continue;
 146                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 147                         sdhci_transfer_pio(host, data);
 148                         data->dest += data->blocksize;
 149                         if (++block >= data->blocks) {
 150                                 /* Keep looping until the SDHCI_INT_DATA_END is
 151                                  * cleared, even if we finished sending all the
 152                                  * blocks.
 153                                  */
 154                                 transfer_done = true;
 155                                 continue;
 156                         }
 157                 }
 158                 if ((host->flags & USE_DMA) && !transfer_done &&
 159                     (stat & SDHCI_INT_DMA_END)) {
 160                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 161                         if (host->flags & USE_SDMA) {
 162                                 start_addr &=
 163                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 164                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 165                                 sdhci_writel(host, phys_to_bus((ulong)start_addr),
 166                                              SDHCI_DMA_ADDRESS);
 167                         }
 168                 }
 169                 if (timeout-- > 0)
 170                         udelay(10);
 171                 else {
 172                         printf("%s: Transfer data timeout\n", __func__);
 173                         return -ETIMEDOUT;
 174                 }
 175         } while (!(stat & SDHCI_INT_DATA_END));
 176
 177         dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
 178                          mmc_get_dma_dir(data));
 179
 180         return 0;
 181 }
 182
 183 /*
 184  * No command will be sent by driver if card is busy, so driver must wait
 185  * for card ready state.
 186  * Every time when card is busy after timeout then (last) timeout value will be
 187  * increased twice but only if it doesn't exceed global defined maximum.
 188  * Each function call will use last timeout value.
 189  */
 190 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 191 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 192 #define SDHCI_READ_STATUS_TIMEOUT               1000
 193
 194 #ifdef CONFIG_DM_MMC
 195 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 196                               struct mmc_data *data)
 197 {
 198         struct mmc *mmc = mmc_get_mmc_dev(dev);
 199
 200 #else
 201 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 202                               struct mmc_data *data)
 203 {
 204 #endif
 205         struct sdhci_host *host = mmc->priv;
 206         unsigned int stat = 0;
 207         int ret = 0;
 208         int trans_bytes = 0, is_aligned = 1;
 209         u32 mask, flags, mode;
 210         unsigned int time = 0;
 211         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 212         ulong start = get_timer(0);
 213
 214         host->start_addr = 0;
 215         /* Timeout unit - ms */
 216         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 217
 218         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 219
 220         /* We shouldn't wait for data inihibit for stop commands, even
 221            though they might use busy signaling */
 222         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 223             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 224               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 225                 mask &= ~SDHCI_DATA_INHIBIT;
 226
 227         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 228                 if (time >= cmd_timeout) {
 229                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 230                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 231                                 cmd_timeout += cmd_timeout;
 232                                 printf("timeout increasing to: %u ms.\n",
 233                                        cmd_timeout);
 234                         } else {
 235                                 puts("timeout.\n");
 236                                 return -ECOMM;
 237                         }
 238                 }
 239                 time++;
 240                 udelay(1000);
 241         }
 242
 243         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 244
 245         mask = SDHCI_INT_RESPONSE;
 246         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 247              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 248                 mask = SDHCI_INT_DATA_AVAIL;
 249
 250         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 251                 flags = SDHCI_CMD_RESP_NONE;
 252         else if (cmd->resp_type & MMC_RSP_136)
 253                 flags = SDHCI_CMD_RESP_LONG;
 254         else if (cmd->resp_type & MMC_RSP_BUSY) {
 255                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 256                 if (data)
 257                         mask |= SDHCI_INT_DATA_END;
 258         } else
 259                 flags = SDHCI_CMD_RESP_SHORT;
 260
 261         if (cmd->resp_type & MMC_RSP_CRC)
 262                 flags |= SDHCI_CMD_CRC;
 263         if (cmd->resp_type & MMC_RSP_OPCODE)
 264                 flags |= SDHCI_CMD_INDEX;
 265         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 266             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 267                 flags |= SDHCI_CMD_DATA;
 268
 269         /* Set Transfer mode regarding to data flag */
 270         if (data) {
 271                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 272                 mode = SDHCI_TRNS_BLK_CNT_EN;
 273                 trans_bytes = data->blocks * data->blocksize;
 274                 if (data->blocks > 1)
 275                         mode |= SDHCI_TRNS_MULTI;
 276
 277                 if (data->flags == MMC_DATA_READ)
 278                         mode |= SDHCI_TRNS_READ;
 279
 280                 if (host->flags & USE_DMA) {
 281                         mode |= SDHCI_TRNS_DMA;
 282                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 283                 }
 284
 285                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 286                                 data->blocksize),
 287                                 SDHCI_BLOCK_SIZE);
 288                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 289                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 290         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 291                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 292         }
 293
 294         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 295         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 296         start = get_timer(0);
 297         do {
 298                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 299                 if (stat & SDHCI_INT_ERROR)
 300                         break;
 301
 302                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 303                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 304                                 return 0;
 305                         } else {
 306                                 printf("%s: Timeout for status update!\n",
 307                                        __func__);
 308                                 return -ETIMEDOUT;
 309                         }
 310                 }
 311         } while ((stat & mask) != mask);
 312
 313         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 314                 sdhci_cmd_done(host, cmd);
 315                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 316         } else
 317                 ret = -1;
 318
 319         if (!ret && data)
 320                 ret = sdhci_transfer_data(host, data);
 321
 322         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 323                 udelay(1000);
 324
 325         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 326         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 327         if (!ret) {
 328                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 329                                 !is_aligned && (data->flags == MMC_DATA_READ))
 330                         memcpy(data->dest, host->align_buffer, trans_bytes);
 331                 return 0;
 332         }
 333
 334         sdhci_reset(host, SDHCI_RESET_CMD);
 335         sdhci_reset(host, SDHCI_RESET_DATA);
 336         if (stat & SDHCI_INT_TIMEOUT)
 337                 return -ETIMEDOUT;
 338         else
 339                 return -ECOMM;
 340 }
 341
 342 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 343 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 344 {
 345         int err;
 346         struct mmc *mmc = mmc_get_mmc_dev(dev);
 347         struct sdhci_host *host = mmc->priv;
 348
 349         debug("%s\n", __func__);
 350
 351         if (host->ops && host->ops->platform_execute_tuning) {
 352                 err = host->ops->platform_execute_tuning(mmc, opcode);
 353                 if (err)
 354                         return err;
 355                 return 0;
 356         }
 357         return 0;
 358 }
 359 #endif
 360 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 361 {
 362         struct sdhci_host *host = mmc->priv;
 363         unsigned int div, clk = 0, timeout;
 364
 365         /* Wait max 20 ms */
 366         timeout = 200;
 367         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 368                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 369                 if (timeout == 0) {
 370                         printf("%s: Timeout to wait cmd & data inhibit\n",
 371                                __func__);
 372                         return -EBUSY;
 373                 }
 374
 375                 timeout--;
 376                 udelay(100);
 377         }
 378
 379         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 380
 381         if (clock == 0)
 382                 return 0;
 383
 384         if (host->ops && host->ops->set_delay)
 385                 host->ops->set_delay(host);
 386
 387         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 388                 /*
 389                  * Check if the Host Controller supports Programmable Clock
 390                  * Mode.
 391                  */
 392                 if (host->clk_mul) {
 393                         for (div = 1; div <= 1024; div++) {
 394                                 if ((host->max_clk / div) <= clock)
 395                                         break;
 396                         }
 397
 398                         /*
 399                          * Set Programmable Clock Mode in the Clock
 400                          * Control register.
 401                          */
 402                         clk = SDHCI_PROG_CLOCK_MODE;
 403                         div--;
 404                 } else {
 405                         /* Version 3.00 divisors must be a multiple of 2. */
 406                         if (host->max_clk <= clock) {
 407                                 div = 1;
 408                         } else {
 409                                 for (div = 2;
 410                                      div < SDHCI_MAX_DIV_SPEC_300;
 411                                      div += 2) {
 412                                         if ((host->max_clk / div) <= clock)
 413                                                 break;
 414                                 }
 415                         }
 416                         div >>= 1;
 417                 }
 418         } else {
 419                 /* Version 2.00 divisors must be a power of 2. */
 420                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 421                         if ((host->max_clk / div) <= clock)
 422                                 break;
 423                 }
 424                 div >>= 1;
 425         }
 426
 427         if (host->ops && host->ops->set_clock)
 428                 host->ops->set_clock(host, div);
 429
 430         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 431         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 432                 << SDHCI_DIVIDER_HI_SHIFT;
 433         clk |= SDHCI_CLOCK_INT_EN;
 434         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 435
 436         /* Wait max 20 ms */
 437         timeout = 20;
 438         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 439                 & SDHCI_CLOCK_INT_STABLE)) {
 440                 if (timeout == 0) {
 441                         printf("%s: Internal clock never stabilised.\n",
 442                                __func__);
 443                         return -EBUSY;
 444                 }
 445                 timeout--;
 446                 udelay(1000);
 447         }
 448
 449         clk |= SDHCI_CLOCK_CARD_EN;
 450         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 451         return 0;
 452 }
 453
 454 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 455 {
 456         u8 pwr = 0;
 457
 458         if (power != (unsigned short)-1) {
 459                 switch (1 << power) {
 460                 case MMC_VDD_165_195:
 461                         pwr = SDHCI_POWER_180;
 462                         break;
 463                 case MMC_VDD_29_30:
 464                 case MMC_VDD_30_31:
 465                         pwr = SDHCI_POWER_300;
 466                         break;
 467                 case MMC_VDD_32_33:
 468                 case MMC_VDD_33_34:
 469                         pwr = SDHCI_POWER_330;
 470                         break;
 471                 }
 472         }
 473
 474         if (pwr == 0) {
 475                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 476                 return;
 477         }
 478
 479         pwr |= SDHCI_POWER_ON;
 480
 481         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 482 }
 483
 484 void sdhci_set_uhs_timing(struct sdhci_host *host)
 485 {
 486         struct mmc *mmc = host->mmc;
 487         u32 reg;
 488
 489         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 490         reg &= ~SDHCI_CTRL_UHS_MASK;
 491
 492         switch (mmc->selected_mode) {
 493         case UHS_SDR50:
 494         case MMC_HS_52:
 495                 reg |= SDHCI_CTRL_UHS_SDR50;
 496                 break;
 497         case UHS_DDR50:
 498         case MMC_DDR_52:
 499                 reg |= SDHCI_CTRL_UHS_DDR50;
 500                 break;
 501         case UHS_SDR104:
 502         case MMC_HS_200:
 503                 reg |= SDHCI_CTRL_UHS_SDR104;
 504                 break;
 505         default:
 506                 reg |= SDHCI_CTRL_UHS_SDR12;
 507         }
 508
 509         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 510 }
 511
 512 #ifdef CONFIG_DM_MMC
 513 static int sdhci_set_ios(struct udevice *dev)
 514 {
 515         struct mmc *mmc = mmc_get_mmc_dev(dev);
 516 #else
 517 static int sdhci_set_ios(struct mmc *mmc)
 518 {
 519 #endif
 520         u32 ctrl;
 521         struct sdhci_host *host = mmc->priv;
 522         bool no_hispd_bit = false;
 523
 524         if (host->ops && host->ops->set_control_reg)
 525                 host->ops->set_control_reg(host);
 526
 527         if (mmc->clock != host->clock)
 528                 sdhci_set_clock(mmc, mmc->clock);
 529
 530         if (mmc->clk_disable)
 531                 sdhci_set_clock(mmc, 0);
 532
 533         /* Set bus width */
 534         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 535         if (mmc->bus_width == 8) {
 536                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 537                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 538                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 539                         ctrl |= SDHCI_CTRL_8BITBUS;
 540         } else {
 541                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 542                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 543                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 544                 if (mmc->bus_width == 4)
 545                         ctrl |= SDHCI_CTRL_4BITBUS;
 546                 else
 547                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 548         }
 549
 550         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 551             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
 552                 ctrl &= ~SDHCI_CTRL_HISPD;
 553                 no_hispd_bit = true;
 554         }
 555
 556         if (!no_hispd_bit) {
 557                 if (mmc->selected_mode == MMC_HS ||
 558                     mmc->selected_mode == SD_HS ||
 559                     mmc->selected_mode == MMC_DDR_52 ||
 560                     mmc->selected_mode == MMC_HS_200 ||
 561                     mmc->selected_mode == MMC_HS_400 ||
 562                     mmc->selected_mode == UHS_SDR25 ||
 563                     mmc->selected_mode == UHS_SDR50 ||
 564                     mmc->selected_mode == UHS_SDR104 ||
 565                     mmc->selected_mode == UHS_DDR50)
 566                         ctrl |= SDHCI_CTRL_HISPD;
 567                 else
 568                         ctrl &= ~SDHCI_CTRL_HISPD;
 569         }
 570
 571         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 572
 573         /* If available, call the driver specific "post" set_ios() function */
 574         if (host->ops && host->ops->set_ios_post)
 575                 return host->ops->set_ios_post(host);
 576
 577         return 0;
 578 }
 579
 580 static int sdhci_init(struct mmc *mmc)
 581 {
 582         struct sdhci_host *host = mmc->priv;
 583 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 584         struct udevice *dev = mmc->dev;
 585
 586         gpio_request_by_name(dev, "cd-gpios", 0,
 587                              &host->cd_gpio, GPIOD_IS_IN);
 588 #endif
 589
 590         sdhci_reset(host, SDHCI_RESET_ALL);
 591
 592 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 593         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 594         /*
 595          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 596          * is defined.
 597          */
 598         host->force_align_buffer = true;
 599 #else
 600         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 601                 host->align_buffer = memalign(8, 512 * 1024);
 602                 if (!host->align_buffer) {
 603                         printf("%s: Aligned buffer alloc failed!!!\n",
 604                                __func__);
 605                         return -ENOMEM;
 606                 }
 607         }
 608 #endif
 609
 610         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 611
 612         if (host->ops && host->ops->get_cd)
 613                 host->ops->get_cd(host);
 614
 615         /* Enable only interrupts served by the SD controller */
 616         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 617                      SDHCI_INT_ENABLE);
 618         /* Mask all sdhci interrupt sources */
 619         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 620
 621         return 0;
 622 }
 623
 624 #ifdef CONFIG_DM_MMC
 625 int sdhci_probe(struct udevice *dev)
 626 {
 627         struct mmc *mmc = mmc_get_mmc_dev(dev);
 628
 629         return sdhci_init(mmc);
 630 }
 631
 632 static int sdhci_deferred_probe(struct udevice *dev)
 633 {
 634         int err;
 635         struct mmc *mmc = mmc_get_mmc_dev(dev);
 636         struct sdhci_host *host = mmc->priv;
 637
 638         if (host->ops && host->ops->deferred_probe) {
 639                 err = host->ops->deferred_probe(host);
 640                 if (err)
 641                         return err;
 642         }
 643         return 0;
 644 }
 645
 646 static int sdhci_get_cd(struct udevice *dev)
 647 {
 648         struct mmc *mmc = mmc_get_mmc_dev(dev);
 649         struct sdhci_host *host = mmc->priv;
 650         int value;
 651
 652         /* If nonremovable, assume that the card is always present. */
 653         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 654                 return 1;
 655         /* If polling, assume that the card is always present. */
 656         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 657                 return 1;
 658
 659 #if CONFIG_IS_ENABLED(DM_GPIO)
 660         value = dm_gpio_get_value(&host->cd_gpio);
 661         if (value >= 0) {
 662                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 663                         return !value;
 664                 else
 665                         return value;
 666         }
 667 #endif
 668         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 669                    SDHCI_CARD_PRESENT);
 670         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 671                 return !value;
 672         else
 673                 return value;
 674 }
 675
 676 const struct dm_mmc_ops sdhci_ops = {
 677         .send_cmd       = sdhci_send_command,
 678         .set_ios        = sdhci_set_ios,
 679         .get_cd         = sdhci_get_cd,
 680         .deferred_probe = sdhci_deferred_probe,
 681 #ifdef MMC_SUPPORTS_TUNING
 682         .execute_tuning = sdhci_execute_tuning,
 683 #endif
 684 };
 685 #else
 686 static const struct mmc_ops sdhci_ops = {
 687         .send_cmd       = sdhci_send_command,
 688         .set_ios        = sdhci_set_ios,
 689         .init           = sdhci_init,
 690 };
 691 #endif
 692
 693 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 694                 u32 f_max, u32 f_min)
 695 {
 696         u32 caps, caps_1 = 0;
 697 #if CONFIG_IS_ENABLED(DM_MMC)
 698         u64 dt_caps, dt_caps_mask;
 699
 700         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 701                                             "sdhci-caps-mask", 0);
 702         dt_caps = dev_read_u64_default(host->mmc->dev,
 703                                        "sdhci-caps", 0);
 704         caps = ~lower_32_bits(dt_caps_mask) &
 705                sdhci_readl(host, SDHCI_CAPABILITIES);
 706         caps |= lower_32_bits(dt_caps);
 707 #else
 708         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 709 #endif
 710         debug("%s, caps: 0x%x\n", __func__, caps);
 711
 712 #ifdef CONFIG_MMC_SDHCI_SDMA
 713         if ((caps & SDHCI_CAN_DO_SDMA)) {
 714                 host->flags |= USE_SDMA;
 715         } else {
 716                 debug("%s: Your controller doesn't support SDMA!!\n",
 717                       __func__);
 718         }
 719 #endif
 720 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 721         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 722                 printf("%s: Your controller doesn't support SDMA!!\n",
 723                        __func__);
 724                 return -EINVAL;
 725         }
 726         host->adma_desc_table = sdhci_adma_init();
 727         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 728
 729 #ifdef CONFIG_DMA_ADDR_T_64BIT
 730         host->flags |= USE_ADMA64;
 731 #else
 732         host->flags |= USE_ADMA;
 733 #endif
 734 #endif
 735         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 736                 host->version =
 737                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 738         else
 739                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 740
 741         cfg->name = host->name;
 742 #ifndef CONFIG_DM_MMC
 743         cfg->ops = &sdhci_ops;
 744 #endif
 745
 746         /* Check whether the clock multiplier is supported or not */
 747         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 748 #if CONFIG_IS_ENABLED(DM_MMC)
 749                 caps_1 = ~upper_32_bits(dt_caps_mask) &
 750                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 751                 caps_1 |= upper_32_bits(dt_caps);
 752 #else
 753                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 754 #endif
 755                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 756                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 757                                 SDHCI_CLOCK_MUL_SHIFT;
 758         }
 759
 760         if (host->max_clk == 0) {
 761                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 762                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 763                                 SDHCI_CLOCK_BASE_SHIFT;
 764                 else
 765                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 766                                 SDHCI_CLOCK_BASE_SHIFT;
 767                 host->max_clk *= 1000000;
 768                 if (host->clk_mul)
 769                         host->max_clk *= host->clk_mul;
 770         }
 771         if (host->max_clk == 0) {
 772                 printf("%s: Hardware doesn't specify base clock frequency\n",
 773                        __func__);
 774                 return -EINVAL;
 775         }
 776         if (f_max && (f_max < host->max_clk))
 777                 cfg->f_max = f_max;
 778         else
 779                 cfg->f_max = host->max_clk;
 780         if (f_min)
 781                 cfg->f_min = f_min;
 782         else {
 783                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 784                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 785                 else
 786                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 787         }
 788         cfg->voltages = 0;
 789         if (caps & SDHCI_CAN_VDD_330)
 790                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 791         if (caps & SDHCI_CAN_VDD_300)
 792                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 793         if (caps & SDHCI_CAN_VDD_180)
 794                 cfg->voltages |= MMC_VDD_165_195;
 795
 796         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 797                 cfg->voltages |= host->voltages;
 798
 799         if (caps & SDHCI_CAN_DO_HISPD)
 800                 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 801
 802         cfg->host_caps |= MMC_MODE_4BIT;
 803
 804         /* Since Host Controller Version3.0 */
 805         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 806                 if (!(caps & SDHCI_CAN_DO_8BIT))
 807                         cfg->host_caps &= ~MMC_MODE_8BIT;
 808         }
 809
 810         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 811                 cfg->host_caps &= ~MMC_MODE_HS;
 812                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 813         }
 814
 815         if (!(cfg->voltages & MMC_VDD_165_195) ||
 816             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 817                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 818                             SDHCI_SUPPORT_DDR50);
 819
 820         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 821                       SDHCI_SUPPORT_DDR50))
 822                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 823
 824         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 825                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 826                 /*
 827                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 828                  * field can be promoted to support HS200.
 829                  */
 830                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 831         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 832                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 833         }
 834
 835         if (caps_1 & SDHCI_SUPPORT_DDR50)
 836                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 837
 838         if (host->host_caps)
 839                 cfg->host_caps |= host->host_caps;
 840
 841         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 842
 843         return 0;
 844 }
 845
 846 #ifdef CONFIG_BLK
 847 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 848 {
 849         return mmc_bind(dev, mmc, cfg);
 850 }
 851 #else
 852 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 853 {
 854         int ret;
 855
 856         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 857         if (ret)
 858                 return ret;
 859
 860         host->mmc = mmc_create(&host->cfg, host);
 861         if (host->mmc == NULL) {
 862                 printf("%s: mmc create fail!\n", __func__);
 863                 return -ENOMEM;
 864         }
 865
 866         return 0;
 867 }
 868 #endif