drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <mmc.h>
  14 #include <sdhci.h>
  15
  16 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  17 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  18 #else
  19 void *aligned_buffer;
  20 #endif
  21
  22 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  23 {
  24         unsigned long timeout;
  25
  26         /* Wait max 100 ms */
  27         timeout = 100;
  28         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  29         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  30                 if (timeout == 0) {
  31                         printf("%s: Reset 0x%x never completed.\n",
  32                                __func__, (int)mask);
  33                         return;
  34                 }
  35                 timeout--;
  36                 udelay(1000);
  37         }
  38 }
  39
  40 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  41 {
  42         int i;
  43         if (cmd->resp_type & MMC_RSP_136) {
  44                 /* CRC is stripped so we need to do some shifting. */
  45                 for (i = 0; i < 4; i++) {
  46                         cmd->response[i] = sdhci_readl(host,
  47                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  48                         if (i != 3)
  49                                 cmd->response[i] |= sdhci_readb(host,
  50                                                 SDHCI_RESPONSE + (3-i)*4-1);
  51                 }
  52         } else {
  53                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  54         }
  55 }
  56
  57 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  58 {
  59         int i;
  60         char *offs;
  61         for (i = 0; i < data->blocksize; i += 4) {
  62                 offs = data->dest + i;
  63                 if (data->flags == MMC_DATA_READ)
  64                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  65                 else
  66                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  67         }
  68 }
  69 #ifdef CONFIG_MMC_SDHCI_SDMA
  70 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  71                               int *is_aligned, int trans_bytes)
  72 {
  73         unsigned char ctrl;
  74
  75         if (data->flags == MMC_DATA_READ)
  76                 host->start_addr = (dma_addr_t)data->dest;
  77         else
  78                 host->start_addr = (dma_addr_t)data->src;
  79
  80         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
  81             (host->start_addr & 0x7) != 0x0) {
  82                 *is_aligned = 0;
  83                 host->start_addr = (unsigned long)aligned_buffer;
  84                 if (data->flags != MMC_DATA_READ)
  85                         memcpy(aligned_buffer, data->src, trans_bytes);
  86         }
  87
  88         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  89         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  90         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  91
  92 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  93         /*
  94          * Always use this bounce-buffer when
  95          * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
  96          */
  97         *is_aligned = 0;
  98         host->start_addr = (unsigned long)aligned_buffer;
  99         if (data->flags != MMC_DATA_READ)
 100                 memcpy(aligned_buffer, data->src, trans_bytes);
 101 #endif
 102         sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
 103         flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
 104 }
 105 #else
 106 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 107                               int *is_aligned, int trans_bytes)
 108 {}
 109 #endif
 110 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 111 {
 112         dma_addr_t start_addr = host->start_addr;
 113         unsigned int stat, rdy, mask, timeout, block = 0;
 114         bool transfer_done = false;
 115
 116         timeout = 1000000;
 117         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 118         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 119         do {
 120                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 121                 if (stat & SDHCI_INT_ERROR) {
 122                         pr_debug("%s: Error detected in status(0x%X)!\n",
 123                                  __func__, stat);
 124                         return -EIO;
 125                 }
 126                 if (!transfer_done && (stat & rdy)) {
 127                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 128                                 continue;
 129                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 130                         sdhci_transfer_pio(host, data);
 131                         data->dest += data->blocksize;
 132                         if (++block >= data->blocks) {
 133                                 /* Keep looping until the SDHCI_INT_DATA_END is
 134                                  * cleared, even if we finished sending all the
 135                                  * blocks.
 136                                  */
 137                                 transfer_done = true;
 138                                 continue;
 139                         }
 140                 }
 141                 if ((host->flags & USE_SDMA) && !transfer_done &&
 142                     (stat & SDHCI_INT_DMA_END)) {
 143                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 144                         start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 145                         start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 146                         sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 147                 }
 148                 if (timeout-- > 0)
 149                         udelay(10);
 150                 else {
 151                         printf("%s: Transfer data timeout\n", __func__);
 152                         return -ETIMEDOUT;
 153                 }
 154         } while (!(stat & SDHCI_INT_DATA_END));
 155         return 0;
 156 }
 157
 158 /*
 159  * No command will be sent by driver if card is busy, so driver must wait
 160  * for card ready state.
 161  * Every time when card is busy after timeout then (last) timeout value will be
 162  * increased twice but only if it doesn't exceed global defined maximum.
 163  * Each function call will use last timeout value.
 164  */
 165 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 166 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 167 #define SDHCI_READ_STATUS_TIMEOUT               1000
 168
 169 #ifdef CONFIG_DM_MMC
 170 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 171                               struct mmc_data *data)
 172 {
 173         struct mmc *mmc = mmc_get_mmc_dev(dev);
 174
 175 #else
 176 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 177                               struct mmc_data *data)
 178 {
 179 #endif
 180         struct sdhci_host *host = mmc->priv;
 181         unsigned int stat = 0;
 182         int ret = 0;
 183         int trans_bytes = 0, is_aligned = 1;
 184         u32 mask, flags, mode;
 185         unsigned int time = 0;
 186         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 187         ulong start = get_timer(0);
 188
 189         host->start_addr = 0;
 190         /* Timeout unit - ms */
 191         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 192
 193         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 194
 195         /* We shouldn't wait for data inihibit for stop commands, even
 196            though they might use busy signaling */
 197         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 198             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 199               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 200                 mask &= ~SDHCI_DATA_INHIBIT;
 201
 202         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 203                 if (time >= cmd_timeout) {
 204                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 205                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 206                                 cmd_timeout += cmd_timeout;
 207                                 printf("timeout increasing to: %u ms.\n",
 208                                        cmd_timeout);
 209                         } else {
 210                                 puts("timeout.\n");
 211                                 return -ECOMM;
 212                         }
 213                 }
 214                 time++;
 215                 udelay(1000);
 216         }
 217
 218         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 219
 220         mask = SDHCI_INT_RESPONSE;
 221         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 222              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 223                 mask = SDHCI_INT_DATA_AVAIL;
 224
 225         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 226                 flags = SDHCI_CMD_RESP_NONE;
 227         else if (cmd->resp_type & MMC_RSP_136)
 228                 flags = SDHCI_CMD_RESP_LONG;
 229         else if (cmd->resp_type & MMC_RSP_BUSY) {
 230                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 231                 if (data)
 232                         mask |= SDHCI_INT_DATA_END;
 233         } else
 234                 flags = SDHCI_CMD_RESP_SHORT;
 235
 236         if (cmd->resp_type & MMC_RSP_CRC)
 237                 flags |= SDHCI_CMD_CRC;
 238         if (cmd->resp_type & MMC_RSP_OPCODE)
 239                 flags |= SDHCI_CMD_INDEX;
 240         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 241             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 242                 flags |= SDHCI_CMD_DATA;
 243
 244         /* Set Transfer mode regarding to data flag */
 245         if (data) {
 246                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 247                 mode = SDHCI_TRNS_BLK_CNT_EN;
 248                 trans_bytes = data->blocks * data->blocksize;
 249                 if (data->blocks > 1)
 250                         mode |= SDHCI_TRNS_MULTI;
 251
 252                 if (data->flags == MMC_DATA_READ)
 253                         mode |= SDHCI_TRNS_READ;
 254
 255                 if (host->flags & USE_SDMA) {
 256                         mode |= SDHCI_TRNS_DMA;
 257                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 258                 }
 259
 260                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 261                                 data->blocksize),
 262                                 SDHCI_BLOCK_SIZE);
 263                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 264                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 265         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 266                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 267         }
 268
 269         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 270         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 271         start = get_timer(0);
 272         do {
 273                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 274                 if (stat & SDHCI_INT_ERROR)
 275                         break;
 276
 277                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 278                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 279                                 return 0;
 280                         } else {
 281                                 printf("%s: Timeout for status update!\n",
 282                                        __func__);
 283                                 return -ETIMEDOUT;
 284                         }
 285                 }
 286         } while ((stat & mask) != mask);
 287
 288         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 289                 sdhci_cmd_done(host, cmd);
 290                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 291         } else
 292                 ret = -1;
 293
 294         if (!ret && data)
 295                 ret = sdhci_transfer_data(host, data);
 296
 297         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 298                 udelay(1000);
 299
 300         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 301         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 302         if (!ret) {
 303                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 304                                 !is_aligned && (data->flags == MMC_DATA_READ))
 305                         memcpy(data->dest, aligned_buffer, trans_bytes);
 306                 return 0;
 307         }
 308
 309         sdhci_reset(host, SDHCI_RESET_CMD);
 310         sdhci_reset(host, SDHCI_RESET_DATA);
 311         if (stat & SDHCI_INT_TIMEOUT)
 312                 return -ETIMEDOUT;
 313         else
 314                 return -ECOMM;
 315 }
 316
 317 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 318 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 319 {
 320         int err;
 321         struct mmc *mmc = mmc_get_mmc_dev(dev);
 322         struct sdhci_host *host = mmc->priv;
 323
 324         debug("%s\n", __func__);
 325
 326         if (host->ops && host->ops->platform_execute_tuning) {
 327                 err = host->ops->platform_execute_tuning(mmc, opcode);
 328                 if (err)
 329                         return err;
 330                 return 0;
 331         }
 332         return 0;
 333 }
 334 #endif
 335 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 336 {
 337         struct sdhci_host *host = mmc->priv;
 338         unsigned int div, clk = 0, timeout;
 339
 340         /* Wait max 20 ms */
 341         timeout = 200;
 342         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 343                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 344                 if (timeout == 0) {
 345                         printf("%s: Timeout to wait cmd & data inhibit\n",
 346                                __func__);
 347                         return -EBUSY;
 348                 }
 349
 350                 timeout--;
 351                 udelay(100);
 352         }
 353
 354         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 355
 356         if (clock == 0)
 357                 return 0;
 358
 359         if (host->ops && host->ops->set_delay)
 360                 host->ops->set_delay(host);
 361
 362         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 363                 /*
 364                  * Check if the Host Controller supports Programmable Clock
 365                  * Mode.
 366                  */
 367                 if (host->clk_mul) {
 368                         for (div = 1; div <= 1024; div++) {
 369                                 if ((host->max_clk / div) <= clock)
 370                                         break;
 371                         }
 372
 373                         /*
 374                          * Set Programmable Clock Mode in the Clock
 375                          * Control register.
 376                          */
 377                         clk = SDHCI_PROG_CLOCK_MODE;
 378                         div--;
 379                 } else {
 380                         /* Version 3.00 divisors must be a multiple of 2. */
 381                         if (host->max_clk <= clock) {
 382                                 div = 1;
 383                         } else {
 384                                 for (div = 2;
 385                                      div < SDHCI_MAX_DIV_SPEC_300;
 386                                      div += 2) {
 387                                         if ((host->max_clk / div) <= clock)
 388                                                 break;
 389                                 }
 390                         }
 391                         div >>= 1;
 392                 }
 393         } else {
 394                 /* Version 2.00 divisors must be a power of 2. */
 395                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 396                         if ((host->max_clk / div) <= clock)
 397                                 break;
 398                 }
 399                 div >>= 1;
 400         }
 401
 402         if (host->ops && host->ops->set_clock)
 403                 host->ops->set_clock(host, div);
 404
 405         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 406         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 407                 << SDHCI_DIVIDER_HI_SHIFT;
 408         clk |= SDHCI_CLOCK_INT_EN;
 409         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 410
 411         /* Wait max 20 ms */
 412         timeout = 20;
 413         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 414                 & SDHCI_CLOCK_INT_STABLE)) {
 415                 if (timeout == 0) {
 416                         printf("%s: Internal clock never stabilised.\n",
 417                                __func__);
 418                         return -EBUSY;
 419                 }
 420                 timeout--;
 421                 udelay(1000);
 422         }
 423
 424         clk |= SDHCI_CLOCK_CARD_EN;
 425         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 426         return 0;
 427 }
 428
 429 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 430 {
 431         u8 pwr = 0;
 432
 433         if (power != (unsigned short)-1) {
 434                 switch (1 << power) {
 435                 case MMC_VDD_165_195:
 436                         pwr = SDHCI_POWER_180;
 437                         break;
 438                 case MMC_VDD_29_30:
 439                 case MMC_VDD_30_31:
 440                         pwr = SDHCI_POWER_300;
 441                         break;
 442                 case MMC_VDD_32_33:
 443                 case MMC_VDD_33_34:
 444                         pwr = SDHCI_POWER_330;
 445                         break;
 446                 }
 447         }
 448
 449         if (pwr == 0) {
 450                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 451                 return;
 452         }
 453
 454         pwr |= SDHCI_POWER_ON;
 455
 456         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 457 }
 458
 459 #ifdef CONFIG_DM_MMC
 460 static int sdhci_set_ios(struct udevice *dev)
 461 {
 462         struct mmc *mmc = mmc_get_mmc_dev(dev);
 463 #else
 464 static int sdhci_set_ios(struct mmc *mmc)
 465 {
 466 #endif
 467         u32 ctrl;
 468         struct sdhci_host *host = mmc->priv;
 469
 470         if (host->ops && host->ops->set_control_reg)
 471                 host->ops->set_control_reg(host);
 472
 473         if (mmc->clock != host->clock)
 474                 sdhci_set_clock(mmc, mmc->clock);
 475
 476         if (mmc->clk_disable)
 477                 sdhci_set_clock(mmc, 0);
 478
 479         /* Set bus width */
 480         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 481         if (mmc->bus_width == 8) {
 482                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 483                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 484                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 485                         ctrl |= SDHCI_CTRL_8BITBUS;
 486         } else {
 487                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 488                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 489                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 490                 if (mmc->bus_width == 4)
 491                         ctrl |= SDHCI_CTRL_4BITBUS;
 492                 else
 493                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 494         }
 495
 496         if (mmc->clock > 26000000)
 497                 ctrl |= SDHCI_CTRL_HISPD;
 498         else
 499                 ctrl &= ~SDHCI_CTRL_HISPD;
 500
 501         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 502             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 503                 ctrl &= ~SDHCI_CTRL_HISPD;
 504
 505         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 506
 507         /* If available, call the driver specific "post" set_ios() function */
 508         if (host->ops && host->ops->set_ios_post)
 509                 host->ops->set_ios_post(host);
 510
 511         return 0;
 512 }
 513
 514 static int sdhci_init(struct mmc *mmc)
 515 {
 516         struct sdhci_host *host = mmc->priv;
 517
 518         sdhci_reset(host, SDHCI_RESET_ALL);
 519
 520         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 521                 aligned_buffer = memalign(8, 512*1024);
 522                 if (!aligned_buffer) {
 523                         printf("%s: Aligned buffer alloc failed!!!\n",
 524                                __func__);
 525                         return -ENOMEM;
 526                 }
 527         }
 528
 529         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 530
 531         if (host->ops && host->ops->get_cd)
 532                 host->ops->get_cd(host);
 533
 534         /* Enable only interrupts served by the SD controller */
 535         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 536                      SDHCI_INT_ENABLE);
 537         /* Mask all sdhci interrupt sources */
 538         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 539
 540         return 0;
 541 }
 542
 543 #ifdef CONFIG_DM_MMC
 544 int sdhci_probe(struct udevice *dev)
 545 {
 546         struct mmc *mmc = mmc_get_mmc_dev(dev);
 547
 548         return sdhci_init(mmc);
 549 }
 550
 551 const struct dm_mmc_ops sdhci_ops = {
 552         .send_cmd       = sdhci_send_command,
 553         .set_ios        = sdhci_set_ios,
 554 #ifdef MMC_SUPPORTS_TUNING
 555         .execute_tuning = sdhci_execute_tuning,
 556 #endif
 557 };
 558 #else
 559 static const struct mmc_ops sdhci_ops = {
 560         .send_cmd       = sdhci_send_command,
 561         .set_ios        = sdhci_set_ios,
 562         .init           = sdhci_init,
 563 };
 564 #endif
 565
 566 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 567                 u32 f_max, u32 f_min)
 568 {
 569         u32 caps, caps_1 = 0;
 570
 571         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 572
 573 #ifdef CONFIG_MMC_SDHCI_SDMA
 574         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 575                 printf("%s: Your controller doesn't support SDMA!!\n",
 576                        __func__);
 577                 return -EINVAL;
 578         }
 579
 580         host->flags |= USE_SDMA;
 581 #endif
 582         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 583                 host->version =
 584                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 585         else
 586                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 587
 588         cfg->name = host->name;
 589 #ifndef CONFIG_DM_MMC
 590         cfg->ops = &sdhci_ops;
 591 #endif
 592
 593         /* Check whether the clock multiplier is supported or not */
 594         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 595                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 596                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 597                                 SDHCI_CLOCK_MUL_SHIFT;
 598         }
 599
 600         if (host->max_clk == 0) {
 601                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 602                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 603                                 SDHCI_CLOCK_BASE_SHIFT;
 604                 else
 605                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 606                                 SDHCI_CLOCK_BASE_SHIFT;
 607                 host->max_clk *= 1000000;
 608                 if (host->clk_mul)
 609                         host->max_clk *= host->clk_mul;
 610         }
 611         if (host->max_clk == 0) {
 612                 printf("%s: Hardware doesn't specify base clock frequency\n",
 613                        __func__);
 614                 return -EINVAL;
 615         }
 616         if (f_max && (f_max < host->max_clk))
 617                 cfg->f_max = f_max;
 618         else
 619                 cfg->f_max = host->max_clk;
 620         if (f_min)
 621                 cfg->f_min = f_min;
 622         else {
 623                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 624                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 625                 else
 626                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 627         }
 628         cfg->voltages = 0;
 629         if (caps & SDHCI_CAN_VDD_330)
 630                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 631         if (caps & SDHCI_CAN_VDD_300)
 632                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 633         if (caps & SDHCI_CAN_VDD_180)
 634                 cfg->voltages |= MMC_VDD_165_195;
 635
 636         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 637                 cfg->voltages |= host->voltages;
 638
 639         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 640
 641         /* Since Host Controller Version3.0 */
 642         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 643                 if (!(caps & SDHCI_CAN_DO_8BIT))
 644                         cfg->host_caps &= ~MMC_MODE_8BIT;
 645         }
 646
 647         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 648                 cfg->host_caps &= ~MMC_MODE_HS;
 649                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 650         }
 651
 652         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 653                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 654
 655         if (!(cfg->voltages & MMC_VDD_165_195) ||
 656             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 657                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 658                             SDHCI_SUPPORT_DDR50);
 659
 660         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 661                       SDHCI_SUPPORT_DDR50))
 662                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 663
 664         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 665                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 666                 /*
 667                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 668                  * field can be promoted to support HS200.
 669                  */
 670                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 671         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 672                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 673         }
 674
 675         if (caps_1 & SDHCI_SUPPORT_DDR50)
 676                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 677
 678         if (host->host_caps)
 679                 cfg->host_caps |= host->host_caps;
 680
 681         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 682
 683         return 0;
 684 }
 685
 686 #ifdef CONFIG_BLK
 687 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 688 {
 689         return mmc_bind(dev, mmc, cfg);
 690 }
 691 #else
 692 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 693 {
 694         int ret;
 695
 696         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 697         if (ret)
 698                 return ret;
 699
 700         host->mmc = mmc_create(&host->cfg, host);
 701         if (host->mmc == NULL) {
 702                 printf("%s: mmc create fail!\n", __func__);
 703                 return -ENOMEM;
 704         }
 705
 706         return 0;
 707 }
 708 #endif