drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <log.h>
  15 #include <malloc.h>
  16 #include <mmc.h>
  17 #include <sdhci.h>
  18 #include <asm/cache.h>
  19 #include <linux/bitops.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <phys2bus.h>
  23 #include <power/regulator.h>
  24
  25 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  26 {
  27         unsigned long timeout;
  28
  29         /* Wait max 100 ms */
  30         timeout = 100;
  31         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  32         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  33                 if (timeout == 0) {
  34                         printf("%s: Reset 0x%x never completed.\n",
  35                                __func__, (int)mask);
  36                         return;
  37                 }
  38                 timeout--;
  39                 udelay(1000);
  40         }
  41 }
  42
  43 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  44 {
  45         int i;
  46         if (cmd->resp_type & MMC_RSP_136) {
  47                 /* CRC is stripped so we need to do some shifting. */
  48                 for (i = 0; i < 4; i++) {
  49                         cmd->response[i] = sdhci_readl(host,
  50                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  51                         if (i != 3)
  52                                 cmd->response[i] |= sdhci_readb(host,
  53                                                 SDHCI_RESPONSE + (3-i)*4-1);
  54                 }
  55         } else {
  56                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  57         }
  58 }
  59
  60 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  61 {
  62         int i;
  63         char *offs;
  64         for (i = 0; i < data->blocksize; i += 4) {
  65                 offs = data->dest + i;
  66                 if (data->flags == MMC_DATA_READ)
  67                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  68                 else
  69                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  70         }
  71 }
  72
  73 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  74 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  75                               int *is_aligned, int trans_bytes)
  76 {
  77         dma_addr_t dma_addr;
  78         unsigned char ctrl;
  79         void *buf;
  80
  81         if (data->flags == MMC_DATA_READ)
  82                 buf = data->dest;
  83         else
  84                 buf = (void *)data->src;
  85
  86         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  87         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  88         if (host->flags & USE_ADMA64)
  89                 ctrl |= SDHCI_CTRL_ADMA64;
  90         else if (host->flags & USE_ADMA)
  91                 ctrl |= SDHCI_CTRL_ADMA32;
  92         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  93
  94         if (host->flags & USE_SDMA &&
  95             (host->force_align_buffer ||
  96              (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
  97               ((unsigned long)buf & 0x7) != 0x0))) {
  98                 *is_aligned = 0;
  99                 if (data->flags != MMC_DATA_READ)
 100                         memcpy(host->align_buffer, buf, trans_bytes);
 101                 buf = host->align_buffer;
 102         }
 103
 104         host->start_addr = dma_map_single(buf, trans_bytes,
 105                                           mmc_get_dma_dir(data));
 106
 107         if (host->flags & USE_SDMA) {
 108                 dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
 109                 sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
 110         }
 111 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 112         else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 113                 sdhci_prepare_adma_table(host->adma_desc_table, data,
 114                                          host->start_addr);
 115
 116                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 117                              SDHCI_ADMA_ADDRESS);
 118                 if (host->flags & USE_ADMA64)
 119                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 120                                      SDHCI_ADMA_ADDRESS_HI);
 121         }
 122 #endif
 123 }
 124 #else
 125 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 126                               int *is_aligned, int trans_bytes)
 127 {}
 128 #endif
 129 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 130 {
 131         dma_addr_t start_addr = host->start_addr;
 132         unsigned int stat, rdy, mask, timeout, block = 0;
 133         bool transfer_done = false;
 134
 135         timeout = 1000000;
 136         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 137         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 138         do {
 139                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 140                 if (stat & SDHCI_INT_ERROR) {
 141                         pr_debug("%s: Error detected in status(0x%X)!\n",
 142                                  __func__, stat);
 143                         return -EIO;
 144                 }
 145                 if (!transfer_done && (stat & rdy)) {
 146                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 147                                 continue;
 148                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 149                         sdhci_transfer_pio(host, data);
 150                         data->dest += data->blocksize;
 151                         if (++block >= data->blocks) {
 152                                 /* Keep looping until the SDHCI_INT_DATA_END is
 153                                  * cleared, even if we finished sending all the
 154                                  * blocks.
 155                                  */
 156                                 transfer_done = true;
 157                                 continue;
 158                         }
 159                 }
 160                 if ((host->flags & USE_DMA) && !transfer_done &&
 161                     (stat & SDHCI_INT_DMA_END)) {
 162                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 163                         if (host->flags & USE_SDMA) {
 164                                 start_addr &=
 165                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 166                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 167                                 start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
 168                                                              start_addr);
 169                                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 170                         }
 171                 }
 172                 if (timeout-- > 0)
 173                         udelay(10);
 174                 else {
 175                         printf("%s: Transfer data timeout\n", __func__);
 176                         return -ETIMEDOUT;
 177                 }
 178         } while (!(stat & SDHCI_INT_DATA_END));
 179
 180 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 181         dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
 182                          mmc_get_dma_dir(data));
 183 #endif
 184
 185         return 0;
 186 }
 187
 188 /*
 189  * No command will be sent by driver if card is busy, so driver must wait
 190  * for card ready state.
 191  * Every time when card is busy after timeout then (last) timeout value will be
 192  * increased twice but only if it doesn't exceed global defined maximum.
 193  * Each function call will use last timeout value.
 194  */
 195 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 196 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 197 #define SDHCI_READ_STATUS_TIMEOUT               1000
 198
 199 #ifdef CONFIG_DM_MMC
 200 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 201                               struct mmc_data *data)
 202 {
 203         struct mmc *mmc = mmc_get_mmc_dev(dev);
 204
 205 #else
 206 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 207                               struct mmc_data *data)
 208 {
 209 #endif
 210         struct sdhci_host *host = mmc->priv;
 211         unsigned int stat = 0;
 212         int ret = 0;
 213         int trans_bytes = 0, is_aligned = 1;
 214         u32 mask, flags, mode = 0;
 215         unsigned int time = 0;
 216         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 217         ulong start = get_timer(0);
 218
 219         host->start_addr = 0;
 220         /* Timeout unit - ms */
 221         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 222
 223         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 224
 225         /* We shouldn't wait for data inihibit for stop commands, even
 226            though they might use busy signaling */
 227         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 228             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 229               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 230                 mask &= ~SDHCI_DATA_INHIBIT;
 231
 232         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 233                 if (time >= cmd_timeout) {
 234                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 235                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 236                                 cmd_timeout += cmd_timeout;
 237                                 printf("timeout increasing to: %u ms.\n",
 238                                        cmd_timeout);
 239                         } else {
 240                                 puts("timeout.\n");
 241                                 return -ECOMM;
 242                         }
 243                 }
 244                 time++;
 245                 udelay(1000);
 246         }
 247
 248         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 249
 250         mask = SDHCI_INT_RESPONSE;
 251         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 252              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 253                 mask = SDHCI_INT_DATA_AVAIL;
 254
 255         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 256                 flags = SDHCI_CMD_RESP_NONE;
 257         else if (cmd->resp_type & MMC_RSP_136)
 258                 flags = SDHCI_CMD_RESP_LONG;
 259         else if (cmd->resp_type & MMC_RSP_BUSY) {
 260                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 261                 mask |= SDHCI_INT_DATA_END;
 262         } else
 263                 flags = SDHCI_CMD_RESP_SHORT;
 264
 265         if (cmd->resp_type & MMC_RSP_CRC)
 266                 flags |= SDHCI_CMD_CRC;
 267         if (cmd->resp_type & MMC_RSP_OPCODE)
 268                 flags |= SDHCI_CMD_INDEX;
 269         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 270             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 271                 flags |= SDHCI_CMD_DATA;
 272
 273         /* Set Transfer mode regarding to data flag */
 274         if (data) {
 275                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 276
 277                 if (!(host->quirks & SDHCI_QUIRK_SUPPORT_SINGLE))
 278                         mode = SDHCI_TRNS_BLK_CNT_EN;
 279                 trans_bytes = data->blocks * data->blocksize;
 280                 if (data->blocks > 1)
 281                         mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
 282
 283                 if (data->flags == MMC_DATA_READ)
 284                         mode |= SDHCI_TRNS_READ;
 285
 286                 if (host->flags & USE_DMA) {
 287                         mode |= SDHCI_TRNS_DMA;
 288                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 289                 }
 290
 291                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 292                                 data->blocksize),
 293                                 SDHCI_BLOCK_SIZE);
 294                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 295                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 296         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 297                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 298         }
 299
 300         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 301         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 302         start = get_timer(0);
 303         do {
 304                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 305                 if (stat & SDHCI_INT_ERROR)
 306                         break;
 307
 308                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 309                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 310                                 return 0;
 311                         } else {
 312                                 printf("%s: Timeout for status update!\n",
 313                                        __func__);
 314                                 return -ETIMEDOUT;
 315                         }
 316                 }
 317         } while ((stat & mask) != mask);
 318
 319         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 320                 sdhci_cmd_done(host, cmd);
 321                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 322         } else
 323                 ret = -1;
 324
 325         if (!ret && data)
 326                 ret = sdhci_transfer_data(host, data);
 327
 328         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 329                 udelay(1000);
 330
 331         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 332         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 333         if (!ret) {
 334                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 335                                 !is_aligned && (data->flags == MMC_DATA_READ))
 336                         memcpy(data->dest, host->align_buffer, trans_bytes);
 337                 return 0;
 338         }
 339
 340         sdhci_reset(host, SDHCI_RESET_CMD);
 341         sdhci_reset(host, SDHCI_RESET_DATA);
 342         if (stat & SDHCI_INT_TIMEOUT)
 343                 return -ETIMEDOUT;
 344         else
 345                 return -ECOMM;
 346 }
 347
 348 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 349 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 350 {
 351         int err;
 352         struct mmc *mmc = mmc_get_mmc_dev(dev);
 353         struct sdhci_host *host = mmc->priv;
 354
 355         debug("%s\n", __func__);
 356
 357         if (host->ops && host->ops->platform_execute_tuning) {
 358                 err = host->ops->platform_execute_tuning(mmc, opcode);
 359                 if (err)
 360                         return err;
 361                 return 0;
 362         }
 363         return 0;
 364 }
 365 #endif
 366 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 367 {
 368         struct sdhci_host *host = mmc->priv;
 369         unsigned int div, clk = 0, timeout;
 370         int ret;
 371
 372         /* Wait max 20 ms */
 373         timeout = 200;
 374         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 375                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 376                 if (timeout == 0) {
 377                         printf("%s: Timeout to wait cmd & data inhibit\n",
 378                                __func__);
 379                         return -EBUSY;
 380                 }
 381
 382                 timeout--;
 383                 udelay(100);
 384         }
 385
 386         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 387
 388         if (clock == 0)
 389                 return 0;
 390
 391         if (host->ops && host->ops->set_delay) {
 392                 ret = host->ops->set_delay(host);
 393                 if (ret) {
 394                         printf("%s: Error while setting tap delay\n", __func__);
 395                         return ret;
 396                 }
 397         }
 398
 399         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 400                 /*
 401                  * Check if the Host Controller supports Programmable Clock
 402                  * Mode.
 403                  */
 404                 if (host->clk_mul) {
 405                         for (div = 1; div <= 1024; div++) {
 406                                 if ((host->max_clk / div) <= clock)
 407                                         break;
 408                         }
 409
 410                         /*
 411                          * Set Programmable Clock Mode in the Clock
 412                          * Control register.
 413                          */
 414                         clk = SDHCI_PROG_CLOCK_MODE;
 415                         div--;
 416                 } else {
 417                         /* Version 3.00 divisors must be a multiple of 2. */
 418                         if (host->max_clk <= clock) {
 419                                 div = 1;
 420                         } else {
 421                                 for (div = 2;
 422                                      div < SDHCI_MAX_DIV_SPEC_300;
 423                                      div += 2) {
 424                                         if ((host->max_clk / div) <= clock)
 425                                                 break;
 426                                 }
 427                         }
 428                         div >>= 1;
 429                 }
 430         } else {
 431                 /* Version 2.00 divisors must be a power of 2. */
 432                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 433                         if ((host->max_clk / div) <= clock)
 434                                 break;
 435                 }
 436                 div >>= 1;
 437         }
 438
 439         if (host->ops && host->ops->set_clock)
 440                 host->ops->set_clock(host, div);
 441
 442         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 443         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 444                 << SDHCI_DIVIDER_HI_SHIFT;
 445         clk |= SDHCI_CLOCK_INT_EN;
 446         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 447
 448         /* Wait max 20 ms */
 449         timeout = 20;
 450         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 451                 & SDHCI_CLOCK_INT_STABLE)) {
 452                 if (timeout == 0) {
 453                         printf("%s: Internal clock never stabilised.\n",
 454                                __func__);
 455                         return -EBUSY;
 456                 }
 457                 timeout--;
 458                 udelay(1000);
 459         }
 460
 461         clk |= SDHCI_CLOCK_CARD_EN;
 462         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 463         return 0;
 464 }
 465
 466 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 467 {
 468         u8 pwr = 0;
 469
 470         if (power != (unsigned short)-1) {
 471                 switch (1 << power) {
 472                 case MMC_VDD_165_195:
 473                         pwr = SDHCI_POWER_180;
 474                         break;
 475                 case MMC_VDD_29_30:
 476                 case MMC_VDD_30_31:
 477                         pwr = SDHCI_POWER_300;
 478                         break;
 479                 case MMC_VDD_32_33:
 480                 case MMC_VDD_33_34:
 481                         pwr = SDHCI_POWER_330;
 482                         break;
 483                 }
 484         }
 485
 486         if (pwr == 0) {
 487                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 488                 return;
 489         }
 490
 491         pwr |= SDHCI_POWER_ON;
 492
 493         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 494 }
 495
 496 void sdhci_set_uhs_timing(struct sdhci_host *host)
 497 {
 498         struct mmc *mmc = host->mmc;
 499         u32 reg;
 500
 501         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 502         reg &= ~SDHCI_CTRL_UHS_MASK;
 503
 504         switch (mmc->selected_mode) {
 505         case UHS_SDR50:
 506         case MMC_HS_52:
 507                 reg |= SDHCI_CTRL_UHS_SDR50;
 508                 break;
 509         case UHS_DDR50:
 510         case MMC_DDR_52:
 511                 reg |= SDHCI_CTRL_UHS_DDR50;
 512                 break;
 513         case UHS_SDR104:
 514         case MMC_HS_200:
 515                 reg |= SDHCI_CTRL_UHS_SDR104;
 516                 break;
 517         case MMC_HS_400:
 518         case MMC_HS_400_ES:
 519                 reg |= SDHCI_CTRL_HS400;
 520                 break;
 521         default:
 522                 reg |= SDHCI_CTRL_UHS_SDR12;
 523         }
 524
 525         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 526 }
 527
 528 static void sdhci_set_voltage(struct sdhci_host *host)
 529 {
 530         if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
 531                 struct mmc *mmc = (struct mmc *)host->mmc;
 532                 u32 ctrl;
 533
 534                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 535
 536                 switch (mmc->signal_voltage) {
 537                 case MMC_SIGNAL_VOLTAGE_330:
 538 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 539                         if (mmc->vqmmc_supply) {
 540                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
 541                                         pr_err("failed to disable vqmmc-supply\n");
 542                                         return;
 543                                 }
 544
 545                                 if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
 546                                         pr_err("failed to set vqmmc-voltage to 3.3V\n");
 547                                         return;
 548                                 }
 549
 550                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
 551                                         pr_err("failed to enable vqmmc-supply\n");
 552                                         return;
 553                                 }
 554                         }
 555 #endif
 556                         if (IS_SD(mmc)) {
 557                                 ctrl &= ~SDHCI_CTRL_VDD_180;
 558                                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 559                         }
 560
 561                         /* Wait for 5ms */
 562                         mdelay(5);
 563
 564                         /* 3.3V regulator output should be stable within 5 ms */
 565                         if (IS_SD(mmc)) {
 566                                 if (ctrl & SDHCI_CTRL_VDD_180) {
 567                                         pr_err("3.3V regulator output did not become stable\n");
 568                                         return;
 569                                 }
 570                         }
 571
 572                         break;
 573                 case MMC_SIGNAL_VOLTAGE_180:
 574 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 575                         if (mmc->vqmmc_supply) {
 576                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
 577                                         pr_err("failed to disable vqmmc-supply\n");
 578                                         return;
 579                                 }
 580
 581                                 if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
 582                                         pr_err("failed to set vqmmc-voltage to 1.8V\n");
 583                                         return;
 584                                 }
 585
 586                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
 587                                         pr_err("failed to enable vqmmc-supply\n");
 588                                         return;
 589                                 }
 590                         }
 591 #endif
 592                         if (IS_SD(mmc)) {
 593                                 ctrl |= SDHCI_CTRL_VDD_180;
 594                                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 595                         }
 596
 597                         /* Wait for 5 ms */
 598                         mdelay(5);
 599
 600                         /* 1.8V regulator output has to be stable within 5 ms */
 601                         if (IS_SD(mmc)) {
 602                                 if (!(ctrl & SDHCI_CTRL_VDD_180)) {
 603                                         pr_err("1.8V regulator output did not become stable\n");
 604                                         return;
 605                                 }
 606                         }
 607
 608                         break;
 609                 default:
 610                         /* No signal voltage switch required */
 611                         return;
 612                 }
 613         }
 614 }
 615
 616 void sdhci_set_control_reg(struct sdhci_host *host)
 617 {
 618         sdhci_set_voltage(host);
 619         sdhci_set_uhs_timing(host);
 620 }
 621
 622 #ifdef CONFIG_DM_MMC
 623 static int sdhci_set_ios(struct udevice *dev)
 624 {
 625         struct mmc *mmc = mmc_get_mmc_dev(dev);
 626 #else
 627 static int sdhci_set_ios(struct mmc *mmc)
 628 {
 629 #endif
 630         u32 ctrl;
 631         struct sdhci_host *host = mmc->priv;
 632         bool no_hispd_bit = false;
 633
 634         if (host->ops && host->ops->set_control_reg)
 635                 host->ops->set_control_reg(host);
 636
 637         if (mmc->clock != host->clock)
 638                 sdhci_set_clock(mmc, mmc->clock);
 639
 640         if (mmc->clk_disable)
 641                 sdhci_set_clock(mmc, 0);
 642
 643         /* Set bus width */
 644         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 645         if (mmc->bus_width == 8) {
 646                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 647                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 648                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 649                         ctrl |= SDHCI_CTRL_8BITBUS;
 650         } else {
 651                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 652                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 653                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 654                 if (mmc->bus_width == 4)
 655                         ctrl |= SDHCI_CTRL_4BITBUS;
 656                 else
 657                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 658         }
 659
 660         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 661             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
 662                 ctrl &= ~SDHCI_CTRL_HISPD;
 663                 no_hispd_bit = true;
 664         }
 665
 666         if (!no_hispd_bit) {
 667                 if (mmc->selected_mode == MMC_HS ||
 668                     mmc->selected_mode == SD_HS ||
 669                     mmc->selected_mode == MMC_DDR_52 ||
 670                     mmc->selected_mode == MMC_HS_200 ||
 671                     mmc->selected_mode == MMC_HS_400 ||
 672                     mmc->selected_mode == MMC_HS_400_ES ||
 673                     mmc->selected_mode == UHS_SDR25 ||
 674                     mmc->selected_mode == UHS_SDR50 ||
 675                     mmc->selected_mode == UHS_SDR104 ||
 676                     mmc->selected_mode == UHS_DDR50)
 677                         ctrl |= SDHCI_CTRL_HISPD;
 678                 else
 679                         ctrl &= ~SDHCI_CTRL_HISPD;
 680         }
 681
 682         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 683
 684         /* If available, call the driver specific "post" set_ios() function */
 685         if (host->ops && host->ops->set_ios_post)
 686                 return host->ops->set_ios_post(host);
 687
 688         return 0;
 689 }
 690
 691 static int sdhci_init(struct mmc *mmc)
 692 {
 693         struct sdhci_host *host = mmc->priv;
 694 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 695         struct udevice *dev = mmc->dev;
 696
 697         gpio_request_by_name(dev, "cd-gpios", 0,
 698                              &host->cd_gpio, GPIOD_IS_IN);
 699 #endif
 700
 701         sdhci_reset(host, SDHCI_RESET_ALL);
 702
 703 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 704         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 705         /*
 706          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 707          * is defined.
 708          */
 709         host->force_align_buffer = true;
 710 #else
 711         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 712                 host->align_buffer = memalign(8, 512 * 1024);
 713                 if (!host->align_buffer) {
 714                         printf("%s: Aligned buffer alloc failed!!!\n",
 715                                __func__);
 716                         return -ENOMEM;
 717                 }
 718         }
 719 #endif
 720
 721         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 722
 723         if (host->ops && host->ops->get_cd)
 724                 host->ops->get_cd(host);
 725
 726         /* Enable only interrupts served by the SD controller */
 727         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 728                      SDHCI_INT_ENABLE);
 729         /* Mask all sdhci interrupt sources */
 730         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 731
 732         return 0;
 733 }
 734
 735 #ifdef CONFIG_DM_MMC
 736 int sdhci_probe(struct udevice *dev)
 737 {
 738         struct mmc *mmc = mmc_get_mmc_dev(dev);
 739
 740         return sdhci_init(mmc);
 741 }
 742
 743 static int sdhci_deferred_probe(struct udevice *dev)
 744 {
 745         int err;
 746         struct mmc *mmc = mmc_get_mmc_dev(dev);
 747         struct sdhci_host *host = mmc->priv;
 748
 749         if (host->ops && host->ops->deferred_probe) {
 750                 err = host->ops->deferred_probe(host);
 751                 if (err)
 752                         return err;
 753         }
 754         return 0;
 755 }
 756
 757 static int sdhci_get_cd(struct udevice *dev)
 758 {
 759         struct mmc *mmc = mmc_get_mmc_dev(dev);
 760         struct sdhci_host *host = mmc->priv;
 761         int value;
 762
 763         /* If nonremovable, assume that the card is always present. */
 764         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 765                 return 1;
 766         /* If polling, assume that the card is always present. */
 767         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 768                 return 1;
 769
 770 #if CONFIG_IS_ENABLED(DM_GPIO)
 771         value = dm_gpio_get_value(&host->cd_gpio);
 772         if (value >= 0) {
 773                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 774                         return !value;
 775                 else
 776                         return value;
 777         }
 778 #endif
 779         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 780                    SDHCI_CARD_PRESENT);
 781         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 782                 return !value;
 783         else
 784                 return value;
 785 }
 786
 787 static int sdhci_wait_dat0(struct udevice *dev, int state,
 788                            int timeout_us)
 789 {
 790         int tmp;
 791         struct mmc *mmc = mmc_get_mmc_dev(dev);
 792         struct sdhci_host *host = mmc->priv;
 793         unsigned long timeout = timer_get_us() + timeout_us;
 794
 795         // readx_poll_timeout is unsuitable because sdhci_readl accepts
 796         // two arguments
 797         do {
 798                 tmp = sdhci_readl(host, SDHCI_PRESENT_STATE);
 799                 if (!!(tmp & SDHCI_DATA_0_LVL_MASK) == !!state)
 800                         return 0;
 801         } while (!timeout_us || !time_after(timer_get_us(), timeout));
 802
 803         return -ETIMEDOUT;
 804 }
 805
 806 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 807 static int sdhci_set_enhanced_strobe(struct udevice *dev)
 808 {
 809         struct mmc *mmc = mmc_get_mmc_dev(dev);
 810         struct sdhci_host *host = mmc->priv;
 811
 812         if (host->ops && host->ops->set_enhanced_strobe)
 813                 return host->ops->set_enhanced_strobe(host);
 814
 815         return -ENOTSUPP;
 816 }
 817 #endif
 818
 819 const struct dm_mmc_ops sdhci_ops = {
 820         .send_cmd       = sdhci_send_command,
 821         .set_ios        = sdhci_set_ios,
 822         .get_cd         = sdhci_get_cd,
 823         .deferred_probe = sdhci_deferred_probe,
 824 #ifdef MMC_SUPPORTS_TUNING
 825         .execute_tuning = sdhci_execute_tuning,
 826 #endif
 827         .wait_dat0      = sdhci_wait_dat0,
 828 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 829         .set_enhanced_strobe = sdhci_set_enhanced_strobe,
 830 #endif
 831 };
 832 #else
 833 static const struct mmc_ops sdhci_ops = {
 834         .send_cmd       = sdhci_send_command,
 835         .set_ios        = sdhci_set_ios,
 836         .init           = sdhci_init,
 837 };
 838 #endif
 839
 840 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 841                 u32 f_max, u32 f_min)
 842 {
 843         u32 caps, caps_1 = 0;
 844 #if CONFIG_IS_ENABLED(DM_MMC)
 845         u64 dt_caps, dt_caps_mask;
 846
 847         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 848                                             "sdhci-caps-mask", 0);
 849         dt_caps = dev_read_u64_default(host->mmc->dev,
 850                                        "sdhci-caps", 0);
 851         caps = ~lower_32_bits(dt_caps_mask) &
 852                sdhci_readl(host, SDHCI_CAPABILITIES);
 853         caps |= lower_32_bits(dt_caps);
 854 #else
 855         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 856 #endif
 857         debug("%s, caps: 0x%x\n", __func__, caps);
 858
 859 #ifdef CONFIG_MMC_SDHCI_SDMA
 860         if ((caps & SDHCI_CAN_DO_SDMA)) {
 861                 host->flags |= USE_SDMA;
 862         } else {
 863                 debug("%s: Your controller doesn't support SDMA!!\n",
 864                       __func__);
 865         }
 866 #endif
 867 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 868         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 869                 printf("%s: Your controller doesn't support SDMA!!\n",
 870                        __func__);
 871                 return -EINVAL;
 872         }
 873         host->adma_desc_table = sdhci_adma_init();
 874         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 875
 876 #ifdef CONFIG_DMA_ADDR_T_64BIT
 877         host->flags |= USE_ADMA64;
 878 #else
 879         host->flags |= USE_ADMA;
 880 #endif
 881 #endif
 882         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 883                 host->version =
 884                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 885         else
 886                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 887
 888         cfg->name = host->name;
 889 #ifndef CONFIG_DM_MMC
 890         cfg->ops = &sdhci_ops;
 891 #endif
 892
 893         /* Check whether the clock multiplier is supported or not */
 894         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 895 #if CONFIG_IS_ENABLED(DM_MMC)
 896                 caps_1 = ~upper_32_bits(dt_caps_mask) &
 897                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 898                 caps_1 |= upper_32_bits(dt_caps);
 899 #else
 900                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 901 #endif
 902                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 903                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 904                                 SDHCI_CLOCK_MUL_SHIFT;
 905         }
 906
 907         if (host->max_clk == 0) {
 908                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 909                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 910                                 SDHCI_CLOCK_BASE_SHIFT;
 911                 else
 912                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 913                                 SDHCI_CLOCK_BASE_SHIFT;
 914                 host->max_clk *= 1000000;
 915                 if (host->clk_mul)
 916                         host->max_clk *= host->clk_mul;
 917         }
 918         if (host->max_clk == 0) {
 919                 printf("%s: Hardware doesn't specify base clock frequency\n",
 920                        __func__);
 921                 return -EINVAL;
 922         }
 923         if (f_max && (f_max < host->max_clk))
 924                 cfg->f_max = f_max;
 925         else
 926                 cfg->f_max = host->max_clk;
 927         if (f_min)
 928                 cfg->f_min = f_min;
 929         else {
 930                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 931                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 932                 else
 933                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 934         }
 935         cfg->voltages = 0;
 936         if (caps & SDHCI_CAN_VDD_330)
 937                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 938         if (caps & SDHCI_CAN_VDD_300)
 939                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 940         if (caps & SDHCI_CAN_VDD_180)
 941                 cfg->voltages |= MMC_VDD_165_195;
 942
 943         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 944                 cfg->voltages |= host->voltages;
 945
 946         if (caps & SDHCI_CAN_DO_HISPD)
 947                 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 948
 949         cfg->host_caps |= MMC_MODE_4BIT;
 950
 951         /* Since Host Controller Version3.0 */
 952         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 953                 if (!(caps & SDHCI_CAN_DO_8BIT))
 954                         cfg->host_caps &= ~MMC_MODE_8BIT;
 955         }
 956
 957         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 958                 cfg->host_caps &= ~MMC_MODE_HS;
 959                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 960         }
 961
 962         if (!(cfg->voltages & MMC_VDD_165_195) ||
 963             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 964                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 965                             SDHCI_SUPPORT_DDR50);
 966
 967         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 968                       SDHCI_SUPPORT_DDR50))
 969                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 970
 971         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 972                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 973                 /*
 974                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 975                  * field can be promoted to support HS200.
 976                  */
 977                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 978         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 979                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 980         }
 981
 982         if (caps_1 & SDHCI_SUPPORT_DDR50)
 983                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 984
 985         if (host->host_caps)
 986                 cfg->host_caps |= host->host_caps;
 987
 988         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 989
 990         return 0;
 991 }
 992
 993 #ifdef CONFIG_BLK
 994 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 995 {
 996         return mmc_bind(dev, mmc, cfg);
 997 }
 998 #else
 999 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
1000 {
1001         int ret;
1002
1003         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
1004         if (ret)
1005                 return ret;
1006
1007         host->mmc = mmc_create(&host->cfg, host);
1008         if (host->mmc == NULL) {
1009                 printf("%s: mmc create fail!\n", __func__);
1010                 return -ENOMEM;
1011         }
1012
1013         return 0;
1014 }
1015 #endif