1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
16 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
17 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
22 static void sdhci_reset(struct sdhci_host *host, u8 mask)
24 unsigned long timeout;
28 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
29 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
31 printf("%s: Reset 0x%x never completed.\n",
40 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
43 if (cmd->resp_type & MMC_RSP_136) {
44 /* CRC is stripped so we need to do some shifting. */
45 for (i = 0; i < 4; i++) {
46 cmd->response[i] = sdhci_readl(host,
47 SDHCI_RESPONSE + (3-i)*4) << 8;
49 cmd->response[i] |= sdhci_readb(host,
50 SDHCI_RESPONSE + (3-i)*4-1);
53 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
57 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
61 for (i = 0; i < data->blocksize; i += 4) {
62 offs = data->dest + i;
63 if (data->flags == MMC_DATA_READ)
64 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
66 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
70 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
71 unsigned int start_addr)
73 unsigned int stat, rdy, mask, timeout, block = 0;
74 bool transfer_done = false;
75 #ifdef CONFIG_MMC_SDHCI_SDMA
77 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
78 ctrl &= ~SDHCI_CTRL_DMA_MASK;
79 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
83 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
84 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
86 stat = sdhci_readl(host, SDHCI_INT_STATUS);
87 if (stat & SDHCI_INT_ERROR) {
88 pr_debug("%s: Error detected in status(0x%X)!\n",
92 if (!transfer_done && (stat & rdy)) {
93 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
95 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
96 sdhci_transfer_pio(host, data);
97 data->dest += data->blocksize;
98 if (++block >= data->blocks) {
99 /* Keep looping until the SDHCI_INT_DATA_END is
100 * cleared, even if we finished sending all the
103 transfer_done = true;
107 #ifdef CONFIG_MMC_SDHCI_SDMA
108 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
109 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
110 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
111 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
112 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
118 printf("%s: Transfer data timeout\n", __func__);
121 } while (!(stat & SDHCI_INT_DATA_END));
126 * No command will be sent by driver if card is busy, so driver must wait
127 * for card ready state.
128 * Every time when card is busy after timeout then (last) timeout value will be
129 * increased twice but only if it doesn't exceed global defined maximum.
130 * Each function call will use last timeout value.
132 #define SDHCI_CMD_MAX_TIMEOUT 3200
133 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
134 #define SDHCI_READ_STATUS_TIMEOUT 1000
137 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
138 struct mmc_data *data)
140 struct mmc *mmc = mmc_get_mmc_dev(dev);
143 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
144 struct mmc_data *data)
147 struct sdhci_host *host = mmc->priv;
148 unsigned int stat = 0;
150 int trans_bytes = 0, is_aligned = 1;
151 u32 mask, flags, mode;
152 unsigned int time = 0, start_addr = 0;
153 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
154 ulong start = get_timer(0);
156 /* Timeout unit - ms */
157 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
159 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
161 /* We shouldn't wait for data inihibit for stop commands, even
162 though they might use busy signaling */
163 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
164 mask &= ~SDHCI_DATA_INHIBIT;
166 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
167 if (time >= cmd_timeout) {
168 printf("%s: MMC: %d busy ", __func__, mmc_dev);
169 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
170 cmd_timeout += cmd_timeout;
171 printf("timeout increasing to: %u ms.\n",
182 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
184 mask = SDHCI_INT_RESPONSE;
185 if (!(cmd->resp_type & MMC_RSP_PRESENT))
186 flags = SDHCI_CMD_RESP_NONE;
187 else if (cmd->resp_type & MMC_RSP_136)
188 flags = SDHCI_CMD_RESP_LONG;
189 else if (cmd->resp_type & MMC_RSP_BUSY) {
190 flags = SDHCI_CMD_RESP_SHORT_BUSY;
192 mask |= SDHCI_INT_DATA_END;
194 flags = SDHCI_CMD_RESP_SHORT;
196 if (cmd->resp_type & MMC_RSP_CRC)
197 flags |= SDHCI_CMD_CRC;
198 if (cmd->resp_type & MMC_RSP_OPCODE)
199 flags |= SDHCI_CMD_INDEX;
201 flags |= SDHCI_CMD_DATA;
203 /* Set Transfer mode regarding to data flag */
205 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
206 mode = SDHCI_TRNS_BLK_CNT_EN;
207 trans_bytes = data->blocks * data->blocksize;
208 if (data->blocks > 1)
209 mode |= SDHCI_TRNS_MULTI;
211 if (data->flags == MMC_DATA_READ)
212 mode |= SDHCI_TRNS_READ;
214 #ifdef CONFIG_MMC_SDHCI_SDMA
215 if (data->flags == MMC_DATA_READ)
216 start_addr = (unsigned long)data->dest;
218 start_addr = (unsigned long)data->src;
219 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
220 (start_addr & 0x7) != 0x0) {
222 start_addr = (unsigned long)aligned_buffer;
223 if (data->flags != MMC_DATA_READ)
224 memcpy(aligned_buffer, data->src, trans_bytes);
227 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
229 * Always use this bounce-buffer when
230 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
233 start_addr = (unsigned long)aligned_buffer;
234 if (data->flags != MMC_DATA_READ)
235 memcpy(aligned_buffer, data->src, trans_bytes);
238 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
239 mode |= SDHCI_TRNS_DMA;
241 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
244 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
245 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
246 } else if (cmd->resp_type & MMC_RSP_BUSY) {
247 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
250 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
251 #ifdef CONFIG_MMC_SDHCI_SDMA
253 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
254 flush_cache(start_addr, trans_bytes);
257 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
258 start = get_timer(0);
260 stat = sdhci_readl(host, SDHCI_INT_STATUS);
261 if (stat & SDHCI_INT_ERROR)
264 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
265 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
268 printf("%s: Timeout for status update!\n",
273 } while ((stat & mask) != mask);
275 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
276 sdhci_cmd_done(host, cmd);
277 sdhci_writel(host, mask, SDHCI_INT_STATUS);
282 ret = sdhci_transfer_data(host, data, start_addr);
284 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
287 stat = sdhci_readl(host, SDHCI_INT_STATUS);
288 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
290 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
291 !is_aligned && (data->flags == MMC_DATA_READ))
292 memcpy(data->dest, aligned_buffer, trans_bytes);
296 sdhci_reset(host, SDHCI_RESET_CMD);
297 sdhci_reset(host, SDHCI_RESET_DATA);
298 if (stat & SDHCI_INT_TIMEOUT)
304 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
306 struct sdhci_host *host = mmc->priv;
307 unsigned int div, clk = 0, timeout;
311 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
312 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
314 printf("%s: Timeout to wait cmd & data inhibit\n",
323 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
328 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
330 * Check if the Host Controller supports Programmable Clock
334 for (div = 1; div <= 1024; div++) {
335 if ((host->max_clk / div) <= clock)
340 * Set Programmable Clock Mode in the Clock
343 clk = SDHCI_PROG_CLOCK_MODE;
346 /* Version 3.00 divisors must be a multiple of 2. */
347 if (host->max_clk <= clock) {
351 div < SDHCI_MAX_DIV_SPEC_300;
353 if ((host->max_clk / div) <= clock)
360 /* Version 2.00 divisors must be a power of 2. */
361 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
362 if ((host->max_clk / div) <= clock)
368 if (host->ops && host->ops->set_clock)
369 host->ops->set_clock(host, div);
371 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
372 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
373 << SDHCI_DIVIDER_HI_SHIFT;
374 clk |= SDHCI_CLOCK_INT_EN;
375 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
379 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
380 & SDHCI_CLOCK_INT_STABLE)) {
382 printf("%s: Internal clock never stabilised.\n",
390 clk |= SDHCI_CLOCK_CARD_EN;
391 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
395 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
399 if (power != (unsigned short)-1) {
400 switch (1 << power) {
401 case MMC_VDD_165_195:
402 pwr = SDHCI_POWER_180;
406 pwr = SDHCI_POWER_300;
410 pwr = SDHCI_POWER_330;
416 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
420 pwr |= SDHCI_POWER_ON;
422 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
426 static int sdhci_set_ios(struct udevice *dev)
428 struct mmc *mmc = mmc_get_mmc_dev(dev);
430 static int sdhci_set_ios(struct mmc *mmc)
434 struct sdhci_host *host = mmc->priv;
436 if (host->ops && host->ops->set_control_reg)
437 host->ops->set_control_reg(host);
439 if (mmc->clock != host->clock)
440 sdhci_set_clock(mmc, mmc->clock);
443 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
444 if (mmc->bus_width == 8) {
445 ctrl &= ~SDHCI_CTRL_4BITBUS;
446 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
447 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
448 ctrl |= SDHCI_CTRL_8BITBUS;
450 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
451 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
452 ctrl &= ~SDHCI_CTRL_8BITBUS;
453 if (mmc->bus_width == 4)
454 ctrl |= SDHCI_CTRL_4BITBUS;
456 ctrl &= ~SDHCI_CTRL_4BITBUS;
459 if (mmc->clock > 26000000)
460 ctrl |= SDHCI_CTRL_HISPD;
462 ctrl &= ~SDHCI_CTRL_HISPD;
464 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
465 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
466 ctrl &= ~SDHCI_CTRL_HISPD;
468 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
470 /* If available, call the driver specific "post" set_ios() function */
471 if (host->ops && host->ops->set_ios_post)
472 host->ops->set_ios_post(host);
477 static int sdhci_init(struct mmc *mmc)
479 struct sdhci_host *host = mmc->priv;
481 sdhci_reset(host, SDHCI_RESET_ALL);
483 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
484 aligned_buffer = memalign(8, 512*1024);
485 if (!aligned_buffer) {
486 printf("%s: Aligned buffer alloc failed!!!\n",
492 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
494 if (host->ops && host->ops->get_cd)
495 host->ops->get_cd(host);
497 /* Enable only interrupts served by the SD controller */
498 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
500 /* Mask all sdhci interrupt sources */
501 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
507 int sdhci_probe(struct udevice *dev)
509 struct mmc *mmc = mmc_get_mmc_dev(dev);
511 return sdhci_init(mmc);
514 const struct dm_mmc_ops sdhci_ops = {
515 .send_cmd = sdhci_send_command,
516 .set_ios = sdhci_set_ios,
519 static const struct mmc_ops sdhci_ops = {
520 .send_cmd = sdhci_send_command,
521 .set_ios = sdhci_set_ios,
526 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
527 u32 f_max, u32 f_min)
531 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
533 #ifdef CONFIG_MMC_SDHCI_SDMA
534 if (!(caps & SDHCI_CAN_DO_SDMA)) {
535 printf("%s: Your controller doesn't support SDMA!!\n",
540 if (host->quirks & SDHCI_QUIRK_REG32_RW)
542 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
544 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
546 cfg->name = host->name;
547 #ifndef CONFIG_DM_MMC
548 cfg->ops = &sdhci_ops;
551 /* Check whether the clock multiplier is supported or not */
552 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
553 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
554 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
555 SDHCI_CLOCK_MUL_SHIFT;
558 if (host->max_clk == 0) {
559 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
560 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
561 SDHCI_CLOCK_BASE_SHIFT;
563 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
564 SDHCI_CLOCK_BASE_SHIFT;
565 host->max_clk *= 1000000;
567 host->max_clk *= host->clk_mul;
569 if (host->max_clk == 0) {
570 printf("%s: Hardware doesn't specify base clock frequency\n",
574 if (f_max && (f_max < host->max_clk))
577 cfg->f_max = host->max_clk;
581 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
582 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
584 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
587 if (caps & SDHCI_CAN_VDD_330)
588 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
589 if (caps & SDHCI_CAN_VDD_300)
590 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
591 if (caps & SDHCI_CAN_VDD_180)
592 cfg->voltages |= MMC_VDD_165_195;
594 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
595 cfg->voltages |= host->voltages;
597 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
599 /* Since Host Controller Version3.0 */
600 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
601 if (!(caps & SDHCI_CAN_DO_8BIT))
602 cfg->host_caps &= ~MMC_MODE_8BIT;
605 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
606 cfg->host_caps &= ~MMC_MODE_HS;
607 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
611 cfg->host_caps |= host->host_caps;
613 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
619 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
621 return mmc_bind(dev, mmc, cfg);
624 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
628 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
632 host->mmc = mmc_create(&host->cfg, host);
633 if (host->mmc == NULL) {
634 printf("%s: mmc create fail!\n", __func__);