drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <mmc.h>
  14 #include <sdhci.h>
  15 #include <dm.h>
  16
  17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  19 #else
  20 void *aligned_buffer;
  21 #endif
  22
  23 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  24 {
  25         unsigned long timeout;
  26
  27         /* Wait max 100 ms */
  28         timeout = 100;
  29         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  30         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  31                 if (timeout == 0) {
  32                         printf("%s: Reset 0x%x never completed.\n",
  33                                __func__, (int)mask);
  34                         return;
  35                 }
  36                 timeout--;
  37                 udelay(1000);
  38         }
  39 }
  40
  41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  42 {
  43         int i;
  44         if (cmd->resp_type & MMC_RSP_136) {
  45                 /* CRC is stripped so we need to do some shifting. */
  46                 for (i = 0; i < 4; i++) {
  47                         cmd->response[i] = sdhci_readl(host,
  48                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  49                         if (i != 3)
  50                                 cmd->response[i] |= sdhci_readb(host,
  51                                                 SDHCI_RESPONSE + (3-i)*4-1);
  52                 }
  53         } else {
  54                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  55         }
  56 }
  57
  58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  59 {
  60         int i;
  61         char *offs;
  62         for (i = 0; i < data->blocksize; i += 4) {
  63                 offs = data->dest + i;
  64                 if (data->flags == MMC_DATA_READ)
  65                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  66                 else
  67                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  68         }
  69 }
  70
  71 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  72 static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len,
  73                             bool end)
  74 {
  75         struct sdhci_adma_desc *desc;
  76         u8 attr;
  77
  78         desc = &host->adma_desc_table[host->desc_slot];
  79
  80         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  81         if (!end)
  82                 host->desc_slot++;
  83         else
  84                 attr |= ADMA_DESC_ATTR_END;
  85
  86         desc->attr = attr;
  87         desc->len = len;
  88         desc->reserved = 0;
  89         desc->addr_lo = (dma_addr_t)buf;
  90 #ifdef CONFIG_DMA_ADDR_T_64BIT
  91         desc->addr_hi = (u64)buf >> 32;
  92 #endif
  93 }
  94
  95 static void sdhci_prepare_adma_table(struct sdhci_host *host,
  96                                      struct mmc_data *data)
  97 {
  98         uint trans_bytes = data->blocksize * data->blocks;
  99         uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
 100         int i = desc_count;
 101         char *buf;
 102
 103         host->desc_slot = 0;
 104
 105         if (data->flags & MMC_DATA_READ)
 106                 buf = data->dest;
 107         else
 108                 buf = (char *)data->src;
 109
 110         while (--i) {
 111                 sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false);
 112                 buf += ADMA_MAX_LEN;
 113                 trans_bytes -= ADMA_MAX_LEN;
 114         }
 115
 116         sdhci_adma_desc(host, buf, trans_bytes, true);
 117
 118         flush_cache((dma_addr_t)host->adma_desc_table,
 119                     ROUND(desc_count * sizeof(struct sdhci_adma_desc),
 120                           ARCH_DMA_MINALIGN));
 121 }
 122 #elif defined(CONFIG_MMC_SDHCI_SDMA)
 123 static void sdhci_prepare_adma_table(struct sdhci_host *host,
 124                                      struct mmc_data *data)
 125 {}
 126 #endif
 127 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 128 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 129                               int *is_aligned, int trans_bytes)
 130 {
 131         unsigned char ctrl;
 132
 133         if (data->flags == MMC_DATA_READ)
 134                 host->start_addr = (dma_addr_t)data->dest;
 135         else
 136                 host->start_addr = (dma_addr_t)data->src;
 137
 138         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 139         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 140         if (host->flags & USE_ADMA64)
 141                 ctrl |= SDHCI_CTRL_ADMA64;
 142         else if (host->flags & USE_ADMA)
 143                 ctrl |= SDHCI_CTRL_ADMA32;
 144         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 145
 146         if (host->flags & USE_SDMA) {
 147                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 148                     (host->start_addr & 0x7) != 0x0) {
 149                         *is_aligned = 0;
 150                         host->start_addr = (unsigned long)aligned_buffer;
 151                         if (data->flags != MMC_DATA_READ)
 152                                 memcpy(aligned_buffer, data->src, trans_bytes);
 153                 }
 154
 155 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 156                 /*
 157                  * Always use this bounce-buffer when
 158                  * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
 159                  */
 160                 *is_aligned = 0;
 161                 host->start_addr = (unsigned long)aligned_buffer;
 162                 if (data->flags != MMC_DATA_READ)
 163                         memcpy(aligned_buffer, data->src, trans_bytes);
 164 #endif
 165                 sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
 166
 167         } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 168                 sdhci_prepare_adma_table(host, data);
 169
 170                 sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS);
 171                 if (host->flags & USE_ADMA64)
 172                         sdhci_writel(host, (u64)host->adma_addr >> 32,
 173                                      SDHCI_ADMA_ADDRESS_HI);
 174         }
 175
 176         flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
 177 }
 178 #else
 179 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 180                               int *is_aligned, int trans_bytes)
 181 {}
 182 #endif
 183 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 184 {
 185         dma_addr_t start_addr = host->start_addr;
 186         unsigned int stat, rdy, mask, timeout, block = 0;
 187         bool transfer_done = false;
 188
 189         timeout = 1000000;
 190         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 191         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 192         do {
 193                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 194                 if (stat & SDHCI_INT_ERROR) {
 195                         pr_debug("%s: Error detected in status(0x%X)!\n",
 196                                  __func__, stat);
 197                         return -EIO;
 198                 }
 199                 if (!transfer_done && (stat & rdy)) {
 200                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 201                                 continue;
 202                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 203                         sdhci_transfer_pio(host, data);
 204                         data->dest += data->blocksize;
 205                         if (++block >= data->blocks) {
 206                                 /* Keep looping until the SDHCI_INT_DATA_END is
 207                                  * cleared, even if we finished sending all the
 208                                  * blocks.
 209                                  */
 210                                 transfer_done = true;
 211                                 continue;
 212                         }
 213                 }
 214                 if ((host->flags & USE_DMA) && !transfer_done &&
 215                     (stat & SDHCI_INT_DMA_END)) {
 216                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 217                         if (host->flags & USE_SDMA) {
 218                                 start_addr &=
 219                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 220                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 221                                 sdhci_writel(host, start_addr,
 222                                              SDHCI_DMA_ADDRESS);
 223                         }
 224                 }
 225                 if (timeout-- > 0)
 226                         udelay(10);
 227                 else {
 228                         printf("%s: Transfer data timeout\n", __func__);
 229                         return -ETIMEDOUT;
 230                 }
 231         } while (!(stat & SDHCI_INT_DATA_END));
 232         return 0;
 233 }
 234
 235 /*
 236  * No command will be sent by driver if card is busy, so driver must wait
 237  * for card ready state.
 238  * Every time when card is busy after timeout then (last) timeout value will be
 239  * increased twice but only if it doesn't exceed global defined maximum.
 240  * Each function call will use last timeout value.
 241  */
 242 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 243 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 244 #define SDHCI_READ_STATUS_TIMEOUT               1000
 245
 246 #ifdef CONFIG_DM_MMC
 247 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 248                               struct mmc_data *data)
 249 {
 250         struct mmc *mmc = mmc_get_mmc_dev(dev);
 251
 252 #else
 253 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 254                               struct mmc_data *data)
 255 {
 256 #endif
 257         struct sdhci_host *host = mmc->priv;
 258         unsigned int stat = 0;
 259         int ret = 0;
 260         int trans_bytes = 0, is_aligned = 1;
 261         u32 mask, flags, mode;
 262         unsigned int time = 0;
 263         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 264         ulong start = get_timer(0);
 265
 266         host->start_addr = 0;
 267         /* Timeout unit - ms */
 268         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 269
 270         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 271
 272         /* We shouldn't wait for data inihibit for stop commands, even
 273            though they might use busy signaling */
 274         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 275             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 276               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 277                 mask &= ~SDHCI_DATA_INHIBIT;
 278
 279         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 280                 if (time >= cmd_timeout) {
 281                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 282                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 283                                 cmd_timeout += cmd_timeout;
 284                                 printf("timeout increasing to: %u ms.\n",
 285                                        cmd_timeout);
 286                         } else {
 287                                 puts("timeout.\n");
 288                                 return -ECOMM;
 289                         }
 290                 }
 291                 time++;
 292                 udelay(1000);
 293         }
 294
 295         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 296
 297         mask = SDHCI_INT_RESPONSE;
 298         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 299              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 300                 mask = SDHCI_INT_DATA_AVAIL;
 301
 302         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 303                 flags = SDHCI_CMD_RESP_NONE;
 304         else if (cmd->resp_type & MMC_RSP_136)
 305                 flags = SDHCI_CMD_RESP_LONG;
 306         else if (cmd->resp_type & MMC_RSP_BUSY) {
 307                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 308                 if (data)
 309                         mask |= SDHCI_INT_DATA_END;
 310         } else
 311                 flags = SDHCI_CMD_RESP_SHORT;
 312
 313         if (cmd->resp_type & MMC_RSP_CRC)
 314                 flags |= SDHCI_CMD_CRC;
 315         if (cmd->resp_type & MMC_RSP_OPCODE)
 316                 flags |= SDHCI_CMD_INDEX;
 317         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 318             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 319                 flags |= SDHCI_CMD_DATA;
 320
 321         /* Set Transfer mode regarding to data flag */
 322         if (data) {
 323                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 324                 mode = SDHCI_TRNS_BLK_CNT_EN;
 325                 trans_bytes = data->blocks * data->blocksize;
 326                 if (data->blocks > 1)
 327                         mode |= SDHCI_TRNS_MULTI;
 328
 329                 if (data->flags == MMC_DATA_READ)
 330                         mode |= SDHCI_TRNS_READ;
 331
 332                 if (host->flags & USE_DMA) {
 333                         mode |= SDHCI_TRNS_DMA;
 334                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 335                 }
 336
 337                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 338                                 data->blocksize),
 339                                 SDHCI_BLOCK_SIZE);
 340                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 341                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 342         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 343                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 344         }
 345
 346         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 347         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 348         start = get_timer(0);
 349         do {
 350                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 351                 if (stat & SDHCI_INT_ERROR)
 352                         break;
 353
 354                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 355                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 356                                 return 0;
 357                         } else {
 358                                 printf("%s: Timeout for status update!\n",
 359                                        __func__);
 360                                 return -ETIMEDOUT;
 361                         }
 362                 }
 363         } while ((stat & mask) != mask);
 364
 365         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 366                 sdhci_cmd_done(host, cmd);
 367                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 368         } else
 369                 ret = -1;
 370
 371         if (!ret && data)
 372                 ret = sdhci_transfer_data(host, data);
 373
 374         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 375                 udelay(1000);
 376
 377         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 378         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 379         if (!ret) {
 380                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 381                                 !is_aligned && (data->flags == MMC_DATA_READ))
 382                         memcpy(data->dest, aligned_buffer, trans_bytes);
 383                 return 0;
 384         }
 385
 386         sdhci_reset(host, SDHCI_RESET_CMD);
 387         sdhci_reset(host, SDHCI_RESET_DATA);
 388         if (stat & SDHCI_INT_TIMEOUT)
 389                 return -ETIMEDOUT;
 390         else
 391                 return -ECOMM;
 392 }
 393
 394 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 395 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 396 {
 397         int err;
 398         struct mmc *mmc = mmc_get_mmc_dev(dev);
 399         struct sdhci_host *host = mmc->priv;
 400
 401         debug("%s\n", __func__);
 402
 403         if (host->ops && host->ops->platform_execute_tuning) {
 404                 err = host->ops->platform_execute_tuning(mmc, opcode);
 405                 if (err)
 406                         return err;
 407                 return 0;
 408         }
 409         return 0;
 410 }
 411 #endif
 412 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 413 {
 414         struct sdhci_host *host = mmc->priv;
 415         unsigned int div, clk = 0, timeout;
 416
 417         /* Wait max 20 ms */
 418         timeout = 200;
 419         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 420                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 421                 if (timeout == 0) {
 422                         printf("%s: Timeout to wait cmd & data inhibit\n",
 423                                __func__);
 424                         return -EBUSY;
 425                 }
 426
 427                 timeout--;
 428                 udelay(100);
 429         }
 430
 431         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 432
 433         if (clock == 0)
 434                 return 0;
 435
 436         if (host->ops && host->ops->set_delay)
 437                 host->ops->set_delay(host);
 438
 439         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 440                 /*
 441                  * Check if the Host Controller supports Programmable Clock
 442                  * Mode.
 443                  */
 444                 if (host->clk_mul) {
 445                         for (div = 1; div <= 1024; div++) {
 446                                 if ((host->max_clk / div) <= clock)
 447                                         break;
 448                         }
 449
 450                         /*
 451                          * Set Programmable Clock Mode in the Clock
 452                          * Control register.
 453                          */
 454                         clk = SDHCI_PROG_CLOCK_MODE;
 455                         div--;
 456                 } else {
 457                         /* Version 3.00 divisors must be a multiple of 2. */
 458                         if (host->max_clk <= clock) {
 459                                 div = 1;
 460                         } else {
 461                                 for (div = 2;
 462                                      div < SDHCI_MAX_DIV_SPEC_300;
 463                                      div += 2) {
 464                                         if ((host->max_clk / div) <= clock)
 465                                                 break;
 466                                 }
 467                         }
 468                         div >>= 1;
 469                 }
 470         } else {
 471                 /* Version 2.00 divisors must be a power of 2. */
 472                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 473                         if ((host->max_clk / div) <= clock)
 474                                 break;
 475                 }
 476                 div >>= 1;
 477         }
 478
 479         if (host->ops && host->ops->set_clock)
 480                 host->ops->set_clock(host, div);
 481
 482         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 483         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 484                 << SDHCI_DIVIDER_HI_SHIFT;
 485         clk |= SDHCI_CLOCK_INT_EN;
 486         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 487
 488         /* Wait max 20 ms */
 489         timeout = 20;
 490         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 491                 & SDHCI_CLOCK_INT_STABLE)) {
 492                 if (timeout == 0) {
 493                         printf("%s: Internal clock never stabilised.\n",
 494                                __func__);
 495                         return -EBUSY;
 496                 }
 497                 timeout--;
 498                 udelay(1000);
 499         }
 500
 501         clk |= SDHCI_CLOCK_CARD_EN;
 502         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 503         return 0;
 504 }
 505
 506 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 507 {
 508         u8 pwr = 0;
 509
 510         if (power != (unsigned short)-1) {
 511                 switch (1 << power) {
 512                 case MMC_VDD_165_195:
 513                         pwr = SDHCI_POWER_180;
 514                         break;
 515                 case MMC_VDD_29_30:
 516                 case MMC_VDD_30_31:
 517                         pwr = SDHCI_POWER_300;
 518                         break;
 519                 case MMC_VDD_32_33:
 520                 case MMC_VDD_33_34:
 521                         pwr = SDHCI_POWER_330;
 522                         break;
 523                 }
 524         }
 525
 526         if (pwr == 0) {
 527                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 528                 return;
 529         }
 530
 531         pwr |= SDHCI_POWER_ON;
 532
 533         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 534 }
 535
 536 #ifdef CONFIG_DM_MMC
 537 static int sdhci_set_ios(struct udevice *dev)
 538 {
 539         struct mmc *mmc = mmc_get_mmc_dev(dev);
 540 #else
 541 static int sdhci_set_ios(struct mmc *mmc)
 542 {
 543 #endif
 544         u32 ctrl;
 545         struct sdhci_host *host = mmc->priv;
 546
 547         if (host->ops && host->ops->set_control_reg)
 548                 host->ops->set_control_reg(host);
 549
 550         if (mmc->clock != host->clock)
 551                 sdhci_set_clock(mmc, mmc->clock);
 552
 553         if (mmc->clk_disable)
 554                 sdhci_set_clock(mmc, 0);
 555
 556         /* Set bus width */
 557         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 558         if (mmc->bus_width == 8) {
 559                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 560                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 561                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 562                         ctrl |= SDHCI_CTRL_8BITBUS;
 563         } else {
 564                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 565                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 566                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 567                 if (mmc->bus_width == 4)
 568                         ctrl |= SDHCI_CTRL_4BITBUS;
 569                 else
 570                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 571         }
 572
 573         if (mmc->clock > 26000000)
 574                 ctrl |= SDHCI_CTRL_HISPD;
 575         else
 576                 ctrl &= ~SDHCI_CTRL_HISPD;
 577
 578         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 579             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 580                 ctrl &= ~SDHCI_CTRL_HISPD;
 581
 582         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 583
 584         /* If available, call the driver specific "post" set_ios() function */
 585         if (host->ops && host->ops->set_ios_post)
 586                 host->ops->set_ios_post(host);
 587
 588         return 0;
 589 }
 590
 591 static int sdhci_init(struct mmc *mmc)
 592 {
 593         struct sdhci_host *host = mmc->priv;
 594 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 595         struct udevice *dev = mmc->dev;
 596
 597         gpio_request_by_name(dev, "cd-gpio", 0,
 598                              &host->cd_gpio, GPIOD_IS_IN);
 599 #endif
 600
 601         sdhci_reset(host, SDHCI_RESET_ALL);
 602
 603         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 604                 aligned_buffer = memalign(8, 512*1024);
 605                 if (!aligned_buffer) {
 606                         printf("%s: Aligned buffer alloc failed!!!\n",
 607                                __func__);
 608                         return -ENOMEM;
 609                 }
 610         }
 611
 612         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 613
 614         if (host->ops && host->ops->get_cd)
 615                 host->ops->get_cd(host);
 616
 617         /* Enable only interrupts served by the SD controller */
 618         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 619                      SDHCI_INT_ENABLE);
 620         /* Mask all sdhci interrupt sources */
 621         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 622
 623         return 0;
 624 }
 625
 626 #ifdef CONFIG_DM_MMC
 627 int sdhci_probe(struct udevice *dev)
 628 {
 629         struct mmc *mmc = mmc_get_mmc_dev(dev);
 630
 631         return sdhci_init(mmc);
 632 }
 633
 634 int sdhci_get_cd(struct udevice *dev)
 635 {
 636         struct mmc *mmc = mmc_get_mmc_dev(dev);
 637         struct sdhci_host *host = mmc->priv;
 638         int value;
 639
 640         /* If nonremovable, assume that the card is always present. */
 641         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 642                 return 1;
 643         /* If polling, assume that the card is always present. */
 644         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 645                 return 1;
 646
 647 #if CONFIG_IS_ENABLED(DM_GPIO)
 648         value = dm_gpio_get_value(&host->cd_gpio);
 649         if (value >= 0) {
 650                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 651                         return !value;
 652                 else
 653                         return value;
 654         }
 655 #endif
 656         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 657                    SDHCI_CARD_PRESENT);
 658         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 659                 return !value;
 660         else
 661                 return value;
 662 }
 663
 664 const struct dm_mmc_ops sdhci_ops = {
 665         .send_cmd       = sdhci_send_command,
 666         .set_ios        = sdhci_set_ios,
 667         .get_cd         = sdhci_get_cd,
 668 #ifdef MMC_SUPPORTS_TUNING
 669         .execute_tuning = sdhci_execute_tuning,
 670 #endif
 671 };
 672 #else
 673 static const struct mmc_ops sdhci_ops = {
 674         .send_cmd       = sdhci_send_command,
 675         .set_ios        = sdhci_set_ios,
 676         .init           = sdhci_init,
 677 };
 678 #endif
 679
 680 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 681                 u32 f_max, u32 f_min)
 682 {
 683         u32 caps, caps_1 = 0;
 684
 685         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 686
 687 #ifdef CONFIG_MMC_SDHCI_SDMA
 688         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 689                 printf("%s: Your controller doesn't support SDMA!!\n",
 690                        __func__);
 691                 return -EINVAL;
 692         }
 693
 694         host->flags |= USE_SDMA;
 695 #endif
 696 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 697         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 698                 printf("%s: Your controller doesn't support SDMA!!\n",
 699                        __func__);
 700                 return -EINVAL;
 701         }
 702         host->adma_desc_table = (struct sdhci_adma_desc *)
 703                                 memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
 704
 705         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 706 #ifdef CONFIG_DMA_ADDR_T_64BIT
 707         host->flags |= USE_ADMA64;
 708 #else
 709         host->flags |= USE_ADMA;
 710 #endif
 711 #endif
 712         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 713                 host->version =
 714                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 715         else
 716                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 717
 718         cfg->name = host->name;
 719 #ifndef CONFIG_DM_MMC
 720         cfg->ops = &sdhci_ops;
 721 #endif
 722
 723         /* Check whether the clock multiplier is supported or not */
 724         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 725                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 726                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 727                                 SDHCI_CLOCK_MUL_SHIFT;
 728         }
 729
 730         if (host->max_clk == 0) {
 731                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 732                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 733                                 SDHCI_CLOCK_BASE_SHIFT;
 734                 else
 735                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 736                                 SDHCI_CLOCK_BASE_SHIFT;
 737                 host->max_clk *= 1000000;
 738                 if (host->clk_mul)
 739                         host->max_clk *= host->clk_mul;
 740         }
 741         if (host->max_clk == 0) {
 742                 printf("%s: Hardware doesn't specify base clock frequency\n",
 743                        __func__);
 744                 return -EINVAL;
 745         }
 746         if (f_max && (f_max < host->max_clk))
 747                 cfg->f_max = f_max;
 748         else
 749                 cfg->f_max = host->max_clk;
 750         if (f_min)
 751                 cfg->f_min = f_min;
 752         else {
 753                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 754                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 755                 else
 756                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 757         }
 758         cfg->voltages = 0;
 759         if (caps & SDHCI_CAN_VDD_330)
 760                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 761         if (caps & SDHCI_CAN_VDD_300)
 762                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 763         if (caps & SDHCI_CAN_VDD_180)
 764                 cfg->voltages |= MMC_VDD_165_195;
 765
 766         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 767                 cfg->voltages |= host->voltages;
 768
 769         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 770
 771         /* Since Host Controller Version3.0 */
 772         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 773                 if (!(caps & SDHCI_CAN_DO_8BIT))
 774                         cfg->host_caps &= ~MMC_MODE_8BIT;
 775         }
 776
 777         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 778                 cfg->host_caps &= ~MMC_MODE_HS;
 779                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 780         }
 781
 782         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 783                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 784
 785         if (!(cfg->voltages & MMC_VDD_165_195) ||
 786             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 787                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 788                             SDHCI_SUPPORT_DDR50);
 789
 790         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 791                       SDHCI_SUPPORT_DDR50))
 792                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 793
 794         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 795                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 796                 /*
 797                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 798                  * field can be promoted to support HS200.
 799                  */
 800                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 801         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 802                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 803         }
 804
 805         if (caps_1 & SDHCI_SUPPORT_DDR50)
 806                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 807
 808         if (host->host_caps)
 809                 cfg->host_caps |= host->host_caps;
 810
 811         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 812
 813         return 0;
 814 }
 815
 816 #ifdef CONFIG_BLK
 817 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 818 {
 819         return mmc_bind(dev, mmc, cfg);
 820 }
 821 #else
 822 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 823 {
 824         int ret;
 825
 826         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 827         if (ret)
 828                 return ret;
 829
 830         host->mmc = mmc_create(&host->cfg, host);
 831         if (host->mmc == NULL) {
 832                 printf("%s: mmc create fail!\n", __func__);
 833                 return -ENOMEM;
 834         }
 835
 836         return 0;
 837 }
 838 #endif