drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <log.h>
  15 #include <malloc.h>
  16 #include <mmc.h>
  17 #include <sdhci.h>
  18 #include <asm/cache.h>
  19 #include <linux/bitops.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <phys2bus.h>
  23
  24 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  25 {
  26         unsigned long timeout;
  27
  28         /* Wait max 100 ms */
  29         timeout = 100;
  30         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  31         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  32                 if (timeout == 0) {
  33                         printf("%s: Reset 0x%x never completed.\n",
  34                                __func__, (int)mask);
  35                         return;
  36                 }
  37                 timeout--;
  38                 udelay(1000);
  39         }
  40 }
  41
  42 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  43 {
  44         int i;
  45         if (cmd->resp_type & MMC_RSP_136) {
  46                 /* CRC is stripped so we need to do some shifting. */
  47                 for (i = 0; i < 4; i++) {
  48                         cmd->response[i] = sdhci_readl(host,
  49                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  50                         if (i != 3)
  51                                 cmd->response[i] |= sdhci_readb(host,
  52                                                 SDHCI_RESPONSE + (3-i)*4-1);
  53                 }
  54         } else {
  55                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  56         }
  57 }
  58
  59 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  60 {
  61         int i;
  62         char *offs;
  63         for (i = 0; i < data->blocksize; i += 4) {
  64                 offs = data->dest + i;
  65                 if (data->flags == MMC_DATA_READ)
  66                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  67                 else
  68                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  69         }
  70 }
  71
  72 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  73 static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
  74                             u16 len, bool end)
  75 {
  76         struct sdhci_adma_desc *desc;
  77         u8 attr;
  78
  79         desc = &host->adma_desc_table[host->desc_slot];
  80
  81         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  82         if (!end)
  83                 host->desc_slot++;
  84         else
  85                 attr |= ADMA_DESC_ATTR_END;
  86
  87         desc->attr = attr;
  88         desc->len = len;
  89         desc->reserved = 0;
  90         desc->addr_lo = lower_32_bits(dma_addr);
  91 #ifdef CONFIG_DMA_ADDR_T_64BIT
  92         desc->addr_hi = upper_32_bits(dma_addr);
  93 #endif
  94 }
  95
  96 static void sdhci_prepare_adma_table(struct sdhci_host *host,
  97                                      struct mmc_data *data)
  98 {
  99         uint trans_bytes = data->blocksize * data->blocks;
 100         uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
 101         int i = desc_count;
 102         dma_addr_t dma_addr = host->start_addr;
 103
 104         host->desc_slot = 0;
 105
 106         while (--i) {
 107                 sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
 108                 dma_addr += ADMA_MAX_LEN;
 109                 trans_bytes -= ADMA_MAX_LEN;
 110         }
 111
 112         sdhci_adma_desc(host, dma_addr, trans_bytes, true);
 113
 114         flush_cache((dma_addr_t)host->adma_desc_table,
 115                     ROUND(desc_count * sizeof(struct sdhci_adma_desc),
 116                           ARCH_DMA_MINALIGN));
 117 }
 118 #elif defined(CONFIG_MMC_SDHCI_SDMA)
 119 static void sdhci_prepare_adma_table(struct sdhci_host *host,
 120                                      struct mmc_data *data)
 121 {}
 122 #endif
 123 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 124 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 125                               int *is_aligned, int trans_bytes)
 126 {
 127         unsigned char ctrl;
 128         void *buf;
 129
 130         if (data->flags == MMC_DATA_READ)
 131                 buf = data->dest;
 132         else
 133                 buf = (void *)data->src;
 134
 135         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 136         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 137         if (host->flags & USE_ADMA64)
 138                 ctrl |= SDHCI_CTRL_ADMA64;
 139         else if (host->flags & USE_ADMA)
 140                 ctrl |= SDHCI_CTRL_ADMA32;
 141         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 142
 143         if (host->flags & USE_SDMA &&
 144             (host->force_align_buffer ||
 145              (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
 146               ((unsigned long)buf & 0x7) != 0x0))) {
 147                 *is_aligned = 0;
 148                 if (data->flags != MMC_DATA_READ)
 149                         memcpy(host->align_buffer, buf, trans_bytes);
 150                 buf = host->align_buffer;
 151         }
 152
 153         host->start_addr = dma_map_single(buf, trans_bytes,
 154                                           mmc_get_dma_dir(data));
 155
 156         if (host->flags & USE_SDMA) {
 157                 sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
 158                                 SDHCI_DMA_ADDRESS);
 159         } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 160                 sdhci_prepare_adma_table(host, data);
 161
 162                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 163                              SDHCI_ADMA_ADDRESS);
 164                 if (host->flags & USE_ADMA64)
 165                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 166                                      SDHCI_ADMA_ADDRESS_HI);
 167         }
 168 }
 169 #else
 170 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 171                               int *is_aligned, int trans_bytes)
 172 {}
 173 #endif
 174 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 175 {
 176         dma_addr_t start_addr = host->start_addr;
 177         unsigned int stat, rdy, mask, timeout, block = 0;
 178         bool transfer_done = false;
 179
 180         timeout = 1000000;
 181         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 182         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 183         do {
 184                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 185                 if (stat & SDHCI_INT_ERROR) {
 186                         pr_debug("%s: Error detected in status(0x%X)!\n",
 187                                  __func__, stat);
 188                         return -EIO;
 189                 }
 190                 if (!transfer_done && (stat & rdy)) {
 191                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 192                                 continue;
 193                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 194                         sdhci_transfer_pio(host, data);
 195                         data->dest += data->blocksize;
 196                         if (++block >= data->blocks) {
 197                                 /* Keep looping until the SDHCI_INT_DATA_END is
 198                                  * cleared, even if we finished sending all the
 199                                  * blocks.
 200                                  */
 201                                 transfer_done = true;
 202                                 continue;
 203                         }
 204                 }
 205                 if ((host->flags & USE_DMA) && !transfer_done &&
 206                     (stat & SDHCI_INT_DMA_END)) {
 207                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 208                         if (host->flags & USE_SDMA) {
 209                                 start_addr &=
 210                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 211                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 212                                 sdhci_writel(host, phys_to_bus((ulong)start_addr),
 213                                              SDHCI_DMA_ADDRESS);
 214                         }
 215                 }
 216                 if (timeout-- > 0)
 217                         udelay(10);
 218                 else {
 219                         printf("%s: Transfer data timeout\n", __func__);
 220                         return -ETIMEDOUT;
 221                 }
 222         } while (!(stat & SDHCI_INT_DATA_END));
 223
 224         dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
 225                          mmc_get_dma_dir(data));
 226
 227         return 0;
 228 }
 229
 230 /*
 231  * No command will be sent by driver if card is busy, so driver must wait
 232  * for card ready state.
 233  * Every time when card is busy after timeout then (last) timeout value will be
 234  * increased twice but only if it doesn't exceed global defined maximum.
 235  * Each function call will use last timeout value.
 236  */
 237 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 238 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 239 #define SDHCI_READ_STATUS_TIMEOUT               1000
 240
 241 #ifdef CONFIG_DM_MMC
 242 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 243                               struct mmc_data *data)
 244 {
 245         struct mmc *mmc = mmc_get_mmc_dev(dev);
 246
 247 #else
 248 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 249                               struct mmc_data *data)
 250 {
 251 #endif
 252         struct sdhci_host *host = mmc->priv;
 253         unsigned int stat = 0;
 254         int ret = 0;
 255         int trans_bytes = 0, is_aligned = 1;
 256         u32 mask, flags, mode;
 257         unsigned int time = 0;
 258         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 259         ulong start = get_timer(0);
 260
 261         host->start_addr = 0;
 262         /* Timeout unit - ms */
 263         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 264
 265         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 266
 267         /* We shouldn't wait for data inihibit for stop commands, even
 268            though they might use busy signaling */
 269         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 270             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 271               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 272                 mask &= ~SDHCI_DATA_INHIBIT;
 273
 274         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 275                 if (time >= cmd_timeout) {
 276                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 277                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 278                                 cmd_timeout += cmd_timeout;
 279                                 printf("timeout increasing to: %u ms.\n",
 280                                        cmd_timeout);
 281                         } else {
 282                                 puts("timeout.\n");
 283                                 return -ECOMM;
 284                         }
 285                 }
 286                 time++;
 287                 udelay(1000);
 288         }
 289
 290         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 291
 292         mask = SDHCI_INT_RESPONSE;
 293         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 294              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 295                 mask = SDHCI_INT_DATA_AVAIL;
 296
 297         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 298                 flags = SDHCI_CMD_RESP_NONE;
 299         else if (cmd->resp_type & MMC_RSP_136)
 300                 flags = SDHCI_CMD_RESP_LONG;
 301         else if (cmd->resp_type & MMC_RSP_BUSY) {
 302                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 303                 if (data)
 304                         mask |= SDHCI_INT_DATA_END;
 305         } else
 306                 flags = SDHCI_CMD_RESP_SHORT;
 307
 308         if (cmd->resp_type & MMC_RSP_CRC)
 309                 flags |= SDHCI_CMD_CRC;
 310         if (cmd->resp_type & MMC_RSP_OPCODE)
 311                 flags |= SDHCI_CMD_INDEX;
 312         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 313             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 314                 flags |= SDHCI_CMD_DATA;
 315
 316         /* Set Transfer mode regarding to data flag */
 317         if (data) {
 318                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 319                 mode = SDHCI_TRNS_BLK_CNT_EN;
 320                 trans_bytes = data->blocks * data->blocksize;
 321                 if (data->blocks > 1)
 322                         mode |= SDHCI_TRNS_MULTI;
 323
 324                 if (data->flags == MMC_DATA_READ)
 325                         mode |= SDHCI_TRNS_READ;
 326
 327                 if (host->flags & USE_DMA) {
 328                         mode |= SDHCI_TRNS_DMA;
 329                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 330                 }
 331
 332                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 333                                 data->blocksize),
 334                                 SDHCI_BLOCK_SIZE);
 335                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 336                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 337         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 338                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 339         }
 340
 341         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 342         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 343         start = get_timer(0);
 344         do {
 345                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 346                 if (stat & SDHCI_INT_ERROR)
 347                         break;
 348
 349                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 350                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 351                                 return 0;
 352                         } else {
 353                                 printf("%s: Timeout for status update!\n",
 354                                        __func__);
 355                                 return -ETIMEDOUT;
 356                         }
 357                 }
 358         } while ((stat & mask) != mask);
 359
 360         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 361                 sdhci_cmd_done(host, cmd);
 362                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 363         } else
 364                 ret = -1;
 365
 366         if (!ret && data)
 367                 ret = sdhci_transfer_data(host, data);
 368
 369         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 370                 udelay(1000);
 371
 372         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 373         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 374         if (!ret) {
 375                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 376                                 !is_aligned && (data->flags == MMC_DATA_READ))
 377                         memcpy(data->dest, host->align_buffer, trans_bytes);
 378                 return 0;
 379         }
 380
 381         sdhci_reset(host, SDHCI_RESET_CMD);
 382         sdhci_reset(host, SDHCI_RESET_DATA);
 383         if (stat & SDHCI_INT_TIMEOUT)
 384                 return -ETIMEDOUT;
 385         else
 386                 return -ECOMM;
 387 }
 388
 389 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 390 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 391 {
 392         int err;
 393         struct mmc *mmc = mmc_get_mmc_dev(dev);
 394         struct sdhci_host *host = mmc->priv;
 395
 396         debug("%s\n", __func__);
 397
 398         if (host->ops && host->ops->platform_execute_tuning) {
 399                 err = host->ops->platform_execute_tuning(mmc, opcode);
 400                 if (err)
 401                         return err;
 402                 return 0;
 403         }
 404         return 0;
 405 }
 406 #endif
 407 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 408 {
 409         struct sdhci_host *host = mmc->priv;
 410         unsigned int div, clk = 0, timeout;
 411
 412         /* Wait max 20 ms */
 413         timeout = 200;
 414         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 415                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 416                 if (timeout == 0) {
 417                         printf("%s: Timeout to wait cmd & data inhibit\n",
 418                                __func__);
 419                         return -EBUSY;
 420                 }
 421
 422                 timeout--;
 423                 udelay(100);
 424         }
 425
 426         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 427
 428         if (clock == 0)
 429                 return 0;
 430
 431         if (host->ops && host->ops->set_delay)
 432                 host->ops->set_delay(host);
 433
 434         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 435                 /*
 436                  * Check if the Host Controller supports Programmable Clock
 437                  * Mode.
 438                  */
 439                 if (host->clk_mul) {
 440                         for (div = 1; div <= 1024; div++) {
 441                                 if ((host->max_clk / div) <= clock)
 442                                         break;
 443                         }
 444
 445                         /*
 446                          * Set Programmable Clock Mode in the Clock
 447                          * Control register.
 448                          */
 449                         clk = SDHCI_PROG_CLOCK_MODE;
 450                         div--;
 451                 } else {
 452                         /* Version 3.00 divisors must be a multiple of 2. */
 453                         if (host->max_clk <= clock) {
 454                                 div = 1;
 455                         } else {
 456                                 for (div = 2;
 457                                      div < SDHCI_MAX_DIV_SPEC_300;
 458                                      div += 2) {
 459                                         if ((host->max_clk / div) <= clock)
 460                                                 break;
 461                                 }
 462                         }
 463                         div >>= 1;
 464                 }
 465         } else {
 466                 /* Version 2.00 divisors must be a power of 2. */
 467                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 468                         if ((host->max_clk / div) <= clock)
 469                                 break;
 470                 }
 471                 div >>= 1;
 472         }
 473
 474         if (host->ops && host->ops->set_clock)
 475                 host->ops->set_clock(host, div);
 476
 477         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 478         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 479                 << SDHCI_DIVIDER_HI_SHIFT;
 480         clk |= SDHCI_CLOCK_INT_EN;
 481         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 482
 483         /* Wait max 20 ms */
 484         timeout = 20;
 485         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 486                 & SDHCI_CLOCK_INT_STABLE)) {
 487                 if (timeout == 0) {
 488                         printf("%s: Internal clock never stabilised.\n",
 489                                __func__);
 490                         return -EBUSY;
 491                 }
 492                 timeout--;
 493                 udelay(1000);
 494         }
 495
 496         clk |= SDHCI_CLOCK_CARD_EN;
 497         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 498         return 0;
 499 }
 500
 501 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 502 {
 503         u8 pwr = 0;
 504
 505         if (power != (unsigned short)-1) {
 506                 switch (1 << power) {
 507                 case MMC_VDD_165_195:
 508                         pwr = SDHCI_POWER_180;
 509                         break;
 510                 case MMC_VDD_29_30:
 511                 case MMC_VDD_30_31:
 512                         pwr = SDHCI_POWER_300;
 513                         break;
 514                 case MMC_VDD_32_33:
 515                 case MMC_VDD_33_34:
 516                         pwr = SDHCI_POWER_330;
 517                         break;
 518                 }
 519         }
 520
 521         if (pwr == 0) {
 522                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 523                 return;
 524         }
 525
 526         pwr |= SDHCI_POWER_ON;
 527
 528         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 529 }
 530
 531 void sdhci_set_uhs_timing(struct sdhci_host *host)
 532 {
 533         struct mmc *mmc = host->mmc;
 534         u32 reg;
 535
 536         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 537         reg &= ~SDHCI_CTRL_UHS_MASK;
 538
 539         switch (mmc->selected_mode) {
 540         case UHS_SDR50:
 541         case MMC_HS_52:
 542                 reg |= SDHCI_CTRL_UHS_SDR50;
 543                 break;
 544         case UHS_DDR50:
 545         case MMC_DDR_52:
 546                 reg |= SDHCI_CTRL_UHS_DDR50;
 547                 break;
 548         case UHS_SDR104:
 549         case MMC_HS_200:
 550                 reg |= SDHCI_CTRL_UHS_SDR104;
 551                 break;
 552         default:
 553                 reg |= SDHCI_CTRL_UHS_SDR12;
 554         }
 555
 556         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 557 }
 558
 559 #ifdef CONFIG_DM_MMC
 560 static int sdhci_set_ios(struct udevice *dev)
 561 {
 562         struct mmc *mmc = mmc_get_mmc_dev(dev);
 563 #else
 564 static int sdhci_set_ios(struct mmc *mmc)
 565 {
 566 #endif
 567         u32 ctrl;
 568         struct sdhci_host *host = mmc->priv;
 569         bool no_hispd_bit = false;
 570
 571         if (host->ops && host->ops->set_control_reg)
 572                 host->ops->set_control_reg(host);
 573
 574         if (mmc->clock != host->clock)
 575                 sdhci_set_clock(mmc, mmc->clock);
 576
 577         if (mmc->clk_disable)
 578                 sdhci_set_clock(mmc, 0);
 579
 580         /* Set bus width */
 581         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 582         if (mmc->bus_width == 8) {
 583                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 584                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 585                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 586                         ctrl |= SDHCI_CTRL_8BITBUS;
 587         } else {
 588                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 589                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 590                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 591                 if (mmc->bus_width == 4)
 592                         ctrl |= SDHCI_CTRL_4BITBUS;
 593                 else
 594                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 595         }
 596
 597         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 598             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
 599                 ctrl &= ~SDHCI_CTRL_HISPD;
 600                 no_hispd_bit = true;
 601         }
 602
 603         if (!no_hispd_bit) {
 604                 if (mmc->selected_mode == MMC_HS ||
 605                     mmc->selected_mode == SD_HS ||
 606                     mmc->selected_mode == MMC_DDR_52 ||
 607                     mmc->selected_mode == MMC_HS_200 ||
 608                     mmc->selected_mode == MMC_HS_400 ||
 609                     mmc->selected_mode == UHS_SDR25 ||
 610                     mmc->selected_mode == UHS_SDR50 ||
 611                     mmc->selected_mode == UHS_SDR104 ||
 612                     mmc->selected_mode == UHS_DDR50)
 613                         ctrl |= SDHCI_CTRL_HISPD;
 614                 else
 615                         ctrl &= ~SDHCI_CTRL_HISPD;
 616         }
 617
 618         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 619
 620         /* If available, call the driver specific "post" set_ios() function */
 621         if (host->ops && host->ops->set_ios_post)
 622                 return host->ops->set_ios_post(host);
 623
 624         return 0;
 625 }
 626
 627 static int sdhci_init(struct mmc *mmc)
 628 {
 629         struct sdhci_host *host = mmc->priv;
 630 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 631         struct udevice *dev = mmc->dev;
 632
 633         gpio_request_by_name(dev, "cd-gpios", 0,
 634                              &host->cd_gpio, GPIOD_IS_IN);
 635 #endif
 636
 637         sdhci_reset(host, SDHCI_RESET_ALL);
 638
 639 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 640         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 641         /*
 642          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 643          * is defined.
 644          */
 645         host->force_align_buffer = true;
 646 #else
 647         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 648                 host->align_buffer = memalign(8, 512 * 1024);
 649                 if (!host->align_buffer) {
 650                         printf("%s: Aligned buffer alloc failed!!!\n",
 651                                __func__);
 652                         return -ENOMEM;
 653                 }
 654         }
 655 #endif
 656
 657         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 658
 659         if (host->ops && host->ops->get_cd)
 660                 host->ops->get_cd(host);
 661
 662         /* Enable only interrupts served by the SD controller */
 663         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 664                      SDHCI_INT_ENABLE);
 665         /* Mask all sdhci interrupt sources */
 666         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 667
 668         return 0;
 669 }
 670
 671 #ifdef CONFIG_DM_MMC
 672 int sdhci_probe(struct udevice *dev)
 673 {
 674         struct mmc *mmc = mmc_get_mmc_dev(dev);
 675
 676         return sdhci_init(mmc);
 677 }
 678
 679 static int sdhci_deferred_probe(struct udevice *dev)
 680 {
 681         int err;
 682         struct mmc *mmc = mmc_get_mmc_dev(dev);
 683         struct sdhci_host *host = mmc->priv;
 684
 685         if (host->ops && host->ops->deferred_probe) {
 686                 err = host->ops->deferred_probe(host);
 687                 if (err)
 688                         return err;
 689         }
 690         return 0;
 691 }
 692
 693 static int sdhci_get_cd(struct udevice *dev)
 694 {
 695         struct mmc *mmc = mmc_get_mmc_dev(dev);
 696         struct sdhci_host *host = mmc->priv;
 697         int value;
 698
 699         /* If nonremovable, assume that the card is always present. */
 700         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 701                 return 1;
 702         /* If polling, assume that the card is always present. */
 703         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 704                 return 1;
 705
 706 #if CONFIG_IS_ENABLED(DM_GPIO)
 707         value = dm_gpio_get_value(&host->cd_gpio);
 708         if (value >= 0) {
 709                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 710                         return !value;
 711                 else
 712                         return value;
 713         }
 714 #endif
 715         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 716                    SDHCI_CARD_PRESENT);
 717         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 718                 return !value;
 719         else
 720                 return value;
 721 }
 722
 723 const struct dm_mmc_ops sdhci_ops = {
 724         .send_cmd       = sdhci_send_command,
 725         .set_ios        = sdhci_set_ios,
 726         .get_cd         = sdhci_get_cd,
 727         .deferred_probe = sdhci_deferred_probe,
 728 #ifdef MMC_SUPPORTS_TUNING
 729         .execute_tuning = sdhci_execute_tuning,
 730 #endif
 731 };
 732 #else
 733 static const struct mmc_ops sdhci_ops = {
 734         .send_cmd       = sdhci_send_command,
 735         .set_ios        = sdhci_set_ios,
 736         .init           = sdhci_init,
 737 };
 738 #endif
 739
 740 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 741                 u32 f_max, u32 f_min)
 742 {
 743         u32 caps, caps_1 = 0;
 744 #if CONFIG_IS_ENABLED(DM_MMC)
 745         u64 dt_caps, dt_caps_mask;
 746
 747         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 748                                             "sdhci-caps-mask", 0);
 749         dt_caps = dev_read_u64_default(host->mmc->dev,
 750                                        "sdhci-caps", 0);
 751         caps = ~(u32)dt_caps_mask &
 752                sdhci_readl(host, SDHCI_CAPABILITIES);
 753         caps |= (u32)dt_caps;
 754 #else
 755         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 756 #endif
 757         debug("%s, caps: 0x%x\n", __func__, caps);
 758
 759 #ifdef CONFIG_MMC_SDHCI_SDMA
 760         if ((caps & SDHCI_CAN_DO_SDMA)) {
 761                 host->flags |= USE_SDMA;
 762         } else {
 763                 debug("%s: Your controller doesn't support SDMA!!\n",
 764                       __func__);
 765         }
 766 #endif
 767 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 768         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 769                 printf("%s: Your controller doesn't support SDMA!!\n",
 770                        __func__);
 771                 return -EINVAL;
 772         }
 773         host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
 774
 775         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 776 #ifdef CONFIG_DMA_ADDR_T_64BIT
 777         host->flags |= USE_ADMA64;
 778 #else
 779         host->flags |= USE_ADMA;
 780 #endif
 781 #endif
 782         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 783                 host->version =
 784                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 785         else
 786                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 787
 788         cfg->name = host->name;
 789 #ifndef CONFIG_DM_MMC
 790         cfg->ops = &sdhci_ops;
 791 #endif
 792
 793         /* Check whether the clock multiplier is supported or not */
 794         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 795 #if CONFIG_IS_ENABLED(DM_MMC)
 796                 caps_1 = ~(u32)(dt_caps_mask >> 32) &
 797                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 798                 caps_1 |= (u32)(dt_caps >> 32);
 799 #else
 800                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 801 #endif
 802                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 803                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 804                                 SDHCI_CLOCK_MUL_SHIFT;
 805         }
 806
 807         if (host->max_clk == 0) {
 808                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 809                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 810                                 SDHCI_CLOCK_BASE_SHIFT;
 811                 else
 812                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 813                                 SDHCI_CLOCK_BASE_SHIFT;
 814                 host->max_clk *= 1000000;
 815                 if (host->clk_mul)
 816                         host->max_clk *= host->clk_mul;
 817         }
 818         if (host->max_clk == 0) {
 819                 printf("%s: Hardware doesn't specify base clock frequency\n",
 820                        __func__);
 821                 return -EINVAL;
 822         }
 823         if (f_max && (f_max < host->max_clk))
 824                 cfg->f_max = f_max;
 825         else
 826                 cfg->f_max = host->max_clk;
 827         if (f_min)
 828                 cfg->f_min = f_min;
 829         else {
 830                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 831                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 832                 else
 833                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 834         }
 835         cfg->voltages = 0;
 836         if (caps & SDHCI_CAN_VDD_330)
 837                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 838         if (caps & SDHCI_CAN_VDD_300)
 839                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 840         if (caps & SDHCI_CAN_VDD_180)
 841                 cfg->voltages |= MMC_VDD_165_195;
 842
 843         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 844                 cfg->voltages |= host->voltages;
 845
 846         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 847
 848         /* Since Host Controller Version3.0 */
 849         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 850                 if (!(caps & SDHCI_CAN_DO_8BIT))
 851                         cfg->host_caps &= ~MMC_MODE_8BIT;
 852         }
 853
 854         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 855                 cfg->host_caps &= ~MMC_MODE_HS;
 856                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 857         }
 858
 859         if (!(cfg->voltages & MMC_VDD_165_195))
 860                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 861                             SDHCI_SUPPORT_DDR50);
 862
 863         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 864                       SDHCI_SUPPORT_DDR50))
 865                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 866
 867         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 868                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 869                 /*
 870                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 871                  * field can be promoted to support HS200.
 872                  */
 873                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 874         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 875                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 876         }
 877
 878         if (caps_1 & SDHCI_SUPPORT_DDR50)
 879                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 880
 881         if (host->host_caps)
 882                 cfg->host_caps |= host->host_caps;
 883
 884         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 885
 886         return 0;
 887 }
 888
 889 #ifdef CONFIG_BLK
 890 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 891 {
 892         return mmc_bind(dev, mmc, cfg);
 893 }
 894 #else
 895 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 896 {
 897         int ret;
 898
 899         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 900         if (ret)
 901                 return ret;
 902
 903         host->mmc = mmc_create(&host->cfg, host);
 904         if (host->mmc == NULL) {
 905                 printf("%s: mmc create fail!\n", __func__);
 906                 return -ENOMEM;
 907         }
 908
 909         return 0;
 910 }
 911 #endif