2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Back ported to the 8xx platform (from the 8260 platform) by
24 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
32 #ifdef CONFIG_MMC_SDMA
33 extern void Dcache_InvalRegion(unsigned int addr, unsigned int length);
34 extern void Dcache_CleanRegion(unsigned int addr, unsigned int length);
38 void sdhci_dumpregs(struct sdhci_host *host);
40 static void sdhci_reset(struct sdhci_host *host, u8 mask)
42 unsigned long timeout;
46 sdhci_writeb(host, mask|SDHCI_HW_RST, SDHCI_SOFTWARE_RESET);
47 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
49 printf("Reset 0x%x never completed.\n", (int)mask);
57 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
60 if (cmd->resp_type & MMC_RSP_136) {
61 /* CRC is stripped so we need to do some shifting. */
62 for (i = 0; i < 4; i++) {
63 cmd->response[i] = sdhci_readl(host,
64 SDHCI_RESPONSE + (3-i)*4) << 8;
66 cmd->response[i] |= sdhci_readb(host,
67 SDHCI_RESPONSE + (3-i)*4-1);
70 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
74 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
78 for (i = 0; i < data->blocksize; i += 4) {
79 offs = data->dest + i;
80 if (data->flags == MMC_DATA_READ) {
81 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
84 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
89 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
90 unsigned int start_addr)
92 unsigned int stat, rdy, mask, timeout, block = 0;
95 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
96 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
99 stat = sdhci_readl(host, SDHCI_INT_STATUS);
100 if (stat & SDHCI_INT_ERROR) {
101 printf("Error detected in status(0x%X)!\n", stat);
105 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
107 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
108 printf("%s start pio\n", __func__);
109 sdhci_transfer_pio(host, data);
110 data->dest += data->blocksize;
111 if (++block >= data->blocks)
114 #ifdef CONFIG_MMC_SDMA
115 if (stat & SDHCI_INT_DMA_END) {
116 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
117 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
118 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
119 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
125 printf("Transfer data timeout\n");
128 } while (!(stat & SDHCI_INT_DATA_END));
132 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
133 struct mmc_data *data)
135 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
136 unsigned int stat = 0;
138 int trans_bytes = 0, is_aligned = 1;
139 u32 mask, flags, mode;
140 unsigned int timeout, start_addr = 0;
145 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
146 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
148 /* We shouldn't wait for data inihibit for stop commands, even
149 though they might use busy signaling */
150 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
151 mask &= ~SDHCI_DATA_INHIBIT;
153 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
155 printf("Controller never released inhibit bit(s).\n");
162 mask = SDHCI_INT_RESPONSE;
163 if (!(cmd->resp_type & MMC_RSP_PRESENT))
164 flags = SDHCI_CMD_RESP_NONE;
165 else if (cmd->resp_type & MMC_RSP_136)
166 flags = SDHCI_CMD_RESP_LONG;
167 else if (cmd->resp_type & MMC_RSP_BUSY) {
168 flags = SDHCI_CMD_RESP_SHORT_BUSY;
169 mask |= SDHCI_INT_DATA_END;
171 flags = SDHCI_CMD_RESP_SHORT;
173 if (cmd->resp_type & MMC_RSP_CRC)
174 flags |= SDHCI_CMD_CRC;
175 if (cmd->resp_type & MMC_RSP_OPCODE)
176 flags |= SDHCI_CMD_INDEX;
178 flags |= SDHCI_CMD_DATA;
180 /*Set Transfer mode regarding to data flag*/
182 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
183 mode = SDHCI_TRNS_BLK_CNT_EN;
184 trans_bytes = data->blocks * data->blocksize;
185 if (data->blocks > 1)
186 mode |= SDHCI_TRNS_MULTI;
188 if (data->flags == MMC_DATA_READ)
189 mode |= SDHCI_TRNS_READ;
191 #ifdef CONFIG_MMC_SDMA
192 if (data->flags == MMC_DATA_READ)
193 start_addr = (unsigned int)data->dest;
195 start_addr = (unsigned int)data->src;
196 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
197 (start_addr & 0x7) != 0x0) {
199 start_addr = (unsigned int)aligned_buffer;
200 if (data->flags != MMC_DATA_READ)
201 memcpy(aligned_buffer, data->src, trans_bytes);
203 Dcache_CleanRegion(start_addr, trans_bytes);
204 Dcache_InvalRegion(start_addr, trans_bytes);
205 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
206 mode |= SDHCI_TRNS_DMA;
208 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
211 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
212 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
215 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
216 #ifdef CONFIG_MMC_SDMA
217 //flush_cache(start_addr, trans_bytes);
219 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
221 stat = sdhci_readl(host, SDHCI_INT_STATUS);
222 if (stat & SDHCI_INT_ERROR)
224 } while ((stat & mask) != mask);
226 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
227 sdhci_cmd_done(host, cmd);
228 sdhci_writel(host, mask, SDHCI_INT_STATUS);
233 ret = sdhci_transfer_data(host, data, start_addr);
235 stat = sdhci_readl(host, SDHCI_INT_STATUS);
236 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
238 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
239 !is_aligned && (data->flags == MMC_DATA_READ))
240 memcpy(data->dest, aligned_buffer, trans_bytes);
244 sdhci_reset(host, SDHCI_RESET_CMD);
245 sdhci_reset(host, SDHCI_RESET_DATA);
246 if (stat & SDHCI_INT_TIMEOUT)
252 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
254 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
255 unsigned int div, clk, timeout;
257 sdhci_sdclk_enable(host, 0);
263 /* Version 2.00 divisors must be a power of 2. */
264 #if defined(CONFIG_TIGER) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
265 for (div = 1; div < 2046; div *= 2)
267 for (div = 1; div < 256; div *= 2)
270 if ((mmc->f_max / div) <= clock)
275 #if defined(CONFIG_TIGER) || defined (CONFIG_SC8830) || (defined CONFIG_SC9630)
279 #if defined (CONFIG_SPX30G)
283 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
284 clk |= SDHCI_CLOCK_INT_EN;
285 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
289 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
290 & SDHCI_CLOCK_INT_STABLE)) {
292 printf("Internal clock never stabilised.\n");
299 clk |= SDHCI_CLOCK_CARD_EN;
300 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
304 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
308 if (power != (unsigned short)-1) {
309 switch (1 << power) {
310 case MMC_VDD_165_195:
311 pwr = SDHCI_POWER_180;
315 pwr = SDHCI_POWER_300;
319 pwr = SDHCI_POWER_330;
325 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
329 pwr |= SDHCI_POWER_ON;
331 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
334 void sdhci_set_ios(struct mmc *mmc)
337 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
339 if (mmc->clock != host->clock)
340 sdhci_set_clock(mmc, mmc->clock);
343 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
344 if (mmc->bus_width == 8) {
345 ctrl &= ~SDHCI_CTRL_4BITBUS;
347 if (mmc->bus_width == 4)
348 ctrl |= SDHCI_CTRL_4BITBUS;
350 ctrl &= ~SDHCI_CTRL_4BITBUS;
353 /* high speed config is not supported on sp8830 */
354 #ifndef CONFIG_SDHCI_CTRL_NO_HISPD
355 if (mmc->clock > 26000000)
356 ctrl |= SDHCI_CTRL_HISPD;
359 ctrl &= ~SDHCI_CTRL_HISPD;
361 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
365 int sdhci_init(struct mmc *mmc)
367 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
369 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
370 aligned_buffer = memalign(8, 512*1024);
371 if (!aligned_buffer) {
372 printf("Aligned buffer alloc failed!!!");
378 /* Eable all state */
379 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE);
380 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE);
382 sdhci_set_power(host, fls(mmc->voltages) - 1);
387 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
392 mmc = malloc(sizeof(struct mmc));
394 printf("mmc malloc fail!\n");
401 sprintf(mmc->name, "%s", host->name);
402 mmc->send_cmd = sdhci_send_command;
403 mmc->set_ios = sdhci_set_ios;
404 mmc->init = sdhci_init;
406 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
407 #ifdef CONFIG_MMC_SDMA
408 if (!(caps & SDHCI_CAN_DO_SDMA)) {
409 printf("Your controller don't support sdma!!\n");
415 mmc->f_max = max_clk;
417 mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
418 >> SDHCI_CLOCK_BASE_SHIFT;
419 mmc->f_max *= 1000000;
421 if (mmc->f_max == 0) {
422 printf("Hardware doesn't specify base clock frequency\n");
426 mmc->f_min = min_clk;
429 if (caps & SDHCI_CAN_VDD_330)
430 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
431 if (caps & SDHCI_CAN_VDD_300)
432 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
433 if (caps & SDHCI_CAN_VDD_180)
434 mmc->voltages |= MMC_VDD_165_195;
435 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
436 sdhci_sdclk_enable(host, 0);
438 sdhci_reset(host, SDHCI_RESET_ALL);