drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <log.h>
  15 #include <malloc.h>
  16 #include <mmc.h>
  17 #include <sdhci.h>
  18 #include <asm/cache.h>
  19 #include <linux/bitops.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <phys2bus.h>
  23 #include <power/regulator.h>
  24
  25 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  26 {
  27         unsigned long timeout;
  28
  29         /* Wait max 100 ms */
  30         timeout = 100;
  31         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  32         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  33                 if (timeout == 0) {
  34                         printf("%s: Reset 0x%x never completed.\n",
  35                                __func__, (int)mask);
  36                         return;
  37                 }
  38                 timeout--;
  39                 udelay(1000);
  40         }
  41 }
  42
  43 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  44 {
  45         int i;
  46         if (cmd->resp_type & MMC_RSP_136) {
  47                 /* CRC is stripped so we need to do some shifting. */
  48                 for (i = 0; i < 4; i++) {
  49                         cmd->response[i] = sdhci_readl(host,
  50                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  51                         if (i != 3)
  52                                 cmd->response[i] |= sdhci_readb(host,
  53                                                 SDHCI_RESPONSE + (3-i)*4-1);
  54                 }
  55         } else {
  56                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  57         }
  58 }
  59
  60 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  61 {
  62         int i;
  63         char *offs;
  64         for (i = 0; i < data->blocksize; i += 4) {
  65                 offs = data->dest + i;
  66                 if (data->flags == MMC_DATA_READ)
  67                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  68                 else
  69                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  70         }
  71 }
  72
  73 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  74 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  75                               int *is_aligned, int trans_bytes)
  76 {
  77         dma_addr_t dma_addr;
  78         unsigned char ctrl;
  79         void *buf;
  80
  81         if (data->flags == MMC_DATA_READ)
  82                 buf = data->dest;
  83         else
  84                 buf = (void *)data->src;
  85
  86         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  87         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  88         if (host->flags & USE_ADMA64)
  89                 ctrl |= SDHCI_CTRL_ADMA64;
  90         else if (host->flags & USE_ADMA)
  91                 ctrl |= SDHCI_CTRL_ADMA32;
  92         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  93
  94         if (host->flags & USE_SDMA &&
  95             (host->force_align_buffer ||
  96              (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
  97               ((unsigned long)buf & 0x7) != 0x0))) {
  98                 *is_aligned = 0;
  99                 if (data->flags != MMC_DATA_READ)
 100                         memcpy(host->align_buffer, buf, trans_bytes);
 101                 buf = host->align_buffer;
 102         }
 103
 104         host->start_addr = dma_map_single(buf, trans_bytes,
 105                                           mmc_get_dma_dir(data));
 106
 107         if (host->flags & USE_SDMA) {
 108                 dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
 109                 sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
 110         }
 111 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 112         else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 113                 sdhci_prepare_adma_table(host->adma_desc_table, data,
 114                                          host->start_addr);
 115
 116                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 117                              SDHCI_ADMA_ADDRESS);
 118                 if (host->flags & USE_ADMA64)
 119                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 120                                      SDHCI_ADMA_ADDRESS_HI);
 121         }
 122 #endif
 123 }
 124 #else
 125 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 126                               int *is_aligned, int trans_bytes)
 127 {}
 128 #endif
 129 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 130 {
 131         dma_addr_t start_addr = host->start_addr;
 132         unsigned int stat, rdy, mask, timeout, block = 0;
 133         bool transfer_done = false;
 134
 135         timeout = 1000000;
 136         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 137         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 138         do {
 139                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 140                 if (stat & SDHCI_INT_ERROR) {
 141                         pr_debug("%s: Error detected in status(0x%X)!\n",
 142                                  __func__, stat);
 143                         return -EIO;
 144                 }
 145                 if (!transfer_done && (stat & rdy)) {
 146                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 147                                 continue;
 148                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 149                         sdhci_transfer_pio(host, data);
 150                         data->dest += data->blocksize;
 151                         if (++block >= data->blocks) {
 152                                 /* Keep looping until the SDHCI_INT_DATA_END is
 153                                  * cleared, even if we finished sending all the
 154                                  * blocks.
 155                                  */
 156                                 transfer_done = true;
 157                                 continue;
 158                         }
 159                 }
 160                 if ((host->flags & USE_DMA) && !transfer_done &&
 161                     (stat & SDHCI_INT_DMA_END)) {
 162                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 163                         if (host->flags & USE_SDMA) {
 164                                 start_addr &=
 165                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 166                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 167                                 start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
 168                                                              start_addr);
 169                                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 170                         }
 171                 }
 172                 if (timeout-- > 0)
 173                         udelay(10);
 174                 else {
 175                         printf("%s: Transfer data timeout\n", __func__);
 176                         return -ETIMEDOUT;
 177                 }
 178         } while (!(stat & SDHCI_INT_DATA_END));
 179
 180 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 181         dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
 182                          mmc_get_dma_dir(data));
 183 #endif
 184
 185         return 0;
 186 }
 187
 188 /*
 189  * No command will be sent by driver if card is busy, so driver must wait
 190  * for card ready state.
 191  * Every time when card is busy after timeout then (last) timeout value will be
 192  * increased twice but only if it doesn't exceed global defined maximum.
 193  * Each function call will use last timeout value.
 194  */
 195 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 196 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 197 #define SDHCI_READ_STATUS_TIMEOUT               1000
 198
 199 #ifdef CONFIG_DM_MMC
 200 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 201                               struct mmc_data *data)
 202 {
 203         struct mmc *mmc = mmc_get_mmc_dev(dev);
 204
 205 #else
 206 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 207                               struct mmc_data *data)
 208 {
 209 #endif
 210         struct sdhci_host *host = mmc->priv;
 211         unsigned int stat = 0;
 212         int ret = 0;
 213         int trans_bytes = 0, is_aligned = 1;
 214         u32 mask, flags, mode = 0;
 215         unsigned int time = 0;
 216         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 217         ulong start = get_timer(0);
 218
 219         host->start_addr = 0;
 220         /* Timeout unit - ms */
 221         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 222
 223         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 224
 225         /* We shouldn't wait for data inihibit for stop commands, even
 226            though they might use busy signaling */
 227         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 228             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 229               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 230                 mask &= ~SDHCI_DATA_INHIBIT;
 231
 232         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 233                 if (time >= cmd_timeout) {
 234                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 235                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 236                                 cmd_timeout += cmd_timeout;
 237                                 printf("timeout increasing to: %u ms.\n",
 238                                        cmd_timeout);
 239                         } else {
 240                                 puts("timeout.\n");
 241                                 return -ECOMM;
 242                         }
 243                 }
 244                 time++;
 245                 udelay(1000);
 246         }
 247
 248         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 249
 250         mask = SDHCI_INT_RESPONSE;
 251         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 252              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 253                 mask = SDHCI_INT_DATA_AVAIL;
 254
 255         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 256                 flags = SDHCI_CMD_RESP_NONE;
 257         else if (cmd->resp_type & MMC_RSP_136)
 258                 flags = SDHCI_CMD_RESP_LONG;
 259         else if (cmd->resp_type & MMC_RSP_BUSY) {
 260                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 261                 mask |= SDHCI_INT_DATA_END;
 262         } else
 263                 flags = SDHCI_CMD_RESP_SHORT;
 264
 265         if (cmd->resp_type & MMC_RSP_CRC)
 266                 flags |= SDHCI_CMD_CRC;
 267         if (cmd->resp_type & MMC_RSP_OPCODE)
 268                 flags |= SDHCI_CMD_INDEX;
 269         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 270             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 271                 flags |= SDHCI_CMD_DATA;
 272
 273         /* Set Transfer mode regarding to data flag */
 274         if (data) {
 275                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 276
 277                 if (!(host->quirks & SDHCI_QUIRK_SUPPORT_SINGLE))
 278                         mode = SDHCI_TRNS_BLK_CNT_EN;
 279                 trans_bytes = data->blocks * data->blocksize;
 280                 if (data->blocks > 1)
 281                         mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
 282
 283                 if (data->flags == MMC_DATA_READ)
 284                         mode |= SDHCI_TRNS_READ;
 285
 286                 if (host->flags & USE_DMA) {
 287                         mode |= SDHCI_TRNS_DMA;
 288                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 289                 }
 290
 291                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 292                                 data->blocksize),
 293                                 SDHCI_BLOCK_SIZE);
 294                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 295                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 296         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 297                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 298         }
 299
 300         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 301         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 302         start = get_timer(0);
 303         do {
 304                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 305                 if (stat & SDHCI_INT_ERROR)
 306                         break;
 307
 308                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 309                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 310                                 return 0;
 311                         } else {
 312                                 printf("%s: Timeout for status update!\n",
 313                                        __func__);
 314                                 return -ETIMEDOUT;
 315                         }
 316                 }
 317         } while ((stat & mask) != mask);
 318
 319         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 320                 sdhci_cmd_done(host, cmd);
 321                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 322         } else
 323                 ret = -1;
 324
 325         if (!ret && data)
 326                 ret = sdhci_transfer_data(host, data);
 327
 328         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 329                 udelay(1000);
 330
 331         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 332         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 333         if (!ret) {
 334                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 335                                 !is_aligned && (data->flags == MMC_DATA_READ))
 336                         memcpy(data->dest, host->align_buffer, trans_bytes);
 337                 return 0;
 338         }
 339
 340         sdhci_reset(host, SDHCI_RESET_CMD);
 341         sdhci_reset(host, SDHCI_RESET_DATA);
 342         if (stat & SDHCI_INT_TIMEOUT)
 343                 return -ETIMEDOUT;
 344         else
 345                 return -ECOMM;
 346 }
 347
 348 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 349 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 350 {
 351         int err;
 352         struct mmc *mmc = mmc_get_mmc_dev(dev);
 353         struct sdhci_host *host = mmc->priv;
 354
 355         debug("%s\n", __func__);
 356
 357         if (host->ops && host->ops->platform_execute_tuning) {
 358                 err = host->ops->platform_execute_tuning(mmc, opcode);
 359                 if (err)
 360                         return err;
 361                 return 0;
 362         }
 363         return 0;
 364 }
 365 #endif
 366 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 367 {
 368         struct sdhci_host *host = mmc->priv;
 369         unsigned int div, clk = 0, timeout;
 370         int ret;
 371
 372         /* Wait max 20 ms */
 373         timeout = 200;
 374         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 375                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 376                 if (timeout == 0) {
 377                         printf("%s: Timeout to wait cmd & data inhibit\n",
 378                                __func__);
 379                         return -EBUSY;
 380                 }
 381
 382                 timeout--;
 383                 udelay(100);
 384         }
 385
 386         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 387
 388         if (clock == 0)
 389                 return 0;
 390
 391         if (host->ops && host->ops->set_delay) {
 392                 ret = host->ops->set_delay(host);
 393                 if (ret) {
 394                         printf("%s: Error while setting tap delay\n", __func__);
 395                         return ret;
 396                 }
 397         }
 398
 399         if (host->ops && host->ops->config_dll) {
 400                 ret = host->ops->config_dll(host, clock, false);
 401                 if (ret) {
 402                         printf("%s: Error while configuring dll\n", __func__);
 403                         return ret;
 404                 }
 405         }
 406
 407         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 408                 /*
 409                  * Check if the Host Controller supports Programmable Clock
 410                  * Mode.
 411                  */
 412                 if (host->clk_mul) {
 413                         for (div = 1; div <= 1024; div++) {
 414                                 if ((host->max_clk / div) <= clock)
 415                                         break;
 416                         }
 417
 418                         /*
 419                          * Set Programmable Clock Mode in the Clock
 420                          * Control register.
 421                          */
 422                         clk = SDHCI_PROG_CLOCK_MODE;
 423                         div--;
 424                 } else {
 425                         /* Version 3.00 divisors must be a multiple of 2. */
 426                         if (host->max_clk <= clock) {
 427                                 div = 1;
 428                         } else {
 429                                 for (div = 2;
 430                                      div < SDHCI_MAX_DIV_SPEC_300;
 431                                      div += 2) {
 432                                         if ((host->max_clk / div) <= clock)
 433                                                 break;
 434                                 }
 435                         }
 436                         div >>= 1;
 437                 }
 438         } else {
 439                 /* Version 2.00 divisors must be a power of 2. */
 440                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 441                         if ((host->max_clk / div) <= clock)
 442                                 break;
 443                 }
 444                 div >>= 1;
 445         }
 446
 447         if (host->ops && host->ops->set_clock)
 448                 host->ops->set_clock(host, div);
 449
 450         if (host->ops && host->ops->config_dll) {
 451                 ret = host->ops->config_dll(host, clock, true);
 452                 if (ret) {
 453                         printf("%s: Error while configuring dll\n", __func__);
 454                         return ret;
 455                 }
 456         }
 457
 458         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 459         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 460                 << SDHCI_DIVIDER_HI_SHIFT;
 461         clk |= SDHCI_CLOCK_INT_EN;
 462         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 463
 464         /* Wait max 20 ms */
 465         timeout = 20;
 466         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 467                 & SDHCI_CLOCK_INT_STABLE)) {
 468                 if (timeout == 0) {
 469                         printf("%s: Internal clock never stabilised.\n",
 470                                __func__);
 471                         return -EBUSY;
 472                 }
 473                 timeout--;
 474                 udelay(1000);
 475         }
 476
 477         clk |= SDHCI_CLOCK_CARD_EN;
 478         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 479         return 0;
 480 }
 481
 482 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 483 {
 484         u8 pwr = 0;
 485
 486         if (power != (unsigned short)-1) {
 487                 switch (1 << power) {
 488                 case MMC_VDD_165_195:
 489                         pwr = SDHCI_POWER_180;
 490                         break;
 491                 case MMC_VDD_29_30:
 492                 case MMC_VDD_30_31:
 493                         pwr = SDHCI_POWER_300;
 494                         break;
 495                 case MMC_VDD_32_33:
 496                 case MMC_VDD_33_34:
 497                         pwr = SDHCI_POWER_330;
 498                         break;
 499                 }
 500         }
 501
 502         if (pwr == 0) {
 503                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 504                 return;
 505         }
 506
 507         pwr |= SDHCI_POWER_ON;
 508
 509         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 510 }
 511
 512 void sdhci_set_uhs_timing(struct sdhci_host *host)
 513 {
 514         struct mmc *mmc = host->mmc;
 515         u32 reg;
 516
 517         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 518         reg &= ~SDHCI_CTRL_UHS_MASK;
 519
 520         switch (mmc->selected_mode) {
 521         case UHS_SDR50:
 522         case MMC_HS_52:
 523                 reg |= SDHCI_CTRL_UHS_SDR50;
 524                 break;
 525         case UHS_DDR50:
 526         case MMC_DDR_52:
 527                 reg |= SDHCI_CTRL_UHS_DDR50;
 528                 break;
 529         case UHS_SDR104:
 530         case MMC_HS_200:
 531                 reg |= SDHCI_CTRL_UHS_SDR104;
 532                 break;
 533         case MMC_HS_400:
 534         case MMC_HS_400_ES:
 535                 reg |= SDHCI_CTRL_HS400;
 536                 break;
 537         default:
 538                 reg |= SDHCI_CTRL_UHS_SDR12;
 539         }
 540
 541         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 542 }
 543
 544 static void sdhci_set_voltage(struct sdhci_host *host)
 545 {
 546         if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
 547                 struct mmc *mmc = (struct mmc *)host->mmc;
 548                 u32 ctrl;
 549
 550                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 551
 552                 switch (mmc->signal_voltage) {
 553                 case MMC_SIGNAL_VOLTAGE_330:
 554 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 555                         if (mmc->vqmmc_supply) {
 556                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
 557                                         pr_err("failed to disable vqmmc-supply\n");
 558                                         return;
 559                                 }
 560
 561                                 if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
 562                                         pr_err("failed to set vqmmc-voltage to 3.3V\n");
 563                                         return;
 564                                 }
 565
 566                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
 567                                         pr_err("failed to enable vqmmc-supply\n");
 568                                         return;
 569                                 }
 570                         }
 571 #endif
 572                         if (IS_SD(mmc)) {
 573                                 ctrl &= ~SDHCI_CTRL_VDD_180;
 574                                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 575                         }
 576
 577                         /* Wait for 5ms */
 578                         mdelay(5);
 579
 580                         /* 3.3V regulator output should be stable within 5 ms */
 581                         if (IS_SD(mmc)) {
 582                                 if (ctrl & SDHCI_CTRL_VDD_180) {
 583                                         pr_err("3.3V regulator output did not become stable\n");
 584                                         return;
 585                                 }
 586                         }
 587
 588                         break;
 589                 case MMC_SIGNAL_VOLTAGE_180:
 590 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 591                         if (mmc->vqmmc_supply) {
 592                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
 593                                         pr_err("failed to disable vqmmc-supply\n");
 594                                         return;
 595                                 }
 596
 597                                 if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
 598                                         pr_err("failed to set vqmmc-voltage to 1.8V\n");
 599                                         return;
 600                                 }
 601
 602                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
 603                                         pr_err("failed to enable vqmmc-supply\n");
 604                                         return;
 605                                 }
 606                         }
 607 #endif
 608                         if (IS_SD(mmc)) {
 609                                 ctrl |= SDHCI_CTRL_VDD_180;
 610                                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 611                         }
 612
 613                         /* Wait for 5 ms */
 614                         mdelay(5);
 615
 616                         /* 1.8V regulator output has to be stable within 5 ms */
 617                         if (IS_SD(mmc)) {
 618                                 if (!(ctrl & SDHCI_CTRL_VDD_180)) {
 619                                         pr_err("1.8V regulator output did not become stable\n");
 620                                         return;
 621                                 }
 622                         }
 623
 624                         break;
 625                 default:
 626                         /* No signal voltage switch required */
 627                         return;
 628                 }
 629         }
 630 }
 631
 632 void sdhci_set_control_reg(struct sdhci_host *host)
 633 {
 634         sdhci_set_voltage(host);
 635         sdhci_set_uhs_timing(host);
 636 }
 637
 638 #ifdef CONFIG_DM_MMC
 639 static int sdhci_set_ios(struct udevice *dev)
 640 {
 641         struct mmc *mmc = mmc_get_mmc_dev(dev);
 642 #else
 643 static int sdhci_set_ios(struct mmc *mmc)
 644 {
 645 #endif
 646         u32 ctrl;
 647         struct sdhci_host *host = mmc->priv;
 648         bool no_hispd_bit = false;
 649
 650         if (host->ops && host->ops->set_control_reg)
 651                 host->ops->set_control_reg(host);
 652
 653         if (mmc->clock != host->clock)
 654                 sdhci_set_clock(mmc, mmc->clock);
 655
 656         if (mmc->clk_disable)
 657                 sdhci_set_clock(mmc, 0);
 658
 659         /* Set bus width */
 660         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 661         if (mmc->bus_width == 8) {
 662                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 663                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 664                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 665                         ctrl |= SDHCI_CTRL_8BITBUS;
 666         } else {
 667                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 668                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 669                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 670                 if (mmc->bus_width == 4)
 671                         ctrl |= SDHCI_CTRL_4BITBUS;
 672                 else
 673                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 674         }
 675
 676         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 677             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
 678                 ctrl &= ~SDHCI_CTRL_HISPD;
 679                 no_hispd_bit = true;
 680         }
 681
 682         if (!no_hispd_bit) {
 683                 if (mmc->selected_mode == MMC_HS ||
 684                     mmc->selected_mode == SD_HS ||
 685                     mmc->selected_mode == MMC_DDR_52 ||
 686                     mmc->selected_mode == MMC_HS_200 ||
 687                     mmc->selected_mode == MMC_HS_400 ||
 688                     mmc->selected_mode == MMC_HS_400_ES ||
 689                     mmc->selected_mode == UHS_SDR25 ||
 690                     mmc->selected_mode == UHS_SDR50 ||
 691                     mmc->selected_mode == UHS_SDR104 ||
 692                     mmc->selected_mode == UHS_DDR50)
 693                         ctrl |= SDHCI_CTRL_HISPD;
 694                 else
 695                         ctrl &= ~SDHCI_CTRL_HISPD;
 696         }
 697
 698         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 699
 700         /* If available, call the driver specific "post" set_ios() function */
 701         if (host->ops && host->ops->set_ios_post)
 702                 return host->ops->set_ios_post(host);
 703
 704         return 0;
 705 }
 706
 707 static int sdhci_init(struct mmc *mmc)
 708 {
 709         struct sdhci_host *host = mmc->priv;
 710 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 711         struct udevice *dev = mmc->dev;
 712
 713         gpio_request_by_name(dev, "cd-gpios", 0,
 714                              &host->cd_gpio, GPIOD_IS_IN);
 715 #endif
 716
 717         sdhci_reset(host, SDHCI_RESET_ALL);
 718
 719 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 720         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 721         /*
 722          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 723          * is defined.
 724          */
 725         host->force_align_buffer = true;
 726 #else
 727         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 728                 host->align_buffer = memalign(8, 512 * 1024);
 729                 if (!host->align_buffer) {
 730                         printf("%s: Aligned buffer alloc failed!!!\n",
 731                                __func__);
 732                         return -ENOMEM;
 733                 }
 734         }
 735 #endif
 736
 737         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 738
 739         if (host->ops && host->ops->get_cd)
 740                 host->ops->get_cd(host);
 741
 742         /* Enable only interrupts served by the SD controller */
 743         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 744                      SDHCI_INT_ENABLE);
 745         /* Mask all sdhci interrupt sources */
 746         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 747
 748         return 0;
 749 }
 750
 751 #ifdef CONFIG_DM_MMC
 752 int sdhci_probe(struct udevice *dev)
 753 {
 754         struct mmc *mmc = mmc_get_mmc_dev(dev);
 755
 756         return sdhci_init(mmc);
 757 }
 758
 759 static int sdhci_deferred_probe(struct udevice *dev)
 760 {
 761         int err;
 762         struct mmc *mmc = mmc_get_mmc_dev(dev);
 763         struct sdhci_host *host = mmc->priv;
 764
 765         if (host->ops && host->ops->deferred_probe) {
 766                 err = host->ops->deferred_probe(host);
 767                 if (err)
 768                         return err;
 769         }
 770         return 0;
 771 }
 772
 773 static int sdhci_get_cd(struct udevice *dev)
 774 {
 775         struct mmc *mmc = mmc_get_mmc_dev(dev);
 776         struct sdhci_host *host = mmc->priv;
 777         int value;
 778
 779         /* If nonremovable, assume that the card is always present. */
 780         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 781                 return 1;
 782         /* If polling, assume that the card is always present. */
 783         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 784                 return 1;
 785
 786 #if CONFIG_IS_ENABLED(DM_GPIO)
 787         value = dm_gpio_get_value(&host->cd_gpio);
 788         if (value >= 0) {
 789                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 790                         return !value;
 791                 else
 792                         return value;
 793         }
 794 #endif
 795         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 796                    SDHCI_CARD_PRESENT);
 797         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 798                 return !value;
 799         else
 800                 return value;
 801 }
 802
 803 static int sdhci_wait_dat0(struct udevice *dev, int state,
 804                            int timeout_us)
 805 {
 806         int tmp;
 807         struct mmc *mmc = mmc_get_mmc_dev(dev);
 808         struct sdhci_host *host = mmc->priv;
 809         unsigned long timeout = timer_get_us() + timeout_us;
 810
 811         // readx_poll_timeout is unsuitable because sdhci_readl accepts
 812         // two arguments
 813         do {
 814                 tmp = sdhci_readl(host, SDHCI_PRESENT_STATE);
 815                 if (!!(tmp & SDHCI_DATA_0_LVL_MASK) == !!state)
 816                         return 0;
 817         } while (!timeout_us || !time_after(timer_get_us(), timeout));
 818
 819         return -ETIMEDOUT;
 820 }
 821
 822 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 823 static int sdhci_set_enhanced_strobe(struct udevice *dev)
 824 {
 825         struct mmc *mmc = mmc_get_mmc_dev(dev);
 826         struct sdhci_host *host = mmc->priv;
 827
 828         if (host->ops && host->ops->set_enhanced_strobe)
 829                 return host->ops->set_enhanced_strobe(host);
 830
 831         return -ENOTSUPP;
 832 }
 833 #endif
 834
 835 const struct dm_mmc_ops sdhci_ops = {
 836         .send_cmd       = sdhci_send_command,
 837         .set_ios        = sdhci_set_ios,
 838         .get_cd         = sdhci_get_cd,
 839         .deferred_probe = sdhci_deferred_probe,
 840 #ifdef MMC_SUPPORTS_TUNING
 841         .execute_tuning = sdhci_execute_tuning,
 842 #endif
 843         .wait_dat0      = sdhci_wait_dat0,
 844 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 845         .set_enhanced_strobe = sdhci_set_enhanced_strobe,
 846 #endif
 847 };
 848 #else
 849 static const struct mmc_ops sdhci_ops = {
 850         .send_cmd       = sdhci_send_command,
 851         .set_ios        = sdhci_set_ios,
 852         .init           = sdhci_init,
 853 };
 854 #endif
 855
 856 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 857                 u32 f_max, u32 f_min)
 858 {
 859         u32 caps, caps_1 = 0;
 860 #if CONFIG_IS_ENABLED(DM_MMC)
 861         u64 dt_caps, dt_caps_mask;
 862
 863         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 864                                             "sdhci-caps-mask", 0);
 865         dt_caps = dev_read_u64_default(host->mmc->dev,
 866                                        "sdhci-caps", 0);
 867         caps = ~lower_32_bits(dt_caps_mask) &
 868                sdhci_readl(host, SDHCI_CAPABILITIES);
 869         caps |= lower_32_bits(dt_caps);
 870 #else
 871         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 872 #endif
 873         debug("%s, caps: 0x%x\n", __func__, caps);
 874
 875 #ifdef CONFIG_MMC_SDHCI_SDMA
 876         if ((caps & SDHCI_CAN_DO_SDMA)) {
 877                 host->flags |= USE_SDMA;
 878         } else {
 879                 debug("%s: Your controller doesn't support SDMA!!\n",
 880                       __func__);
 881         }
 882 #endif
 883 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 884         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 885                 printf("%s: Your controller doesn't support SDMA!!\n",
 886                        __func__);
 887                 return -EINVAL;
 888         }
 889         host->adma_desc_table = sdhci_adma_init();
 890         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 891
 892 #ifdef CONFIG_DMA_ADDR_T_64BIT
 893         host->flags |= USE_ADMA64;
 894 #else
 895         host->flags |= USE_ADMA;
 896 #endif
 897 #endif
 898         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 899                 host->version =
 900                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 901         else
 902                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 903
 904         cfg->name = host->name;
 905 #ifndef CONFIG_DM_MMC
 906         cfg->ops = &sdhci_ops;
 907 #endif
 908
 909         /* Check whether the clock multiplier is supported or not */
 910         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 911 #if CONFIG_IS_ENABLED(DM_MMC)
 912                 caps_1 = ~upper_32_bits(dt_caps_mask) &
 913                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 914                 caps_1 |= upper_32_bits(dt_caps);
 915 #else
 916                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 917 #endif
 918                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 919                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 920                                 SDHCI_CLOCK_MUL_SHIFT;
 921         }
 922
 923         if (host->max_clk == 0) {
 924                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 925                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 926                                 SDHCI_CLOCK_BASE_SHIFT;
 927                 else
 928                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 929                                 SDHCI_CLOCK_BASE_SHIFT;
 930                 host->max_clk *= 1000000;
 931                 if (host->clk_mul)
 932                         host->max_clk *= host->clk_mul;
 933         }
 934         if (host->max_clk == 0) {
 935                 printf("%s: Hardware doesn't specify base clock frequency\n",
 936                        __func__);
 937                 return -EINVAL;
 938         }
 939         if (f_max && (f_max < host->max_clk))
 940                 cfg->f_max = f_max;
 941         else
 942                 cfg->f_max = host->max_clk;
 943         if (f_min)
 944                 cfg->f_min = f_min;
 945         else {
 946                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 947                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 948                 else
 949                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 950         }
 951         cfg->voltages = 0;
 952         if (caps & SDHCI_CAN_VDD_330)
 953                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 954         if (caps & SDHCI_CAN_VDD_300)
 955                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 956         if (caps & SDHCI_CAN_VDD_180)
 957                 cfg->voltages |= MMC_VDD_165_195;
 958
 959         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 960                 cfg->voltages |= host->voltages;
 961
 962         if (caps & SDHCI_CAN_DO_HISPD)
 963                 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 964
 965         cfg->host_caps |= MMC_MODE_4BIT;
 966
 967         /* Since Host Controller Version3.0 */
 968         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 969                 if (!(caps & SDHCI_CAN_DO_8BIT))
 970                         cfg->host_caps &= ~MMC_MODE_8BIT;
 971         }
 972
 973         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 974                 cfg->host_caps &= ~MMC_MODE_HS;
 975                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 976         }
 977
 978         if (!(cfg->voltages & MMC_VDD_165_195) ||
 979             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 980                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 981                             SDHCI_SUPPORT_DDR50);
 982
 983         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 984                       SDHCI_SUPPORT_DDR50))
 985                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 986
 987         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 988                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 989                 /*
 990                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 991                  * field can be promoted to support HS200.
 992                  */
 993                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 994         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 995                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 996         }
 997
 998         if ((host->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_HS400) &&
 999             (caps_1 & SDHCI_SUPPORT_HS400))
1000                 cfg->host_caps |= MMC_CAP(MMC_HS_400);
1001
1002         if (caps_1 & SDHCI_SUPPORT_DDR50)
1003                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
1004
1005         if (host->host_caps)
1006                 cfg->host_caps |= host->host_caps;
1007
1008         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1009
1010         return 0;
1011 }
1012
1013 #ifdef CONFIG_BLK
1014 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
1015 {
1016         return mmc_bind(dev, mmc, cfg);
1017 }
1018 #else
1019 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
1020 {
1021         int ret;
1022
1023         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
1024         if (ret)
1025                 return ret;
1026
1027         host->mmc = mmc_create(&host->cfg, host);
1028         if (host->mmc == NULL) {
1029                 printf("%s: mmc create fail!\n", __func__);
1030                 return -ENOMEM;
1031         }
1032
1033         return 0;
1034 }
1035 #endif