1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
18 #include <asm/cache.h>
19 #include <linux/bitops.h>
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
23 #include <power/regulator.h>
25 static void sdhci_reset(struct sdhci_host *host, u8 mask)
27 unsigned long timeout;
31 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
32 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
34 printf("%s: Reset 0x%x never completed.\n",
43 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
46 if (cmd->resp_type & MMC_RSP_136) {
47 /* CRC is stripped so we need to do some shifting. */
48 for (i = 0; i < 4; i++) {
49 cmd->response[i] = sdhci_readl(host,
50 SDHCI_RESPONSE + (3-i)*4) << 8;
52 cmd->response[i] |= sdhci_readb(host,
53 SDHCI_RESPONSE + (3-i)*4-1);
56 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
60 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
64 for (i = 0; i < data->blocksize; i += 4) {
65 offs = data->dest + i;
66 if (data->flags == MMC_DATA_READ)
67 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
69 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
73 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
74 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
75 int *is_aligned, int trans_bytes)
81 if (data->flags == MMC_DATA_READ)
84 buf = (void *)data->src;
86 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
87 ctrl &= ~SDHCI_CTRL_DMA_MASK;
88 if (host->flags & USE_ADMA64)
89 ctrl |= SDHCI_CTRL_ADMA64;
90 else if (host->flags & USE_ADMA)
91 ctrl |= SDHCI_CTRL_ADMA32;
92 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
94 if (host->flags & USE_SDMA &&
95 (host->force_align_buffer ||
96 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
97 ((unsigned long)buf & 0x7) != 0x0))) {
99 if (data->flags != MMC_DATA_READ)
100 memcpy(host->align_buffer, buf, trans_bytes);
101 buf = host->align_buffer;
104 host->start_addr = dma_map_single(buf, trans_bytes,
105 mmc_get_dma_dir(data));
107 if (host->flags & USE_SDMA) {
108 dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
109 sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
111 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
112 else if (host->flags & (USE_ADMA | USE_ADMA64)) {
113 sdhci_prepare_adma_table(host->adma_desc_table, data,
116 sdhci_writel(host, lower_32_bits(host->adma_addr),
118 if (host->flags & USE_ADMA64)
119 sdhci_writel(host, upper_32_bits(host->adma_addr),
120 SDHCI_ADMA_ADDRESS_HI);
125 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
126 int *is_aligned, int trans_bytes)
129 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
131 dma_addr_t start_addr = host->start_addr;
132 unsigned int stat, rdy, mask, timeout, block = 0;
133 bool transfer_done = false;
136 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
137 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
139 stat = sdhci_readl(host, SDHCI_INT_STATUS);
140 if (stat & SDHCI_INT_ERROR) {
141 pr_debug("%s: Error detected in status(0x%X)!\n",
145 if (!transfer_done && (stat & rdy)) {
146 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
148 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
149 sdhci_transfer_pio(host, data);
150 data->dest += data->blocksize;
151 if (++block >= data->blocks) {
152 /* Keep looping until the SDHCI_INT_DATA_END is
153 * cleared, even if we finished sending all the
156 transfer_done = true;
160 if ((host->flags & USE_DMA) && !transfer_done &&
161 (stat & SDHCI_INT_DMA_END)) {
162 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
163 if (host->flags & USE_SDMA) {
165 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
166 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
167 start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
169 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
175 printf("%s: Transfer data timeout\n", __func__);
178 } while (!(stat & SDHCI_INT_DATA_END));
180 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
181 dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
182 mmc_get_dma_dir(data));
189 * No command will be sent by driver if card is busy, so driver must wait
190 * for card ready state.
191 * Every time when card is busy after timeout then (last) timeout value will be
192 * increased twice but only if it doesn't exceed global defined maximum.
193 * Each function call will use last timeout value.
195 #define SDHCI_CMD_MAX_TIMEOUT 3200
196 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
197 #define SDHCI_READ_STATUS_TIMEOUT 1000
200 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
201 struct mmc_data *data)
203 struct mmc *mmc = mmc_get_mmc_dev(dev);
206 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
207 struct mmc_data *data)
210 struct sdhci_host *host = mmc->priv;
211 unsigned int stat = 0;
213 int trans_bytes = 0, is_aligned = 1;
214 u32 mask, flags, mode = 0;
215 unsigned int time = 0;
216 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
217 ulong start = get_timer(0);
219 host->start_addr = 0;
220 /* Timeout unit - ms */
221 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
223 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
225 /* We shouldn't wait for data inihibit for stop commands, even
226 though they might use busy signaling */
227 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
228 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
229 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
230 mask &= ~SDHCI_DATA_INHIBIT;
232 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
233 if (time >= cmd_timeout) {
234 printf("%s: MMC: %d busy ", __func__, mmc_dev);
235 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
236 cmd_timeout += cmd_timeout;
237 printf("timeout increasing to: %u ms.\n",
248 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
250 mask = SDHCI_INT_RESPONSE;
251 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
252 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
253 mask = SDHCI_INT_DATA_AVAIL;
255 if (!(cmd->resp_type & MMC_RSP_PRESENT))
256 flags = SDHCI_CMD_RESP_NONE;
257 else if (cmd->resp_type & MMC_RSP_136)
258 flags = SDHCI_CMD_RESP_LONG;
259 else if (cmd->resp_type & MMC_RSP_BUSY) {
260 flags = SDHCI_CMD_RESP_SHORT_BUSY;
261 mask |= SDHCI_INT_DATA_END;
263 flags = SDHCI_CMD_RESP_SHORT;
265 if (cmd->resp_type & MMC_RSP_CRC)
266 flags |= SDHCI_CMD_CRC;
267 if (cmd->resp_type & MMC_RSP_OPCODE)
268 flags |= SDHCI_CMD_INDEX;
269 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
270 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
271 flags |= SDHCI_CMD_DATA;
273 /* Set Transfer mode regarding to data flag */
275 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
277 if (!(host->quirks & SDHCI_QUIRK_SUPPORT_SINGLE))
278 mode = SDHCI_TRNS_BLK_CNT_EN;
279 trans_bytes = data->blocks * data->blocksize;
280 if (data->blocks > 1)
281 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
283 if (data->flags == MMC_DATA_READ)
284 mode |= SDHCI_TRNS_READ;
286 if (host->flags & USE_DMA) {
287 mode |= SDHCI_TRNS_DMA;
288 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
291 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
294 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
295 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
296 } else if (cmd->resp_type & MMC_RSP_BUSY) {
297 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
300 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
301 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
302 start = get_timer(0);
304 stat = sdhci_readl(host, SDHCI_INT_STATUS);
305 if (stat & SDHCI_INT_ERROR)
308 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
309 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
312 printf("%s: Timeout for status update!\n",
317 } while ((stat & mask) != mask);
319 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
320 sdhci_cmd_done(host, cmd);
321 sdhci_writel(host, mask, SDHCI_INT_STATUS);
326 ret = sdhci_transfer_data(host, data);
328 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
331 stat = sdhci_readl(host, SDHCI_INT_STATUS);
332 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
334 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
335 !is_aligned && (data->flags == MMC_DATA_READ))
336 memcpy(data->dest, host->align_buffer, trans_bytes);
340 sdhci_reset(host, SDHCI_RESET_CMD);
341 sdhci_reset(host, SDHCI_RESET_DATA);
342 if (stat & SDHCI_INT_TIMEOUT)
348 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
349 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
352 struct mmc *mmc = mmc_get_mmc_dev(dev);
353 struct sdhci_host *host = mmc->priv;
355 debug("%s\n", __func__);
357 if (host->ops && host->ops->platform_execute_tuning) {
358 err = host->ops->platform_execute_tuning(mmc, opcode);
366 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
368 struct sdhci_host *host = mmc->priv;
369 unsigned int div, clk = 0, timeout;
374 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
375 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
377 printf("%s: Timeout to wait cmd & data inhibit\n",
386 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
391 if (host->ops && host->ops->set_delay) {
392 ret = host->ops->set_delay(host);
394 printf("%s: Error while setting tap delay\n", __func__);
399 if (host->ops && host->ops->config_dll) {
400 ret = host->ops->config_dll(host, clock, false);
402 printf("%s: Error while configuring dll\n", __func__);
407 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
409 * Check if the Host Controller supports Programmable Clock
413 for (div = 1; div <= 1024; div++) {
414 if ((host->max_clk / div) <= clock)
419 * Set Programmable Clock Mode in the Clock
422 clk = SDHCI_PROG_CLOCK_MODE;
425 /* Version 3.00 divisors must be a multiple of 2. */
426 if (host->max_clk <= clock) {
430 div < SDHCI_MAX_DIV_SPEC_300;
432 if ((host->max_clk / div) <= clock)
439 /* Version 2.00 divisors must be a power of 2. */
440 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
441 if ((host->max_clk / div) <= clock)
447 if (host->ops && host->ops->set_clock)
448 host->ops->set_clock(host, div);
450 if (host->ops && host->ops->config_dll) {
451 ret = host->ops->config_dll(host, clock, true);
453 printf("%s: Error while configuring dll\n", __func__);
458 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
459 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
460 << SDHCI_DIVIDER_HI_SHIFT;
461 clk |= SDHCI_CLOCK_INT_EN;
462 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
466 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
467 & SDHCI_CLOCK_INT_STABLE)) {
469 printf("%s: Internal clock never stabilised.\n",
477 clk |= SDHCI_CLOCK_CARD_EN;
478 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
482 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
486 if (power != (unsigned short)-1) {
487 switch (1 << power) {
488 case MMC_VDD_165_195:
489 pwr = SDHCI_POWER_180;
493 pwr = SDHCI_POWER_300;
497 pwr = SDHCI_POWER_330;
503 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
507 pwr |= SDHCI_POWER_ON;
509 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
512 void sdhci_set_uhs_timing(struct sdhci_host *host)
514 struct mmc *mmc = host->mmc;
517 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
518 reg &= ~SDHCI_CTRL_UHS_MASK;
520 switch (mmc->selected_mode) {
523 reg |= SDHCI_CTRL_UHS_SDR25;
527 reg |= SDHCI_CTRL_UHS_SDR50;
531 reg |= SDHCI_CTRL_UHS_DDR50;
535 reg |= SDHCI_CTRL_UHS_SDR104;
539 reg |= SDHCI_CTRL_HS400;
542 reg |= SDHCI_CTRL_UHS_SDR12;
545 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
548 static void sdhci_set_voltage(struct sdhci_host *host)
550 if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
551 struct mmc *mmc = (struct mmc *)host->mmc;
554 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
556 switch (mmc->signal_voltage) {
557 case MMC_SIGNAL_VOLTAGE_330:
558 #if CONFIG_IS_ENABLED(DM_REGULATOR)
559 if (mmc->vqmmc_supply) {
560 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
561 pr_err("failed to disable vqmmc-supply\n");
565 if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
566 pr_err("failed to set vqmmc-voltage to 3.3V\n");
570 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
571 pr_err("failed to enable vqmmc-supply\n");
577 ctrl &= ~SDHCI_CTRL_VDD_180;
578 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
584 /* 3.3V regulator output should be stable within 5 ms */
586 if (ctrl & SDHCI_CTRL_VDD_180) {
587 pr_err("3.3V regulator output did not become stable\n");
593 case MMC_SIGNAL_VOLTAGE_180:
594 #if CONFIG_IS_ENABLED(DM_REGULATOR)
595 if (mmc->vqmmc_supply) {
596 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
597 pr_err("failed to disable vqmmc-supply\n");
601 if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
602 pr_err("failed to set vqmmc-voltage to 1.8V\n");
606 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
607 pr_err("failed to enable vqmmc-supply\n");
613 ctrl |= SDHCI_CTRL_VDD_180;
614 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
620 /* 1.8V regulator output has to be stable within 5 ms */
622 if (!(ctrl & SDHCI_CTRL_VDD_180)) {
623 pr_err("1.8V regulator output did not become stable\n");
630 /* No signal voltage switch required */
636 void sdhci_set_control_reg(struct sdhci_host *host)
638 sdhci_set_voltage(host);
639 sdhci_set_uhs_timing(host);
643 static int sdhci_set_ios(struct udevice *dev)
645 struct mmc *mmc = mmc_get_mmc_dev(dev);
647 static int sdhci_set_ios(struct mmc *mmc)
651 struct sdhci_host *host = mmc->priv;
652 bool no_hispd_bit = false;
654 if (host->ops && host->ops->set_control_reg)
655 host->ops->set_control_reg(host);
657 if (mmc->clock != host->clock)
658 sdhci_set_clock(mmc, mmc->clock);
660 if (mmc->clk_disable)
661 sdhci_set_clock(mmc, 0);
664 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
665 if (mmc->bus_width == 8) {
666 ctrl &= ~SDHCI_CTRL_4BITBUS;
667 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
668 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
669 ctrl |= SDHCI_CTRL_8BITBUS;
671 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
672 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
673 ctrl &= ~SDHCI_CTRL_8BITBUS;
674 if (mmc->bus_width == 4)
675 ctrl |= SDHCI_CTRL_4BITBUS;
677 ctrl &= ~SDHCI_CTRL_4BITBUS;
680 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
681 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
682 ctrl &= ~SDHCI_CTRL_HISPD;
687 if (mmc->selected_mode == MMC_HS ||
688 mmc->selected_mode == SD_HS ||
689 mmc->selected_mode == MMC_HS_52 ||
690 mmc->selected_mode == MMC_DDR_52 ||
691 mmc->selected_mode == MMC_HS_200 ||
692 mmc->selected_mode == MMC_HS_400 ||
693 mmc->selected_mode == MMC_HS_400_ES ||
694 mmc->selected_mode == UHS_SDR25 ||
695 mmc->selected_mode == UHS_SDR50 ||
696 mmc->selected_mode == UHS_SDR104 ||
697 mmc->selected_mode == UHS_DDR50)
698 ctrl |= SDHCI_CTRL_HISPD;
700 ctrl &= ~SDHCI_CTRL_HISPD;
703 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
705 /* If available, call the driver specific "post" set_ios() function */
706 if (host->ops && host->ops->set_ios_post)
707 return host->ops->set_ios_post(host);
712 static int sdhci_init(struct mmc *mmc)
714 struct sdhci_host *host = mmc->priv;
715 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
716 struct udevice *dev = mmc->dev;
718 gpio_request_by_name(dev, "cd-gpios", 0,
719 &host->cd_gpio, GPIOD_IS_IN);
722 sdhci_reset(host, SDHCI_RESET_ALL);
724 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
725 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
727 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
730 host->force_align_buffer = true;
732 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
733 host->align_buffer = memalign(8, 512 * 1024);
734 if (!host->align_buffer) {
735 printf("%s: Aligned buffer alloc failed!!!\n",
742 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
744 if (host->ops && host->ops->get_cd)
745 host->ops->get_cd(host);
747 /* Enable only interrupts served by the SD controller */
748 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
750 /* Mask all sdhci interrupt sources */
751 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
757 int sdhci_probe(struct udevice *dev)
759 struct mmc *mmc = mmc_get_mmc_dev(dev);
761 return sdhci_init(mmc);
764 static int sdhci_deferred_probe(struct udevice *dev)
767 struct mmc *mmc = mmc_get_mmc_dev(dev);
768 struct sdhci_host *host = mmc->priv;
770 if (host->ops && host->ops->deferred_probe) {
771 err = host->ops->deferred_probe(host);
778 static int sdhci_get_cd(struct udevice *dev)
780 struct mmc *mmc = mmc_get_mmc_dev(dev);
781 struct sdhci_host *host = mmc->priv;
784 /* If nonremovable, assume that the card is always present. */
785 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
787 /* If polling, assume that the card is always present. */
788 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
791 #if CONFIG_IS_ENABLED(DM_GPIO)
792 value = dm_gpio_get_value(&host->cd_gpio);
794 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
800 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
802 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
808 static int sdhci_wait_dat0(struct udevice *dev, int state,
812 struct mmc *mmc = mmc_get_mmc_dev(dev);
813 struct sdhci_host *host = mmc->priv;
814 unsigned long timeout = timer_get_us() + timeout_us;
816 // readx_poll_timeout is unsuitable because sdhci_readl accepts
819 tmp = sdhci_readl(host, SDHCI_PRESENT_STATE);
820 if (!!(tmp & SDHCI_DATA_0_LVL_MASK) == !!state)
822 } while (!timeout_us || !time_after(timer_get_us(), timeout));
827 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
828 static int sdhci_set_enhanced_strobe(struct udevice *dev)
830 struct mmc *mmc = mmc_get_mmc_dev(dev);
831 struct sdhci_host *host = mmc->priv;
833 if (host->ops && host->ops->set_enhanced_strobe)
834 return host->ops->set_enhanced_strobe(host);
840 const struct dm_mmc_ops sdhci_ops = {
841 .send_cmd = sdhci_send_command,
842 .set_ios = sdhci_set_ios,
843 .get_cd = sdhci_get_cd,
844 .deferred_probe = sdhci_deferred_probe,
845 #ifdef MMC_SUPPORTS_TUNING
846 .execute_tuning = sdhci_execute_tuning,
848 .wait_dat0 = sdhci_wait_dat0,
849 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
850 .set_enhanced_strobe = sdhci_set_enhanced_strobe,
854 static const struct mmc_ops sdhci_ops = {
855 .send_cmd = sdhci_send_command,
856 .set_ios = sdhci_set_ios,
861 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
862 u32 f_max, u32 f_min)
864 u32 caps, caps_1 = 0;
865 #if CONFIG_IS_ENABLED(DM_MMC)
866 u64 dt_caps, dt_caps_mask;
868 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
869 "sdhci-caps-mask", 0);
870 dt_caps = dev_read_u64_default(host->mmc->dev,
872 caps = ~lower_32_bits(dt_caps_mask) &
873 sdhci_readl(host, SDHCI_CAPABILITIES);
874 caps |= lower_32_bits(dt_caps);
876 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
878 debug("%s, caps: 0x%x\n", __func__, caps);
880 #ifdef CONFIG_MMC_SDHCI_SDMA
881 if ((caps & SDHCI_CAN_DO_SDMA)) {
882 host->flags |= USE_SDMA;
884 debug("%s: Your controller doesn't support SDMA!!\n",
888 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
889 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
890 printf("%s: Your controller doesn't support SDMA!!\n",
894 host->adma_desc_table = sdhci_adma_init();
895 host->adma_addr = (dma_addr_t)host->adma_desc_table;
897 #ifdef CONFIG_DMA_ADDR_T_64BIT
898 host->flags |= USE_ADMA64;
900 host->flags |= USE_ADMA;
903 if (host->quirks & SDHCI_QUIRK_REG32_RW)
905 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
907 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
909 cfg->name = host->name;
910 #ifndef CONFIG_DM_MMC
911 cfg->ops = &sdhci_ops;
914 /* Check whether the clock multiplier is supported or not */
915 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
916 #if CONFIG_IS_ENABLED(DM_MMC)
917 caps_1 = ~upper_32_bits(dt_caps_mask) &
918 sdhci_readl(host, SDHCI_CAPABILITIES_1);
919 caps_1 |= upper_32_bits(dt_caps);
921 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
923 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
924 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
925 SDHCI_CLOCK_MUL_SHIFT;
928 if (host->max_clk == 0) {
929 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
930 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
931 SDHCI_CLOCK_BASE_SHIFT;
933 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
934 SDHCI_CLOCK_BASE_SHIFT;
935 host->max_clk *= 1000000;
937 host->max_clk *= host->clk_mul;
939 if (host->max_clk == 0) {
940 printf("%s: Hardware doesn't specify base clock frequency\n",
944 if (f_max && (f_max < host->max_clk))
947 cfg->f_max = host->max_clk;
951 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
952 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
954 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
957 if (caps & SDHCI_CAN_VDD_330)
958 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
959 if (caps & SDHCI_CAN_VDD_300)
960 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
961 if (caps & SDHCI_CAN_VDD_180)
962 cfg->voltages |= MMC_VDD_165_195;
964 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
965 cfg->voltages |= host->voltages;
967 if (caps & SDHCI_CAN_DO_HISPD)
968 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
970 cfg->host_caps |= MMC_MODE_4BIT;
972 /* Since Host Controller Version3.0 */
973 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
974 if (!(caps & SDHCI_CAN_DO_8BIT))
975 cfg->host_caps &= ~MMC_MODE_8BIT;
978 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
979 cfg->host_caps &= ~MMC_MODE_HS;
980 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
983 if (!(cfg->voltages & MMC_VDD_165_195) ||
984 (host->quirks & SDHCI_QUIRK_NO_1_8_V))
985 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
986 SDHCI_SUPPORT_DDR50);
988 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
989 SDHCI_SUPPORT_DDR50))
990 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
992 if (caps_1 & SDHCI_SUPPORT_SDR104) {
993 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
995 * SD3.0: SDR104 is supported so (for eMMC) the caps2
996 * field can be promoted to support HS200.
998 cfg->host_caps |= MMC_CAP(MMC_HS_200);
999 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
1000 cfg->host_caps |= MMC_CAP(UHS_SDR50);
1003 if ((host->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_HS400) &&
1004 (caps_1 & SDHCI_SUPPORT_HS400))
1005 cfg->host_caps |= MMC_CAP(MMC_HS_400);
1007 if (caps_1 & SDHCI_SUPPORT_DDR50)
1008 cfg->host_caps |= MMC_CAP(UHS_DDR50);
1010 if (host->host_caps)
1011 cfg->host_caps |= host->host_caps;
1013 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1019 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
1021 return mmc_bind(dev, mmc, cfg);
1024 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
1028 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
1032 host->mmc = mmc_create(&host->cfg, host);
1033 if (host->mmc == NULL) {
1034 printf("%s: mmc create fail!\n", __func__);