drivers/mmc/rockchip_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
   4  *
   5  * Rockchip SD Host Controller Interface
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dm/ofnode.h>
  12 #include <dt-structs.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/libfdt.h>
  16 #include <linux/iopoll.h>
  17 #include <malloc.h>
  18 #include <mapmem.h>
  19 #include "mmc_private.h"
  20 #include <sdhci.h>
  21 #include <syscon.h>
  22 #include <asm/arch-rockchip/clock.h>
  23 #include <asm/arch-rockchip/hardware.h>
  24
  25 /* 400KHz is max freq for card ID etc. Use that as min */
  26 #define EMMC_MIN_FREQ   400000
  27 #define KHz     (1000)
  28 #define MHz     (1000 * KHz)
  29 #define SDHCI_TUNING_LOOP_COUNT         40
  30
  31 #define PHYCTRL_CALDONE_MASK            0x1
  32 #define PHYCTRL_CALDONE_SHIFT           0x6
  33 #define PHYCTRL_CALDONE_DONE            0x1
  34 #define PHYCTRL_DLLRDY_MASK             0x1
  35 #define PHYCTRL_DLLRDY_SHIFT            0x5
  36 #define PHYCTRL_DLLRDY_DONE             0x1
  37 #define PHYCTRL_FREQSEL_200M            0x0
  38 #define PHYCTRL_FREQSEL_50M             0x1
  39 #define PHYCTRL_FREQSEL_100M            0x2
  40 #define PHYCTRL_FREQSEL_150M            0x3
  41 #define PHYCTRL_DLL_LOCK_WO_TMOUT(x)    \
  42         ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
  43         PHYCTRL_DLLRDY_DONE)
  44
  45 /* Rockchip specific Registers */
  46 #define DWCMSHC_EMMC_DLL_CTRL           0x800
  47 #define DWCMSHC_EMMC_DLL_CTRL_RESET     BIT(1)
  48 #define DWCMSHC_EMMC_DLL_RXCLK          0x804
  49 #define DWCMSHC_EMMC_DLL_TXCLK          0x808
  50 #define DWCMSHC_EMMC_DLL_STRBIN         0x80c
  51 #define DWCMSHC_EMMC_DLL_STATUS0        0x840
  52 #define DWCMSHC_EMMC_DLL_STATUS1        0x844
  53 #define DWCMSHC_EMMC_DLL_START          BIT(0)
  54 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL   29
  55 #define DWCMSHC_EMMC_DLL_START_POINT    16
  56 #define DWCMSHC_EMMC_DLL_START_DEFAULT  5
  57 #define DWCMSHC_EMMC_DLL_INC_VALUE      2
  58 #define DWCMSHC_EMMC_DLL_INC            8
  59 #define DWCMSHC_EMMC_DLL_DLYENA         BIT(27)
  60 #define DLL_TXCLK_TAPNUM_DEFAULT        0x10
  61 #define DLL_STRBIN_TAPNUM_DEFAULT       0x3
  62 #define DLL_TXCLK_TAPNUM_FROM_SW        BIT(24)
  63 #define DWCMSHC_EMMC_DLL_LOCKED         BIT(8)
  64 #define DWCMSHC_EMMC_DLL_TIMEOUT        BIT(9)
  65 #define DLL_RXCLK_NO_INVERTER           1
  66 #define DLL_RXCLK_INVERTER              0
  67 #define DWCMSHC_ENHANCED_STROBE         BIT(8)
  68 #define DLL_LOCK_WO_TMOUT(x) \
  69         ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
  70         (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
  71 #define ROCKCHIP_MAX_CLKS               3
  72
  73 struct rockchip_sdhc_plat {
  74         struct mmc_config cfg;
  75         struct mmc mmc;
  76 };
  77
  78 struct rockchip_emmc_phy {
  79         u32 emmcphy_con[7];
  80         u32 reserved;
  81         u32 emmcphy_status;
  82 };
  83
  84 struct rockchip_sdhc {
  85         struct sdhci_host host;
  86         struct udevice *dev;
  87         void *base;
  88         struct rockchip_emmc_phy *phy;
  89         struct clk emmc_clk;
  90 };
  91
  92 struct sdhci_data {
  93         int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
  94         int (*emmc_phy_init)(struct udevice *dev);
  95         int (*get_phy)(struct udevice *dev);
  96 };
  97
  98 static int rk3399_emmc_phy_init(struct udevice *dev)
  99 {
 100         return 0;
 101 }
 102
 103 static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
 104 {
 105         u32 caldone, dllrdy, freqsel;
 106
 107         writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]);
 108         writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]);
 109         writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]);
 110
 111         /*
 112          * According to the user manual, calpad calibration
 113          * cycle takes more than 2us without the minimal recommended
 114          * value, so we may need a little margin here
 115          */
 116         udelay(3);
 117         writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]);
 118
 119         /*
 120          * According to the user manual, it asks driver to
 121          * wait 5us for calpad busy trimming. But it seems that
 122          * 5us of caldone isn't enough for all cases.
 123          */
 124         udelay(500);
 125         caldone = readl(&phy->emmcphy_status);
 126         caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
 127         if (caldone != PHYCTRL_CALDONE_DONE) {
 128                 printf("%s: caldone timeout.\n", __func__);
 129                 return;
 130         }
 131
 132         /* Set the frequency of the DLL operation */
 133         if (clock < 75 * MHz)
 134                 freqsel = PHYCTRL_FREQSEL_50M;
 135         else if (clock < 125 * MHz)
 136                 freqsel = PHYCTRL_FREQSEL_100M;
 137         else if (clock < 175 * MHz)
 138                 freqsel = PHYCTRL_FREQSEL_150M;
 139         else
 140                 freqsel = PHYCTRL_FREQSEL_200M;
 141
 142         /* Set the frequency of the DLL operation */
 143         writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
 144         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
 145
 146         /* REN Enable on STRB Line for HS400 */
 147         writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]);
 148
 149         read_poll_timeout(readl, &phy->emmcphy_status, dllrdy,
 150                           PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
 151 }
 152
 153 static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
 154 {
 155         writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]);
 156         writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]);
 157 }
 158
 159 static int rk3399_emmc_get_phy(struct udevice *dev)
 160 {
 161         struct rockchip_sdhc *priv = dev_get_priv(dev);
 162         ofnode phy_node;
 163         void *grf_base;
 164         u32 grf_phy_offset, phandle;
 165
 166         phandle = dev_read_u32_default(dev, "phys", 0);
 167         phy_node = ofnode_get_by_phandle(phandle);
 168         if (!ofnode_valid(phy_node)) {
 169                 debug("Not found emmc phy device\n");
 170                 return -ENODEV;
 171         }
 172
 173         grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 174         if (grf_base < 0) {
 175                 printf("%s Get syscon grf failed", __func__);
 176                 return -ENODEV;
 177         }
 178         grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0);
 179
 180         priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset);
 181
 182         return 0;
 183 }
 184
 185 static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
 186 {
 187         struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 188         int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
 189
 190         if (cycle_phy)
 191                 rk3399_emmc_phy_power_off(priv->phy);
 192
 193         sdhci_set_clock(host->mmc, clock);
 194
 195         if (cycle_phy)
 196                 rk3399_emmc_phy_power_on(priv->phy, clock);
 197
 198         return 0;
 199 }
 200
 201 static int rk3568_emmc_phy_init(struct udevice *dev)
 202 {
 203         struct rockchip_sdhc *prv = dev_get_priv(dev);
 204         struct sdhci_host *host = &prv->host;
 205         u32 extra;
 206
 207         extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 208         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 209
 210         return 0;
 211 }
 212
 213 static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
 214 {
 215         struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 216         int val, ret;
 217         u32 extra;
 218
 219         if (clock > host->max_clk)
 220                 clock = host->max_clk;
 221         if (clock)
 222                 clk_set_rate(&priv->emmc_clk, clock);
 223
 224         sdhci_set_clock(host->mmc, clock);
 225
 226         if (clock >= 100 * MHz) {
 227                 /* reset DLL */
 228                 sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
 229                 udelay(1);
 230                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
 231
 232                 /* Init DLL settings */
 233                 extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
 234                         DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
 235                         DWCMSHC_EMMC_DLL_START;
 236                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
 237
 238                 ret = read_poll_timeout(readl, host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
 239                                         val, DLL_LOCK_WO_TMOUT(val), 1, 500);
 240                 if (ret)
 241                         return ret;
 242
 243                 extra = DWCMSHC_EMMC_DLL_DLYENA |
 244                         DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 245                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 246
 247                 extra = DWCMSHC_EMMC_DLL_DLYENA |
 248                         DLL_TXCLK_TAPNUM_DEFAULT |
 249                         DLL_TXCLK_TAPNUM_FROM_SW;
 250                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
 251
 252                 extra = DWCMSHC_EMMC_DLL_DLYENA |
 253                         DLL_STRBIN_TAPNUM_DEFAULT;
 254                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 255         } else {
 256                 /* reset the clock phase when the frequency is lower than 100MHz */
 257                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
 258                 extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 259                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 260                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
 261                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
 262         }
 263
 264         return 0;
 265 }
 266
 267 static int rk3568_emmc_get_phy(struct udevice *dev)
 268 {
 269         return 0;
 270 }
 271
 272 static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
 273 {
 274         struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 275         struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
 276         struct mmc *mmc = host->mmc;
 277         uint clock = mmc->tran_speed;
 278         u32 reg;
 279
 280         if (!clock)
 281                 clock = mmc->clock;
 282
 283         if (data->emmc_set_clock)
 284                 data->emmc_set_clock(host, clock);
 285
 286         if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
 287                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 288                 reg &= ~SDHCI_CTRL_UHS_MASK;
 289                 reg |= SDHCI_CTRL_HS400;
 290                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 291         } else {
 292                 sdhci_set_uhs_timing(host);
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 299 {
 300         struct sdhci_host *host = dev_get_priv(mmc->dev);
 301         char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 302         struct mmc_cmd cmd;
 303         u32 ctrl, blk_size;
 304         int ret = 0;
 305
 306         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 307         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 308         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 309
 310         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 311         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 312
 313         blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
 314         if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width == 8)
 315                 blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
 316         sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE);
 317         sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 318
 319         cmd.cmdidx = opcode;
 320         cmd.resp_type = MMC_RSP_R1;
 321         cmd.cmdarg = 0;
 322
 323         do {
 324                 if (tuning_loop_counter-- == 0)
 325                         break;
 326
 327                 mmc_send_cmd(mmc, &cmd, NULL);
 328
 329                 if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
 330                         /*
 331                          * For tuning command, do not do busy loop. As tuning
 332                          * is happening (CLK-DATA latching for setup/hold time
 333                          * requirements), give time to complete
 334                          */
 335                         udelay(1);
 336
 337                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 338         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 339
 340         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 341                 printf("%s:Tuning failed\n", __func__);
 342                 ret = -EIO;
 343         }
 344
 345         if (tuning_loop_counter < 0) {
 346                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 347                 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 348         }
 349
 350         /* Enable only interrupts served by the SD controller */
 351         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE);
 352         /* Mask all sdhci interrupt sources */
 353         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 354
 355         return ret;
 356 }
 357
 358 static struct sdhci_ops rockchip_sdhci_ops = {
 359         .set_ios_post   = rockchip_sdhci_set_ios_post,
 360         .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
 361 };
 362
 363 static int rockchip_sdhci_probe(struct udevice *dev)
 364 {
 365         struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
 366         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 367         struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
 368         struct rockchip_sdhc *prv = dev_get_priv(dev);
 369         struct mmc_config *cfg = &plat->cfg;
 370         struct sdhci_host *host = &prv->host;
 371         struct clk clk;
 372         int ret;
 373
 374         host->max_clk = cfg->f_max;
 375         ret = clk_get_by_index(dev, 0, &clk);
 376         if (!ret) {
 377                 ret = clk_set_rate(&clk, host->max_clk);
 378                 if (IS_ERR_VALUE(ret))
 379                         printf("%s clk set rate fail!\n", __func__);
 380         } else {
 381                 printf("%s fail to get clk\n", __func__);
 382         }
 383
 384         prv->emmc_clk = clk;
 385         prv->dev = dev;
 386
 387         if (data->get_phy) {
 388                 ret = data->get_phy(dev);
 389                 if (ret)
 390                         return ret;
 391         }
 392
 393         if (data->emmc_phy_init) {
 394                 ret = data->emmc_phy_init(dev);
 395                 if (ret)
 396                         return ret;
 397         }
 398
 399         host->ops = &rockchip_sdhci_ops;
 400         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
 401
 402         host->mmc = &plat->mmc;
 403         host->mmc->priv = &prv->host;
 404         host->mmc->dev = dev;
 405         upriv->mmc = host->mmc;
 406
 407         ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ);
 408         if (ret)
 409                 return ret;
 410
 411         return sdhci_probe(dev);
 412 }
 413
 414 static int rockchip_sdhci_of_to_plat(struct udevice *dev)
 415 {
 416         struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
 417         struct sdhci_host *host = dev_get_priv(dev);
 418         struct mmc_config *cfg = &plat->cfg;
 419         int ret;
 420
 421         host->name = dev->name;
 422         host->ioaddr = dev_read_addr_ptr(dev);
 423
 424         ret = mmc_of_parse(dev, cfg);
 425         if (ret)
 426                 return ret;
 427
 428         return 0;
 429 }
 430
 431 static int rockchip_sdhci_bind(struct udevice *dev)
 432 {
 433         struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
 434
 435         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 436 }
 437
 438 static const struct sdhci_data rk3399_data = {
 439         .emmc_set_clock = rk3399_sdhci_emmc_set_clock,
 440         .get_phy = rk3399_emmc_get_phy,
 441         .emmc_phy_init = rk3399_emmc_phy_init,
 442 };
 443
 444 static const struct sdhci_data rk3568_data = {
 445         .emmc_set_clock = rk3568_sdhci_emmc_set_clock,
 446         .get_phy = rk3568_emmc_get_phy,
 447         .emmc_phy_init = rk3568_emmc_phy_init,
 448 };
 449
 450 static const struct udevice_id sdhci_ids[] = {
 451         {
 452                 .compatible = "arasan,sdhci-5.1",
 453                 .data = (ulong)&rk3399_data,
 454         },
 455         {
 456                 .compatible = "rockchip,rk3568-dwcmshc",
 457                 .data = (ulong)&rk3568_data,
 458         },
 459         { }
 460 };
 461
 462 U_BOOT_DRIVER(arasan_sdhci_drv) = {
 463         .name           = "rockchip_sdhci_5_1",
 464         .id             = UCLASS_MMC,
 465         .of_match       = sdhci_ids,
 466         .of_to_plat     = rockchip_sdhci_of_to_plat,
 467         .ops            = &sdhci_ops,
 468         .bind           = rockchip_sdhci_bind,
 469         .probe          = rockchip_sdhci_probe,
 470         .priv_auto      = sizeof(struct rockchip_sdhc),
 471         .plat_auto      = sizeof(struct rockchip_sdhc_plat),
 472 };