drivers/mmc/rockchip_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
   4  *
   5  * Rockchip SD Host Controller Interface
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dm/ofnode.h>
  12 #include <dt-structs.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/libfdt.h>
  16 #include <linux/iopoll.h>
  17 #include <malloc.h>
  18 #include <mapmem.h>
  19 #include "mmc_private.h"
  20 #include <sdhci.h>
  21 #include <syscon.h>
  22 #include <asm/arch-rockchip/clock.h>
  23 #include <asm/arch-rockchip/hardware.h>
  24
  25 /* 400KHz is max freq for card ID etc. Use that as min */
  26 #define EMMC_MIN_FREQ   400000
  27 #define KHz     (1000)
  28 #define MHz     (1000 * KHz)
  29 #define SDHCI_TUNING_LOOP_COUNT         40
  30
  31 #define PHYCTRL_CALDONE_MASK            0x1
  32 #define PHYCTRL_CALDONE_SHIFT           0x6
  33 #define PHYCTRL_CALDONE_DONE            0x1
  34 #define PHYCTRL_DLLRDY_MASK             0x1
  35 #define PHYCTRL_DLLRDY_SHIFT            0x5
  36 #define PHYCTRL_DLLRDY_DONE             0x1
  37 #define PHYCTRL_FREQSEL_200M            0x0
  38 #define PHYCTRL_FREQSEL_50M             0x1
  39 #define PHYCTRL_FREQSEL_100M            0x2
  40 #define PHYCTRL_FREQSEL_150M            0x3
  41 #define PHYCTRL_DLL_LOCK_WO_TMOUT(x)    \
  42         ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
  43         PHYCTRL_DLLRDY_DONE)
  44
  45 /* Rockchip specific Registers */
  46 #define DWCMSHC_EMMC_DLL_CTRL           0x800
  47 #define DWCMSHC_EMMC_DLL_CTRL_RESET     BIT(1)
  48 #define DWCMSHC_EMMC_DLL_RXCLK          0x804
  49 #define DWCMSHC_EMMC_DLL_TXCLK          0x808
  50 #define DWCMSHC_EMMC_DLL_STRBIN         0x80c
  51 #define DWCMSHC_EMMC_DLL_STATUS0        0x840
  52 #define DWCMSHC_EMMC_DLL_STATUS1        0x844
  53 #define DWCMSHC_EMMC_DLL_START          BIT(0)
  54 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL   29
  55 #define DWCMSHC_EMMC_DLL_START_POINT    16
  56 #define DWCMSHC_EMMC_DLL_START_DEFAULT  5
  57 #define DWCMSHC_EMMC_DLL_INC_VALUE      2
  58 #define DWCMSHC_EMMC_DLL_INC            8
  59 #define DWCMSHC_EMMC_DLL_DLYENA         BIT(27)
  60 #define DLL_TXCLK_TAPNUM_DEFAULT        0x10
  61 #define DLL_STRBIN_TAPNUM_DEFAULT       0x3
  62 #define DLL_TXCLK_TAPNUM_FROM_SW        BIT(24)
  63 #define DWCMSHC_EMMC_DLL_LOCKED         BIT(8)
  64 #define DWCMSHC_EMMC_DLL_TIMEOUT        BIT(9)
  65 #define DLL_RXCLK_NO_INVERTER           1
  66 #define DLL_RXCLK_INVERTER              0
  67 #define DWCMSHC_ENHANCED_STROBE         BIT(8)
  68 #define DLL_LOCK_WO_TMOUT(x) \
  69         ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
  70         (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
  71 #define ROCKCHIP_MAX_CLKS               3
  72
  73 struct rockchip_sdhc_plat {
  74         struct mmc_config cfg;
  75         struct mmc mmc;
  76 };
  77
  78 struct rockchip_emmc_phy {
  79         u32 emmcphy_con[7];
  80         u32 reserved;
  81         u32 emmcphy_status;
  82 };
  83
  84 struct rockchip_sdhc {
  85         struct sdhci_host host;
  86         struct udevice *dev;
  87         void *base;
  88         struct rockchip_emmc_phy *phy;
  89         struct clk emmc_clk;
  90 };
  91
  92 struct sdhci_data {
  93         int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
  94         int (*emmc_phy_init)(struct udevice *dev);
  95         int (*get_phy)(struct udevice *dev);
  96 };
  97
  98 static int rk3399_emmc_phy_init(struct udevice *dev)
  99 {
 100         return 0;
 101 }
 102
 103 static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
 104 {
 105         u32 caldone, dllrdy, freqsel;
 106
 107         writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]);
 108         writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]);
 109         writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]);
 110
 111         /*
 112          * According to the user manual, calpad calibration
 113          * cycle takes more than 2us without the minimal recommended
 114          * value, so we may need a little margin here
 115          */
 116         udelay(3);
 117         writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]);
 118
 119         /*
 120          * According to the user manual, it asks driver to
 121          * wait 5us for calpad busy trimming. But it seems that
 122          * 5us of caldone isn't enough for all cases.
 123          */
 124         udelay(500);
 125         caldone = readl(&phy->emmcphy_status);
 126         caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
 127         if (caldone != PHYCTRL_CALDONE_DONE) {
 128                 printf("%s: caldone timeout.\n", __func__);
 129                 return;
 130         }
 131
 132         /* Set the frequency of the DLL operation */
 133         if (clock < 75 * MHz)
 134                 freqsel = PHYCTRL_FREQSEL_50M;
 135         else if (clock < 125 * MHz)
 136                 freqsel = PHYCTRL_FREQSEL_100M;
 137         else if (clock < 175 * MHz)
 138                 freqsel = PHYCTRL_FREQSEL_150M;
 139         else
 140                 freqsel = PHYCTRL_FREQSEL_200M;
 141
 142         /* Set the frequency of the DLL operation */
 143         writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
 144         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
 145
 146         read_poll_timeout(readl, &phy->emmcphy_status, dllrdy,
 147                           PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
 148 }
 149
 150 static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
 151 {
 152         writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]);
 153         writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]);
 154 }
 155
 156 static int rk3399_emmc_get_phy(struct udevice *dev)
 157 {
 158         struct rockchip_sdhc *priv = dev_get_priv(dev);
 159         ofnode phy_node;
 160         void *grf_base;
 161         u32 grf_phy_offset, phandle;
 162
 163         phandle = dev_read_u32_default(dev, "phys", 0);
 164         phy_node = ofnode_get_by_phandle(phandle);
 165         if (!ofnode_valid(phy_node)) {
 166                 debug("Not found emmc phy device\n");
 167                 return -ENODEV;
 168         }
 169
 170         grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 171         if (grf_base < 0) {
 172                 printf("%s Get syscon grf failed", __func__);
 173                 return -ENODEV;
 174         }
 175         grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0);
 176
 177         priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset);
 178
 179         return 0;
 180 }
 181
 182 static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
 183 {
 184         struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 185         int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
 186
 187         if (cycle_phy)
 188                 rk3399_emmc_phy_power_off(priv->phy);
 189
 190         sdhci_set_clock(host->mmc, clock);
 191
 192         if (cycle_phy)
 193                 rk3399_emmc_phy_power_on(priv->phy, clock);
 194
 195         return 0;
 196 }
 197
 198 static int rk3568_emmc_phy_init(struct udevice *dev)
 199 {
 200         struct rockchip_sdhc *prv = dev_get_priv(dev);
 201         struct sdhci_host *host = &prv->host;
 202         u32 extra;
 203
 204         extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 205         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 206
 207         return 0;
 208 }
 209
 210 static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
 211 {
 212         struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 213         int val, ret;
 214         u32 extra;
 215
 216         if (clock > host->max_clk)
 217                 clock = host->max_clk;
 218         if (clock)
 219                 clk_set_rate(&priv->emmc_clk, clock);
 220
 221         sdhci_set_clock(host->mmc, clock);
 222
 223         if (clock >= 100 * MHz) {
 224                 /* reset DLL */
 225                 sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
 226                 udelay(1);
 227                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
 228
 229                 /* Init DLL settings */
 230                 extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
 231                         DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
 232                         DWCMSHC_EMMC_DLL_START;
 233                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
 234
 235                 ret = read_poll_timeout(readl, host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
 236                                         val, DLL_LOCK_WO_TMOUT(val), 1, 500);
 237                 if (ret)
 238                         return ret;
 239
 240                 extra = DWCMSHC_EMMC_DLL_DLYENA |
 241                         DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 242                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 243
 244                 extra = DWCMSHC_EMMC_DLL_DLYENA |
 245                         DLL_TXCLK_TAPNUM_DEFAULT |
 246                         DLL_TXCLK_TAPNUM_FROM_SW;
 247                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
 248
 249                 extra = DWCMSHC_EMMC_DLL_DLYENA |
 250                         DLL_STRBIN_TAPNUM_DEFAULT;
 251                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 252         } else {
 253                 /* reset the clock phase when the frequency is lower than 100MHz */
 254                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
 255                 extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 256                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 257                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
 258                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
 259         }
 260
 261         return 0;
 262 }
 263
 264 static int rk3568_emmc_get_phy(struct udevice *dev)
 265 {
 266         return 0;
 267 }
 268
 269 static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
 270 {
 271         struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 272         struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
 273         struct mmc *mmc = host->mmc;
 274         uint clock = mmc->tran_speed;
 275         u32 reg;
 276
 277         if (!clock)
 278                 clock = mmc->clock;
 279
 280         if (data->emmc_set_clock)
 281                 data->emmc_set_clock(host, clock);
 282
 283         if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
 284                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 285                 reg &= ~SDHCI_CTRL_UHS_MASK;
 286                 reg |= SDHCI_CTRL_HS400;
 287                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 288         } else {
 289                 sdhci_set_uhs_timing(host);
 290         }
 291
 292         return 0;
 293 }
 294
 295 static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 296 {
 297         struct sdhci_host *host = dev_get_priv(mmc->dev);
 298         char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 299         struct mmc_cmd cmd;
 300         u32 ctrl, blk_size;
 301         int ret = 0;
 302
 303         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 304         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 305         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 306
 307         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 308         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 309
 310         blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
 311         if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width == 8)
 312                 blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
 313         sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE);
 314         sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 315
 316         cmd.cmdidx = opcode;
 317         cmd.resp_type = MMC_RSP_R1;
 318         cmd.cmdarg = 0;
 319
 320         do {
 321                 if (tuning_loop_counter-- == 0)
 322                         break;
 323
 324                 mmc_send_cmd(mmc, &cmd, NULL);
 325
 326                 if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
 327                         /*
 328                          * For tuning command, do not do busy loop. As tuning
 329                          * is happening (CLK-DATA latching for setup/hold time
 330                          * requirements), give time to complete
 331                          */
 332                         udelay(1);
 333
 334                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 335         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 336
 337         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 338                 printf("%s:Tuning failed\n", __func__);
 339                 ret = -EIO;
 340         }
 341
 342         if (tuning_loop_counter < 0) {
 343                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 344                 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 345         }
 346
 347         /* Enable only interrupts served by the SD controller */
 348         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE);
 349         /* Mask all sdhci interrupt sources */
 350         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 351
 352         return ret;
 353 }
 354
 355 static struct sdhci_ops rockchip_sdhci_ops = {
 356         .set_ios_post   = rockchip_sdhci_set_ios_post,
 357         .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
 358 };
 359
 360 static int rockchip_sdhci_probe(struct udevice *dev)
 361 {
 362         struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
 363         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 364         struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
 365         struct rockchip_sdhc *prv = dev_get_priv(dev);
 366         struct mmc_config *cfg = &plat->cfg;
 367         struct sdhci_host *host = &prv->host;
 368         struct clk clk;
 369         int ret;
 370
 371         host->max_clk = cfg->f_max;
 372         ret = clk_get_by_index(dev, 0, &clk);
 373         if (!ret) {
 374                 ret = clk_set_rate(&clk, host->max_clk);
 375                 if (IS_ERR_VALUE(ret))
 376                         printf("%s clk set rate fail!\n", __func__);
 377         } else {
 378                 printf("%s fail to get clk\n", __func__);
 379         }
 380
 381         prv->emmc_clk = clk;
 382         prv->dev = dev;
 383
 384         if (data->get_phy) {
 385                 ret = data->get_phy(dev);
 386                 if (ret)
 387                         return ret;
 388         }
 389
 390         if (data->emmc_phy_init) {
 391                 ret = data->emmc_phy_init(dev);
 392                 if (ret)
 393                         return ret;
 394         }
 395
 396         host->ops = &rockchip_sdhci_ops;
 397         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
 398
 399         host->mmc = &plat->mmc;
 400         host->mmc->priv = &prv->host;
 401         host->mmc->dev = dev;
 402         upriv->mmc = host->mmc;
 403
 404         ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ);
 405         if (ret)
 406                 return ret;
 407
 408         return sdhci_probe(dev);
 409 }
 410
 411 static int rockchip_sdhci_of_to_plat(struct udevice *dev)
 412 {
 413         struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
 414         struct sdhci_host *host = dev_get_priv(dev);
 415         struct mmc_config *cfg = &plat->cfg;
 416         int ret;
 417
 418         host->name = dev->name;
 419         host->ioaddr = dev_read_addr_ptr(dev);
 420
 421         ret = mmc_of_parse(dev, cfg);
 422         if (ret)
 423                 return ret;
 424
 425         return 0;
 426 }
 427
 428 static int rockchip_sdhci_bind(struct udevice *dev)
 429 {
 430         struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
 431
 432         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 433 }
 434
 435 static const struct sdhci_data rk3399_data = {
 436         .emmc_set_clock = rk3399_sdhci_emmc_set_clock,
 437         .get_phy = rk3399_emmc_get_phy,
 438         .emmc_phy_init = rk3399_emmc_phy_init,
 439 };
 440
 441 static const struct sdhci_data rk3568_data = {
 442         .emmc_set_clock = rk3568_sdhci_emmc_set_clock,
 443         .get_phy = rk3568_emmc_get_phy,
 444         .emmc_phy_init = rk3568_emmc_phy_init,
 445 };
 446
 447 static const struct udevice_id sdhci_ids[] = {
 448         {
 449                 .compatible = "arasan,sdhci-5.1",
 450                 .data = (ulong)&rk3399_data,
 451         },
 452         {
 453                 .compatible = "rockchip,rk3568-dwcmshc",
 454                 .data = (ulong)&rk3568_data,
 455         },
 456         { }
 457 };
 458
 459 U_BOOT_DRIVER(arasan_sdhci_drv) = {
 460         .name           = "rockchip_sdhci_5_1",
 461         .id             = UCLASS_MMC,
 462         .of_match       = sdhci_ids,
 463         .of_to_plat     = rockchip_sdhci_of_to_plat,
 464         .ops            = &sdhci_ops,
 465         .bind           = rockchip_sdhci_bind,
 466         .probe          = rockchip_sdhci_probe,
 467         .priv_auto      = sizeof(struct rockchip_sdhc),
 468         .plat_auto      = sizeof(struct rockchip_sdhc_plat),
 469 };