1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2013 Google, Inc
9 #include <dt-structs.h>
17 #include <asm/arch-rockchip/clock.h>
18 #include <asm/arch-rockchip/periph.h>
19 #include <linux/err.h>
21 struct rockchip_mmc_plat {
22 #if CONFIG_IS_ENABLED(OF_PLATDATA)
23 struct dtd_rockchip_rk3288_dw_mshc dtplat;
25 struct mmc_config cfg;
29 struct rockchip_dwmmc_priv {
31 struct dwmci_host host;
37 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
39 struct udevice *dev = host->priv;
40 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
43 ret = clk_set_rate(&priv->clk, freq);
45 debug("%s: err=%d\n", __func__, ret);
52 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
54 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
55 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
56 struct dwmci_host *host = &priv->host;
58 host->name = dev->name;
59 host->ioaddr = dev_read_addr_ptr(dev);
60 host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
61 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
64 /* use non-removeable as sdcard and emmc as judgement */
65 if (dev_read_bool(dev, "non-removable"))
70 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
72 if (priv->fifo_depth < 0)
74 priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
76 #ifdef CONFIG_SPL_BUILD
78 priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
82 * 'clock-freq-min-max' is deprecated
83 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
85 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
86 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
91 priv->minmax[0] = 400000; /* 400 kHz */
92 priv->minmax[1] = val;
94 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
101 static int rockchip_dwmmc_probe(struct udevice *dev)
103 struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
104 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
105 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
106 struct dwmci_host *host = &priv->host;
107 struct udevice *pwr_dev __maybe_unused;
110 #if CONFIG_IS_ENABLED(OF_PLATDATA)
111 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
113 host->name = dev->name;
114 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
115 host->buswidth = dtplat->bus_width;
116 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
119 priv->fifo_depth = dtplat->fifo_depth;
121 priv->minmax[0] = 400000; /* 400 kHz */
122 priv->minmax[1] = dtplat->max_frequency;
124 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
128 ret = clk_get_by_index(dev, 0, &priv->clk);
132 host->fifoth_val = MSIZE(0x2) |
133 RX_WMARK(priv->fifo_depth / 2 - 1) |
134 TX_WMARK(priv->fifo_depth / 2);
136 host->fifo_mode = priv->fifo_mode;
139 /* Enable power if needed */
140 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
143 ret = pwrseq_set_power(pwr_dev, true);
148 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
149 host->mmc = &plat->mmc;
150 host->mmc->priv = &priv->host;
151 host->mmc->dev = dev;
152 upriv->mmc = host->mmc;
154 return dwmci_probe(dev);
157 static int rockchip_dwmmc_bind(struct udevice *dev)
159 struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
161 return dwmci_bind(dev, &plat->mmc, &plat->cfg);
164 static const struct udevice_id rockchip_dwmmc_ids[] = {
165 { .compatible = "rockchip,rk2928-dw-mshc" },
166 { .compatible = "rockchip,rk3288-dw-mshc" },
170 U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
171 .name = "rockchip_rk3288_dw_mshc",
173 .of_match = rockchip_dwmmc_ids,
174 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
175 .ops = &dm_dwmci_ops,
176 .bind = rockchip_dwmmc_bind,
177 .probe = rockchip_dwmmc_probe,
178 .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
179 .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
183 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
185 struct gpio_desc reset;
188 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
191 dm_gpio_set_value(&reset, 1);
193 dm_gpio_set_value(&reset, 0);
199 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
200 .set_power = rockchip_dwmmc_pwrseq_set_power,
203 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
204 { .compatible = "mmc-pwrseq-emmc" },
208 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
209 .name = "mmc_pwrseq_emmc",
211 .of_match = rockchip_dwmmc_pwrseq_ids,
212 .ops = &rockchip_dwmmc_pwrseq_ops,