drivers/mmc/rockchip_dw_mmc.c

   1 /*
   2  * Copyright (c) 2013 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <dwmmc.h>
  11 #include <errno.h>
  12 #include <pwrseq.h>
  13 #include <syscon.h>
  14 #include <asm/gpio.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/periph.h>
  17 #include <linux/err.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 struct rockchip_mmc_plat {
  22         struct mmc_config cfg;
  23         struct mmc mmc;
  24 };
  25
  26 struct rockchip_dwmmc_priv {
  27         struct clk clk;
  28         struct dwmci_host host;
  29         int fifo_depth;
  30         bool fifo_mode;
  31         u32 minmax[2];
  32 };
  33
  34 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
  35 {
  36         struct udevice *dev = host->priv;
  37         struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  38         int ret;
  39
  40         ret = clk_set_rate(&priv->clk, freq);
  41         if (ret < 0) {
  42                 debug("%s: err=%d\n", __func__, ret);
  43                 return ret;
  44         }
  45
  46         return freq;
  47 }
  48
  49 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
  50 {
  51         struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  52         struct dwmci_host *host = &priv->host;
  53
  54         host->name = dev->name;
  55         host->ioaddr = (void *)dev_get_addr(dev);
  56         host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
  57                                         "bus-width", 4);
  58         host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
  59         host->priv = dev;
  60
  61         /* use non-removeable as sdcard and emmc as judgement */
  62         if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
  63                 host->dev_index = 0;
  64         else
  65                 host->dev_index = 1;
  66
  67         priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
  68                                     "fifo-depth", 0);
  69         if (priv->fifo_depth < 0)
  70                 return -EINVAL;
  71         priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
  72                                           "fifo-mode");
  73         if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
  74                                  "clock-freq-min-max", priv->minmax, 2))
  75                 return -EINVAL;
  76
  77         return 0;
  78 }
  79
  80 static int rockchip_dwmmc_probe(struct udevice *dev)
  81 {
  82         struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
  83         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  84         struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  85         struct dwmci_host *host = &priv->host;
  86         struct udevice *pwr_dev __maybe_unused;
  87         int ret;
  88
  89         ret = clk_get_by_index(dev, 0, &priv->clk);
  90         if (ret < 0)
  91                 return ret;
  92
  93         host->fifoth_val = MSIZE(0x2) |
  94                 RX_WMARK(priv->fifo_depth / 2 - 1) |
  95                 TX_WMARK(priv->fifo_depth / 2);
  96
  97         host->fifo_mode = priv->fifo_mode;
  98
  99 #ifdef CONFIG_PWRSEQ
 100         /* Enable power if needed */
 101         ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
 102                                            &pwr_dev);
 103         if (!ret) {
 104                 ret = pwrseq_set_power(pwr_dev, true);
 105                 if (ret)
 106                         return ret;
 107         }
 108 #endif
 109         dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
 110                         priv->minmax[1], priv->minmax[0]);
 111         host->mmc = &plat->mmc;
 112         host->mmc->priv = &priv->host;
 113         host->mmc->dev = dev;
 114         upriv->mmc = host->mmc;
 115
 116         return dwmci_probe(dev);
 117 }
 118
 119 static int rockchip_dwmmc_bind(struct udevice *dev)
 120 {
 121         struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
 122         int ret;
 123
 124         ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
 125         if (ret)
 126                 return ret;
 127
 128         return 0;
 129 }
 130
 131 static const struct udevice_id rockchip_dwmmc_ids[] = {
 132         { .compatible = "rockchip,rk3288-dw-mshc" },
 133         { }
 134 };
 135
 136 U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
 137         .name           = "rockchip_dwmmc",
 138         .id             = UCLASS_MMC,
 139         .of_match       = rockchip_dwmmc_ids,
 140         .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
 141         .ops            = &dm_dwmci_ops,
 142         .bind           = rockchip_dwmmc_bind,
 143         .probe          = rockchip_dwmmc_probe,
 144         .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
 145         .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
 146 };
 147
 148 #ifdef CONFIG_PWRSEQ
 149 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
 150 {
 151         struct gpio_desc reset;
 152         int ret;
 153
 154         ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
 155         if (ret)
 156                 return ret;
 157         dm_gpio_set_value(&reset, 1);
 158         udelay(1);
 159         dm_gpio_set_value(&reset, 0);
 160         udelay(200);
 161
 162         return 0;
 163 }
 164
 165 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
 166         .set_power      = rockchip_dwmmc_pwrseq_set_power,
 167 };
 168
 169 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
 170         { .compatible = "mmc-pwrseq-emmc" },
 171         { }
 172 };
 173
 174 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
 175         .name           = "mmc_pwrseq_emmc",
 176         .id             = UCLASS_PWRSEQ,
 177         .of_match       = rockchip_dwmmc_pwrseq_ids,
 178         .ops            = &rockchip_dwmmc_pwrseq_ops,
 179 };
 180 #endif