1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2013 Google, Inc
9 #include <dt-structs.h>
17 #include <asm/arch-rockchip/clock.h>
18 #include <asm/arch-rockchip/periph.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
22 struct rockchip_mmc_plat {
23 #if CONFIG_IS_ENABLED(OF_PLATDATA)
24 struct dtd_rockchip_rk3288_dw_mshc dtplat;
26 struct mmc_config cfg;
30 struct rockchip_dwmmc_priv {
32 struct dwmci_host host;
38 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
40 struct udevice *dev = host->priv;
41 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
44 ret = clk_set_rate(&priv->clk, freq);
46 debug("%s: err=%d\n", __func__, ret);
53 static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
55 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
56 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
57 struct dwmci_host *host = &priv->host;
59 host->name = dev->name;
60 host->ioaddr = dev_read_addr_ptr(dev);
61 host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
62 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
65 /* use non-removeable as sdcard and emmc as judgement */
66 if (dev_read_bool(dev, "non-removable"))
71 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
73 if (priv->fifo_depth < 0)
75 priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
77 #ifdef CONFIG_SPL_BUILD
79 priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
83 * 'clock-freq-min-max' is deprecated
84 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
86 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
87 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
92 priv->minmax[0] = 400000; /* 400 kHz */
93 priv->minmax[1] = val;
95 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
102 static int rockchip_dwmmc_probe(struct udevice *dev)
104 struct rockchip_mmc_plat *plat = dev_get_plat(dev);
105 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
106 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
107 struct dwmci_host *host = &priv->host;
110 #if CONFIG_IS_ENABLED(OF_PLATDATA)
111 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
113 host->name = dev->name;
114 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
115 host->buswidth = dtplat->bus_width;
116 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
119 priv->fifo_depth = dtplat->fifo_depth;
121 priv->minmax[0] = 400000; /* 400 kHz */
122 priv->minmax[1] = dtplat->max_frequency;
124 ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
128 ret = clk_get_by_index(dev, 0, &priv->clk);
132 host->fifoth_val = MSIZE(0x2) |
133 RX_WMARK(priv->fifo_depth / 2 - 1) |
134 TX_WMARK(priv->fifo_depth / 2);
136 host->fifo_mode = priv->fifo_mode;
138 #ifdef CONFIG_MMC_PWRSEQ
139 /* Enable power if needed */
140 ret = mmc_pwrseq_get_power(dev, &plat->cfg);
142 ret = pwrseq_set_power(plat->cfg.pwr_dev, true);
147 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
148 host->mmc = &plat->mmc;
149 host->mmc->priv = &priv->host;
150 host->mmc->dev = dev;
151 upriv->mmc = host->mmc;
153 return dwmci_probe(dev);
156 static int rockchip_dwmmc_bind(struct udevice *dev)
158 struct rockchip_mmc_plat *plat = dev_get_plat(dev);
160 return dwmci_bind(dev, &plat->mmc, &plat->cfg);
163 static const struct udevice_id rockchip_dwmmc_ids[] = {
164 { .compatible = "rockchip,rk2928-dw-mshc" },
165 { .compatible = "rockchip,rk3288-dw-mshc" },
169 U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = {
170 .name = "rockchip_rk3288_dw_mshc",
172 .of_match = rockchip_dwmmc_ids,
173 .of_to_plat = rockchip_dwmmc_of_to_plat,
174 .ops = &dm_dwmci_ops,
175 .bind = rockchip_dwmmc_bind,
176 .probe = rockchip_dwmmc_probe,
177 .priv_auto = sizeof(struct rockchip_dwmmc_priv),
178 .plat_auto = sizeof(struct rockchip_mmc_plat),
181 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
182 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc)