drivers/mmc/rockchip_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2013 Google, Inc
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <dt-structs.h>
  10 #include <dwmmc.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <mapmem.h>
  14 #include <pwrseq.h>
  15 #include <syscon.h>
  16 #include <asm/gpio.h>
  17 #include <asm/arch-rockchip/clock.h>
  18 #include <asm/arch-rockchip/periph.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21
  22 struct rockchip_mmc_plat {
  23 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  24         struct dtd_rockchip_rk3288_dw_mshc dtplat;
  25 #endif
  26         struct mmc_config cfg;
  27         struct mmc mmc;
  28 };
  29
  30 struct rockchip_dwmmc_priv {
  31         struct clk clk;
  32         struct dwmci_host host;
  33         int fifo_depth;
  34         bool fifo_mode;
  35         u32 minmax[2];
  36 };
  37
  38 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
  39 {
  40         struct udevice *dev = host->priv;
  41         struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  42         int ret;
  43
  44         /*
  45          * The clock frequency chosen here affects CLKDIV in the dw_mmc core.
  46          * That can be either 0 or 1, but it must be set to 1 for eMMC DDR52
  47          * 8-bit mode.  It will be set to 0 for all other modes.
  48          */
  49         if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8)
  50                 freq *= 2;
  51
  52         ret = clk_set_rate(&priv->clk, freq);
  53         if (ret < 0) {
  54                 debug("%s: err=%d\n", __func__, ret);
  55                 return 0;
  56         }
  57
  58         return freq;
  59 }
  60
  61 static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
  62 {
  63         struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  64         struct dwmci_host *host = &priv->host;
  65
  66         if (!CONFIG_IS_ENABLED(OF_REAL))
  67                 return 0;
  68
  69         host->name = dev->name;
  70         host->ioaddr = dev_read_addr_ptr(dev);
  71         host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
  72         host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
  73         host->priv = dev;
  74
  75         /* use non-removeable as sdcard and emmc as judgement */
  76         if (dev_read_bool(dev, "non-removable"))
  77                 host->dev_index = 0;
  78         else
  79                 host->dev_index = 1;
  80
  81         priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
  82
  83         if (priv->fifo_depth < 0)
  84                 return -EINVAL;
  85         priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
  86
  87 #ifdef CONFIG_SPL_BUILD
  88         if (!priv->fifo_mode)
  89                 priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
  90 #endif
  91
  92         /*
  93          * 'clock-freq-min-max' is deprecated
  94          * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
  95          */
  96         if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
  97                 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
  98
  99                 if (val < 0)
 100                         return val;
 101
 102                 priv->minmax[0] = 400000;  /* 400 kHz */
 103                 priv->minmax[1] = val;
 104         } else {
 105                 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
 106                       __func__);
 107         }
 108
 109         return 0;
 110 }
 111
 112 static int rockchip_dwmmc_probe(struct udevice *dev)
 113 {
 114         struct rockchip_mmc_plat *plat = dev_get_plat(dev);
 115         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 116         struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 117         struct dwmci_host *host = &priv->host;
 118         int ret;
 119
 120 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 121         struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
 122
 123         host->name = dev->name;
 124         host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
 125         host->buswidth = dtplat->bus_width;
 126         host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
 127         host->priv = dev;
 128         host->dev_index = 0;
 129         priv->fifo_depth = dtplat->fifo_depth;
 130         priv->fifo_mode = dtplat->u_boot_spl_fifo_mode;
 131         priv->minmax[0] = 400000;  /*  400 kHz */
 132         priv->minmax[1] = dtplat->max_frequency;
 133
 134         ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
 135         if (ret < 0)
 136                 return ret;
 137 #else
 138         ret = clk_get_by_index(dev, 1, &priv->clk);
 139         if (ret < 0)
 140                 return ret;
 141 #endif
 142         host->fifoth_val = MSIZE(0x2) |
 143                 RX_WMARK(priv->fifo_depth / 2 - 1) |
 144                 TX_WMARK(priv->fifo_depth / 2);
 145
 146         host->fifo_mode = priv->fifo_mode;
 147
 148 #ifdef CONFIG_MMC_PWRSEQ
 149         /* Enable power if needed */
 150         ret = mmc_pwrseq_get_power(dev, &plat->cfg);
 151         if (!ret) {
 152                 ret = pwrseq_set_power(plat->cfg.pwr_dev, true);
 153                 if (ret)
 154                         return ret;
 155         }
 156 #endif
 157         dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
 158         host->mmc = &plat->mmc;
 159         host->mmc->priv = &priv->host;
 160         host->mmc->dev = dev;
 161         upriv->mmc = host->mmc;
 162
 163         return dwmci_probe(dev);
 164 }
 165
 166 static int rockchip_dwmmc_bind(struct udevice *dev)
 167 {
 168         struct rockchip_mmc_plat *plat = dev_get_plat(dev);
 169
 170         return dwmci_bind(dev, &plat->mmc, &plat->cfg);
 171 }
 172
 173 static const struct udevice_id rockchip_dwmmc_ids[] = {
 174         { .compatible = "rockchip,rk2928-dw-mshc" },
 175         { .compatible = "rockchip,rk3288-dw-mshc" },
 176         { }
 177 };
 178
 179 U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = {
 180         .name           = "rockchip_rk3288_dw_mshc",
 181         .id             = UCLASS_MMC,
 182         .of_match       = rockchip_dwmmc_ids,
 183         .of_to_plat = rockchip_dwmmc_of_to_plat,
 184         .ops            = &dm_dwmci_ops,
 185         .bind           = rockchip_dwmmc_bind,
 186         .probe          = rockchip_dwmmc_probe,
 187         .priv_auto      = sizeof(struct rockchip_dwmmc_priv),
 188         .plat_auto      = sizeof(struct rockchip_mmc_plat),
 189 };
 190
 191 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk2928_dw_mshc)
 192 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
 193 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc)