1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2013 Google, Inc
9 #include <dt-structs.h>
17 #include <asm/arch-rockchip/clock.h>
18 #include <asm/arch-rockchip/periph.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
22 struct rockchip_mmc_plat {
23 #if CONFIG_IS_ENABLED(OF_PLATDATA)
24 struct dtd_rockchip_rk3288_dw_mshc dtplat;
26 struct mmc_config cfg;
30 struct rockchip_dwmmc_priv {
32 struct dwmci_host host;
38 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
40 struct udevice *dev = host->priv;
41 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
44 ret = clk_set_rate(&priv->clk, freq);
46 debug("%s: err=%d\n", __func__, ret);
53 static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
55 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
56 struct dwmci_host *host = &priv->host;
58 if (!CONFIG_IS_ENABLED(OF_REAL))
61 host->name = dev->name;
62 host->ioaddr = dev_read_addr_ptr(dev);
63 host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
64 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
67 /* use non-removeable as sdcard and emmc as judgement */
68 if (dev_read_bool(dev, "non-removable"))
73 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
75 if (priv->fifo_depth < 0)
77 priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
79 #ifdef CONFIG_SPL_BUILD
81 priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
85 * 'clock-freq-min-max' is deprecated
86 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
88 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
89 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
94 priv->minmax[0] = 400000; /* 400 kHz */
95 priv->minmax[1] = val;
97 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
104 static int rockchip_dwmmc_probe(struct udevice *dev)
106 struct rockchip_mmc_plat *plat = dev_get_plat(dev);
107 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
108 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
109 struct dwmci_host *host = &priv->host;
112 #if CONFIG_IS_ENABLED(OF_PLATDATA)
113 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
115 host->name = dev->name;
116 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
117 host->buswidth = dtplat->bus_width;
118 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
121 priv->fifo_depth = dtplat->fifo_depth;
122 priv->fifo_mode = dtplat->u_boot_spl_fifo_mode;
123 priv->minmax[0] = 400000; /* 400 kHz */
124 priv->minmax[1] = dtplat->max_frequency;
126 ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
130 ret = clk_get_by_index(dev, 1, &priv->clk);
134 host->fifoth_val = MSIZE(0x2) |
135 RX_WMARK(priv->fifo_depth / 2 - 1) |
136 TX_WMARK(priv->fifo_depth / 2);
138 host->fifo_mode = priv->fifo_mode;
140 #ifdef CONFIG_MMC_PWRSEQ
141 /* Enable power if needed */
142 ret = mmc_pwrseq_get_power(dev, &plat->cfg);
144 ret = pwrseq_set_power(plat->cfg.pwr_dev, true);
149 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
150 host->mmc = &plat->mmc;
151 host->mmc->priv = &priv->host;
152 host->mmc->dev = dev;
153 upriv->mmc = host->mmc;
155 return dwmci_probe(dev);
158 static int rockchip_dwmmc_bind(struct udevice *dev)
160 struct rockchip_mmc_plat *plat = dev_get_plat(dev);
162 return dwmci_bind(dev, &plat->mmc, &plat->cfg);
165 static const struct udevice_id rockchip_dwmmc_ids[] = {
166 { .compatible = "rockchip,rk2928-dw-mshc" },
167 { .compatible = "rockchip,rk3288-dw-mshc" },
171 U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = {
172 .name = "rockchip_rk3288_dw_mshc",
174 .of_match = rockchip_dwmmc_ids,
175 .of_to_plat = rockchip_dwmmc_of_to_plat,
176 .ops = &dm_dwmci_ops,
177 .bind = rockchip_dwmmc_bind,
178 .probe = rockchip_dwmmc_probe,
179 .priv_auto = sizeof(struct rockchip_dwmmc_priv),
180 .plat_auto = sizeof(struct rockchip_mmc_plat),
183 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk2928_dw_mshc)
184 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
185 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc)