drivers/mmc/renesas-sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <fdtdec.h>
   9 #include <mmc.h>
  10 #include <dm.h>
  11 #include <linux/compat.h>
  12 #include <linux/dma-direction.h>
  13 #include <linux/io.h>
  14 #include <linux/sizes.h>
  15 #include <power/regulator.h>
  16 #include <asm/unaligned.h>
  17
  18 #include "tmio-common.h"
  19
  20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  21     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  22     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  23
  24 /* SCC registers */
  25 #define RENESAS_SDHI_SCC_DTCNTL                 0x800
  26 #define   RENESAS_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
  27 #define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
  28 #define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK           0xff
  29 #define RENESAS_SDHI_SCC_TAPSET                 0x804
  30 #define RENESAS_SDHI_SCC_DT2FF                  0x808
  31 #define RENESAS_SDHI_SCC_CKSEL                  0x80c
  32 #define   RENESAS_SDHI_SCC_CKSEL_DTSEL          BIT(0)
  33 #define RENESAS_SDHI_SCC_RVSCNTL                        0x810
  34 #define   RENESAS_SDHI_SCC_RVSCNTL_RVSEN                BIT(0)
  35 #define RENESAS_SDHI_SCC_RVSREQ                 0x814
  36 #define   RENESAS_SDHI_SCC_RVSREQ_RVSERR                BIT(2)
  37 #define RENESAS_SDHI_SCC_SMPCMP                 0x818
  38 #define RENESAS_SDHI_SCC_TMPPORT2                       0x81c
  39 #define   RENESAS_SDHI_SCC_TMPPORT2_HS400EN             BIT(31)
  40 #define   RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL           BIT(4)
  41
  42 #define RENESAS_SDHI_MAX_TAP 3
  43
  44 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
  45 {
  46         u32 reg;
  47
  48         /* Initialize SCC */
  49         tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
  50
  51         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  52         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  53         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  54
  55         /* Set sampling clock selection range */
  56         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
  57                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
  58                              RENESAS_SDHI_SCC_DTCNTL);
  59
  60         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  61         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
  62         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  63
  64         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  65         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  66         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  67
  68         tmio_sd_writel(priv, 0x300 /* scc_tappos */,
  69                            RENESAS_SDHI_SCC_DT2FF);
  70
  71         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  72         reg |= TMIO_SD_CLKCTL_SCLKEN;
  73         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  74
  75         /* Read TAPNUM */
  76         return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
  77                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
  78                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
  79 }
  80
  81 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
  82 {
  83         u32 reg;
  84
  85         /* Reset SCC */
  86         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  87         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  88         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  89
  90         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  91         reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
  92         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  93
  94         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
  95         reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
  96                  RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
  97         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
  98
  99         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 100         reg |= TMIO_SD_CLKCTL_SCLKEN;
 101         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 102
 103         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 104         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 105         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 106
 107         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 108         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 109         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 110 }
 111
 112 static int renesas_sdhi_hs400(struct udevice *dev)
 113 {
 114         struct tmio_sd_priv *priv = dev_get_priv(dev);
 115         struct mmc *mmc = mmc_get_mmc_dev(dev);
 116         bool hs400 = (mmc->selected_mode == MMC_HS_400);
 117         int ret, taps = hs400 ? priv->nrtaps : 8;
 118         u32 reg;
 119
 120         if (taps == 4)  /* HS400 on 4tap SoC needs different clock */
 121                 ret = clk_set_rate(&priv->clk, 400000000);
 122         else
 123                 ret = clk_set_rate(&priv->clk, 200000000);
 124         if (ret < 0)
 125                 return ret;
 126
 127         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 128
 129         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 130         if (hs400) {
 131                 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 132                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
 133         } else {
 134                 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 135                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 136         }
 137
 138         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 139
 140         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 141                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 142                              RENESAS_SDHI_SCC_DTCNTL);
 143
 144         if (taps == 4) {
 145                 tmio_sd_writel(priv, priv->tap_set >> 1,
 146                                RENESAS_SDHI_SCC_TAPSET);
 147         } else {
 148                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 149         }
 150
 151         tmio_sd_writel(priv, hs400 ? 0x704 : 0x300,
 152                        RENESAS_SDHI_SCC_DT2FF);
 153
 154         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 155         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 156         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 157
 158         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 159         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 160         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 161
 162         return 0;
 163 }
 164
 165 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 166                                        unsigned long tap)
 167 {
 168         /* Set sampling clock position */
 169         tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 170 }
 171
 172 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 173 {
 174         /* Get comparison of sampling data */
 175         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 176 }
 177
 178 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 179                                      unsigned int tap_num, unsigned int taps,
 180                                      unsigned int smpcmp)
 181 {
 182         unsigned long tap_cnt;  /* counter of tuning success */
 183         unsigned long tap_start;/* start position of tuning success */
 184         unsigned long tap_end;  /* end position of tuning success */
 185         unsigned long ntap;     /* temporary counter of tuning success */
 186         unsigned long match_cnt;/* counter of matching data */
 187         unsigned long i;
 188         bool select = false;
 189         u32 reg;
 190
 191         /* Clear SCC_RVSREQ */
 192         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 193
 194         /* Merge the results */
 195         for (i = 0; i < tap_num * 2; i++) {
 196                 if (!(taps & BIT(i))) {
 197                         taps &= ~BIT(i % tap_num);
 198                         taps &= ~BIT((i % tap_num) + tap_num);
 199                 }
 200                 if (!(smpcmp & BIT(i))) {
 201                         smpcmp &= ~BIT(i % tap_num);
 202                         smpcmp &= ~BIT((i % tap_num) + tap_num);
 203                 }
 204         }
 205
 206         /*
 207          * Find the longest consecutive run of successful probes.  If that
 208          * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 209          * center index as the tap.
 210          */
 211         tap_cnt = 0;
 212         ntap = 0;
 213         tap_start = 0;
 214         tap_end = 0;
 215         for (i = 0; i < tap_num * 2; i++) {
 216                 if (taps & BIT(i))
 217                         ntap++;
 218                 else {
 219                         if (ntap > tap_cnt) {
 220                                 tap_start = i - ntap;
 221                                 tap_end = i - 1;
 222                                 tap_cnt = ntap;
 223                         }
 224                         ntap = 0;
 225                 }
 226         }
 227
 228         if (ntap > tap_cnt) {
 229                 tap_start = i - ntap;
 230                 tap_end = i - 1;
 231                 tap_cnt = ntap;
 232         }
 233
 234         /*
 235          * If all of the TAP is OK, the sampling clock position is selected by
 236          * identifying the change point of data.
 237          */
 238         if (tap_cnt == tap_num * 2) {
 239                 match_cnt = 0;
 240                 ntap = 0;
 241                 tap_start = 0;
 242                 tap_end = 0;
 243                 for (i = 0; i < tap_num * 2; i++) {
 244                         if (smpcmp & BIT(i))
 245                                 ntap++;
 246                         else {
 247                                 if (ntap > match_cnt) {
 248                                         tap_start = i - ntap;
 249                                         tap_end = i - 1;
 250                                         match_cnt = ntap;
 251                                 }
 252                                 ntap = 0;
 253                         }
 254                 }
 255                 if (ntap > match_cnt) {
 256                         tap_start = i - ntap;
 257                         tap_end = i - 1;
 258                         match_cnt = ntap;
 259                 }
 260                 if (match_cnt)
 261                         select = true;
 262         } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 263                 select = true;
 264
 265         if (select)
 266                 priv->tap_set = ((tap_start + tap_end) / 2) % tap_num;
 267         else
 268                 return -EIO;
 269
 270         /* Set SCC */
 271         tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 272
 273         /* Enable auto re-tuning */
 274         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 275         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 276         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 277
 278         return 0;
 279 }
 280
 281 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 282 {
 283         struct tmio_sd_priv *priv = dev_get_priv(dev);
 284         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 285         struct mmc *mmc = upriv->mmc;
 286         unsigned int tap_num;
 287         unsigned int taps = 0, smpcmp = 0;
 288         int i, ret = 0;
 289         u32 caps;
 290
 291         /* Only supported on Renesas RCar */
 292         if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 293                 return -EINVAL;
 294
 295         /* clock tuning is not needed for upto 52MHz */
 296         if (!((mmc->selected_mode == MMC_HS_200) ||
 297               (mmc->selected_mode == MMC_HS_400) ||
 298               (mmc->selected_mode == UHS_SDR104) ||
 299               (mmc->selected_mode == UHS_SDR50)))
 300                 return 0;
 301
 302         tap_num = renesas_sdhi_init_tuning(priv);
 303         if (!tap_num)
 304                 /* Tuning is not supported */
 305                 goto out;
 306
 307         if (tap_num * 2 >= sizeof(taps) * 8) {
 308                 dev_err(dev,
 309                         "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 310                 goto out;
 311         }
 312
 313         /* Issue CMD19 twice for each tap */
 314         for (i = 0; i < 2 * tap_num; i++) {
 315                 renesas_sdhi_prepare_tuning(priv, i % tap_num);
 316
 317                 /* Force PIO for the tuning */
 318                 caps = priv->caps;
 319                 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 320
 321                 ret = mmc_send_tuning(mmc, opcode, NULL);
 322
 323                 priv->caps = caps;
 324
 325                 if (ret == 0)
 326                         taps |= BIT(i);
 327
 328                 ret = renesas_sdhi_compare_scc_data(priv);
 329                 if (ret == 0)
 330                         smpcmp |= BIT(i);
 331
 332                 mdelay(1);
 333         }
 334
 335         ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
 336
 337 out:
 338         if (ret < 0) {
 339                 dev_warn(dev, "Tuning procedure failed\n");
 340                 renesas_sdhi_reset_tuning(priv);
 341         }
 342
 343         return ret;
 344 }
 345 #else
 346 static int renesas_sdhi_hs400(struct udevice *dev)
 347 {
 348         return 0;
 349 }
 350 #endif
 351
 352 static int renesas_sdhi_set_ios(struct udevice *dev)
 353 {
 354         struct tmio_sd_priv *priv = dev_get_priv(dev);
 355         u32 tmp;
 356         int ret;
 357
 358         /* Stop the clock before changing its rate to avoid a glitch signal */
 359         tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 360         tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
 361         tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
 362
 363         ret = renesas_sdhi_hs400(dev);
 364         if (ret)
 365                 return ret;
 366
 367         ret = tmio_sd_set_ios(dev);
 368
 369         mdelay(10);
 370
 371 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 372     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 373     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 374         struct mmc *mmc = mmc_get_mmc_dev(dev);
 375         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 376             (mmc->selected_mode != UHS_SDR104) &&
 377             (mmc->selected_mode != MMC_HS_200) &&
 378             (mmc->selected_mode != MMC_HS_400)) {
 379                 renesas_sdhi_reset_tuning(priv);
 380         }
 381 #endif
 382
 383         return ret;
 384 }
 385
 386 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 387 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
 388 {
 389         int ret = -ETIMEDOUT;
 390         bool dat0_high;
 391         bool target_dat0_high = !!state;
 392         struct tmio_sd_priv *priv = dev_get_priv(dev);
 393
 394         timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
 395         while (timeout--) {
 396                 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
 397                 if (dat0_high == target_dat0_high) {
 398                         ret = 0;
 399                         break;
 400                 }
 401                 udelay(10);
 402         }
 403
 404         return ret;
 405 }
 406 #endif
 407
 408 static const struct dm_mmc_ops renesas_sdhi_ops = {
 409         .send_cmd = tmio_sd_send_cmd,
 410         .set_ios = renesas_sdhi_set_ios,
 411         .get_cd = tmio_sd_get_cd,
 412 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 413     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 414     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 415         .execute_tuning = renesas_sdhi_execute_tuning,
 416 #endif
 417 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 418         .wait_dat0 = renesas_sdhi_wait_dat0,
 419 #endif
 420 };
 421
 422 #define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 423 #define RENESAS_GEN3_QUIRKS                             \
 424         TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 425
 426 static const struct udevice_id renesas_sdhi_match[] = {
 427         { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 428         { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 429         { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 430         { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 431         { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 432         { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 433         { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 434         { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 435         { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 436         { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 437         { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 438         { /* sentinel */ }
 439 };
 440
 441 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 442 {
 443         return clk_get_rate(&priv->clk);
 444 }
 445
 446 static void renesas_sdhi_filter_caps(struct udevice *dev)
 447 {
 448         struct tmio_sd_plat *plat = dev_get_platdata(dev);
 449         struct tmio_sd_priv *priv = dev_get_priv(dev);
 450
 451         if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
 452                 return;
 453
 454         /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */
 455         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 456             (rmobile_get_cpu_rev_integer() <= 1)) ||
 457             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 458             (rmobile_get_cpu_rev_integer() == 1) &&
 459             (rmobile_get_cpu_rev_fraction() <= 1)))
 460                 plat->cfg.host_caps &= ~MMC_MODE_HS400;
 461
 462         /* H3 ES2.0 uses 4 tuning taps */
 463         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 464             (rmobile_get_cpu_rev_integer() == 2))
 465                 priv->nrtaps = 4;
 466         else
 467                 priv->nrtaps = 8;
 468
 469         /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
 470         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 471             (rmobile_get_cpu_rev_integer() <= 1)) ||
 472             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 473             (rmobile_get_cpu_rev_integer() == 1) &&
 474             (rmobile_get_cpu_rev_fraction() == 0)))
 475                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
 476         else
 477                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
 478 }
 479
 480 static int renesas_sdhi_probe(struct udevice *dev)
 481 {
 482         struct tmio_sd_priv *priv = dev_get_priv(dev);
 483         u32 quirks = dev_get_driver_data(dev);
 484         struct fdt_resource reg_res;
 485         DECLARE_GLOBAL_DATA_PTR;
 486         int ret;
 487
 488         priv->clk_get_rate = renesas_sdhi_clk_get_rate;
 489
 490         if (quirks == RENESAS_GEN2_QUIRKS) {
 491                 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 492                                        "reg", 0, &reg_res);
 493                 if (ret < 0) {
 494                         dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 495                                 ret);
 496                         return ret;
 497                 }
 498
 499                 if (fdt_resource_size(&reg_res) == 0x100)
 500                         quirks |= TMIO_SD_CAP_16BIT;
 501         }
 502
 503         ret = clk_get_by_index(dev, 0, &priv->clk);
 504         if (ret < 0) {
 505                 dev_err(dev, "failed to get host clock\n");
 506                 return ret;
 507         }
 508
 509         /* set to max rate */
 510         ret = clk_set_rate(&priv->clk, 200000000);
 511         if (ret < 0) {
 512                 dev_err(dev, "failed to set rate for host clock\n");
 513                 clk_free(&priv->clk);
 514                 return ret;
 515         }
 516
 517         ret = clk_enable(&priv->clk);
 518         if (ret) {
 519                 dev_err(dev, "failed to enable host clock\n");
 520                 return ret;
 521         }
 522
 523         ret = tmio_sd_probe(dev, quirks);
 524
 525         renesas_sdhi_filter_caps(dev);
 526
 527 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 528     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 529     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 530         if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
 531                 renesas_sdhi_reset_tuning(priv);
 532 #endif
 533         return ret;
 534 }
 535
 536 U_BOOT_DRIVER(renesas_sdhi) = {
 537         .name = "renesas-sdhi",
 538         .id = UCLASS_MMC,
 539         .of_match = renesas_sdhi_match,
 540         .bind = tmio_sd_bind,
 541         .probe = renesas_sdhi_probe,
 542         .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
 543         .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
 544         .ops = &renesas_sdhi_ops,
 545 };