drivers/mmc/renesas-sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <bouncebuf.h>
   8 #include <clk.h>
   9 #include <fdtdec.h>
  10 #include <log.h>
  11 #include <malloc.h>
  12 #include <mmc.h>
  13 #include <dm.h>
  14 #include <asm/global_data.h>
  15 #include <dm/device_compat.h>
  16 #include <linux/bitops.h>
  17 #include <linux/compat.h>
  18 #include <linux/delay.h>
  19 #include <linux/dma-direction.h>
  20 #include <linux/io.h>
  21 #include <linux/sizes.h>
  22 #include <power/regulator.h>
  23 #include <asm/unaligned.h>
  24 #include "tmio-common.h"
  25
  26 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  27     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  28     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  29
  30 /* SCC registers */
  31 #define RENESAS_SDHI_SCC_DTCNTL                 0x800
  32 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN           BIT(0)
  33 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT    16
  34 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK     0xff
  35 #define RENESAS_SDHI_SCC_TAPSET                 0x804
  36 #define RENESAS_SDHI_SCC_DT2FF                  0x808
  37 #define RENESAS_SDHI_SCC_CKSEL                  0x80c
  38 #define RENESAS_SDHI_SCC_CKSEL_DTSEL            BIT(0)
  39 #define RENESAS_SDHI_SCC_RVSCNTL                0x810
  40 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN          BIT(0)
  41 #define RENESAS_SDHI_SCC_RVSREQ                 0x814
  42 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR          BIT(2)
  43 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP        BIT(1)
  44 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN      BIT(0)
  45 #define RENESAS_SDHI_SCC_SMPCMP                 0x818
  46 #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR         (BIT(24) | BIT(8))
  47 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP       BIT(24)
  48 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN     BIT(8)
  49 #define RENESAS_SDHI_SCC_TMPPORT2               0x81c
  50 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN       BIT(31)
  51 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL     BIT(4)
  52 #define RENESAS_SDHI_SCC_TMPPORT3               0x828
  53 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0      3
  54 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1      2
  55 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2      1
  56 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3      0
  57 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK   0x3
  58 #define RENESAS_SDHI_SCC_TMPPORT4               0x82c
  59 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  60 #define RENESAS_SDHI_SCC_TMPPORT5               0x830
  61 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R  BIT(8)
  62 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W  (0 << 8)
  63 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK  0x3F
  64 #define RENESAS_SDHI_SCC_TMPPORT6               0x834
  65 #define RENESAS_SDHI_SCC_TMPPORT7               0x838
  66 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE        0xa5000000
  67 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK        0x1f
  68 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE            BIT(7)
  69
  70 #define RENESAS_SDHI_MAX_TAP 3
  71
  72 #define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
  73
  74 static const u8 r8a7796_rev13_calib_table[2][CALIB_TABLE_MAX] = {
  75         { 3,  3,  3,  3,  3,  3,  3,  4,  4,  5,  6,  7,  8,  9, 10, 15,
  76          16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
  77         { 5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  6,  7,  8, 11,
  78          12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
  79 };
  80
  81 static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
  82         { 1,  2,  6,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
  83          17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
  84         { 2,  3,  4,  4,  5,  6,  7,  9, 10, 11, 12, 13, 14, 15, 16, 17,
  85          17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
  86 };
  87
  88 static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
  89         { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
  90           0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },
  91         { 0,  0,  0,  1,  2,  3,  3,  4,  4,  4,  5,  5,  6,  8,  9, 10,
  92          11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
  93 };
  94
  95 static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
  96 {
  97         /* On R-Car Gen3, MMC0 is at 0xee140000 */
  98         return (uintptr_t)(priv->regbase) == 0xee140000;
  99 }
 100
 101 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
 102 {
 103         /* read mode */
 104         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
 105                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
 106                        RENESAS_SDHI_SCC_TMPPORT5);
 107
 108         /* access start and stop */
 109         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
 110                        RENESAS_SDHI_SCC_TMPPORT4);
 111         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
 112
 113         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
 114 }
 115
 116 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
 117 {
 118         /* write mode */
 119         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
 120                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
 121                        RENESAS_SDHI_SCC_TMPPORT5);
 122         tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
 123
 124         /* access start and stop */
 125         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
 126                        RENESAS_SDHI_SCC_TMPPORT4);
 127         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
 128 }
 129
 130 static bool renesas_sdhi_check_scc_error(struct udevice *dev)
 131 {
 132         struct tmio_sd_priv *priv = dev_get_priv(dev);
 133         struct mmc *mmc = mmc_get_mmc_dev(dev);
 134         unsigned long new_tap = priv->tap_set;
 135         unsigned long error_tap = priv->tap_set;
 136         u32 reg, smpcmp;
 137
 138         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 139             (mmc->selected_mode != UHS_SDR104) &&
 140             (mmc->selected_mode != MMC_HS_200) &&
 141             (mmc->selected_mode != MMC_HS_400) &&
 142             (priv->nrtaps != 4))
 143                 return false;
 144
 145         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 146         /* Handle automatic tuning correction */
 147         if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
 148                 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 149                 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
 150                         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 151                         return true;
 152                 }
 153
 154                 return false;
 155         }
 156
 157         /* Handle manual tuning correction */
 158         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 159         if (!reg)       /* No error */
 160                 return false;
 161
 162         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 163
 164         if (mmc->selected_mode == MMC_HS_400) {
 165                 /*
 166                  * Correction Error Status contains CMD and DAT signal status.
 167                  * In HS400, DAT signal based on DS signal, not CLK.
 168                  * Therefore, use only CMD status.
 169                  */
 170                 smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
 171                          RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
 172
 173                 switch (smpcmp) {
 174                 case 0:
 175                         return false;   /* No error in CMD signal */
 176                 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
 177                         new_tap = (priv->tap_set +
 178                                    priv->tap_num + 1) % priv->tap_num;
 179                         error_tap = (priv->tap_set +
 180                                      priv->tap_num - 1) % priv->tap_num;
 181                         break;
 182                 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
 183                         new_tap = (priv->tap_set +
 184                                    priv->tap_num - 1) % priv->tap_num;
 185                         error_tap = (priv->tap_set +
 186                                      priv->tap_num + 1) % priv->tap_num;
 187                         break;
 188                 default:
 189                         return true;    /* Need re-tune */
 190                 }
 191
 192                 if (priv->hs400_bad_tap & BIT(new_tap)) {
 193                         /*
 194                          * New tap is bad tap (cannot change).
 195                          * Compare with HS200 tuning result.
 196                          * In HS200 tuning, when smpcmp[error_tap]
 197                          * is OK, retune is executed.
 198                          */
 199                         if (priv->smpcmp & BIT(error_tap))
 200                                 return true;    /* Need retune */
 201
 202                         return false;   /* cannot change */
 203                 }
 204
 205                 priv->tap_set = new_tap;
 206         } else {
 207                 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
 208                         return true;    /* Need re-tune */
 209                 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
 210                         priv->tap_set = (priv->tap_set +
 211                                          priv->tap_num + 1) % priv->tap_num;
 212                 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
 213                         priv->tap_set = (priv->tap_set +
 214                                          priv->tap_num - 1) % priv->tap_num;
 215                 else
 216                         return false;
 217         }
 218
 219         /* Set TAP position */
 220         tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
 221                        RENESAS_SDHI_SCC_TAPSET);
 222
 223         return false;
 224 }
 225
 226 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
 227 {
 228         u32 calib_code;
 229
 230         if (!priv->adjust_hs400_enable)
 231                 return;
 232
 233         if (!priv->needs_adjust_hs400)
 234                 return;
 235
 236         if (!priv->adjust_hs400_calib_table)
 237                 return;
 238
 239         /*
 240          * Enabled Manual adjust HS400 mode
 241          *
 242          * 1) Disabled Write Protect
 243          *    W(addr=0x00, WP_DISABLE_CODE)
 244          *
 245          * 2) Read Calibration code
 246          *    read_value = R(addr=0x26)
 247          * 3) Refer to calibration table
 248          *    Calibration code = table[read_value]
 249          * 4) Enabled Manual Calibration
 250          *    W(addr=0x22, manual mode | Calibration code)
 251          * 5) Set Offset value to TMPPORT3 Reg
 252          */
 253         sd_scc_tmpport_write32(priv, 0x00,
 254                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 255         calib_code = sd_scc_tmpport_read32(priv, 0x26);
 256         calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 257         sd_scc_tmpport_write32(priv, 0x22,
 258                                RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
 259                                priv->adjust_hs400_calib_table[calib_code]);
 260         tmio_sd_writel(priv, priv->adjust_hs400_offset,
 261                        RENESAS_SDHI_SCC_TMPPORT3);
 262
 263         /* Clear flag */
 264         priv->needs_adjust_hs400 = false;
 265 }
 266
 267 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
 268 {
 269
 270         /* Disabled Manual adjust HS400 mode
 271          *
 272          * 1) Disabled Write Protect
 273          *    W(addr=0x00, WP_DISABLE_CODE)
 274          * 2) Disabled Manual Calibration
 275          *    W(addr=0x22, 0)
 276          * 3) Clear offset value to TMPPORT3 Reg
 277          */
 278         sd_scc_tmpport_write32(priv, 0x00,
 279                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 280         sd_scc_tmpport_write32(priv, 0x22, 0);
 281         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
 282 }
 283
 284 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
 285 {
 286         u32 reg;
 287
 288         /* Initialize SCC */
 289         tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
 290
 291         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 292         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 293         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 294
 295         /* Set sampling clock selection range */
 296         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 297                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 298                              RENESAS_SDHI_SCC_DTCNTL);
 299
 300         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 301         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 302         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 303
 304         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 305         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 306         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 307
 308         tmio_sd_writel(priv, 0x300 /* scc_tappos */,
 309                            RENESAS_SDHI_SCC_DT2FF);
 310
 311         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 312         reg |= TMIO_SD_CLKCTL_SCLKEN;
 313         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 314
 315         /* Read TAPNUM */
 316         return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
 317                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 318                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 319 }
 320
 321 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
 322 {
 323         u32 reg;
 324
 325         /* Reset SCC */
 326         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 327         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 328         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 329
 330         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 331         reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
 332         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 333
 334         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 335         reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 336                  RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 337         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 338
 339         /* Disable HS400 mode adjustment */
 340         renesas_sdhi_adjust_hs400_mode_disable(priv);
 341
 342         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 343         reg |= TMIO_SD_CLKCTL_SCLKEN;
 344         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 345
 346         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 347         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 348         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 349
 350         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 351         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 352         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 353 }
 354
 355 static int renesas_sdhi_hs400(struct udevice *dev)
 356 {
 357         struct tmio_sd_priv *priv = dev_get_priv(dev);
 358         struct mmc *mmc = mmc_get_mmc_dev(dev);
 359         bool hs400 = (mmc->selected_mode == MMC_HS_400);
 360         int ret, taps = hs400 ? priv->nrtaps : 8;
 361         const u32 sdn_rate = 200000000;
 362         u32 sdnh_rate = 800000000;
 363         unsigned long new_tap;
 364         u32 reg;
 365
 366         if (clk_valid(&priv->clkh) && !priv->needs_clkh_fallback) {
 367                 /* HS400 on 4tap SoC => SDnH=400 MHz, SDn=200 MHz */
 368                 if (taps == 4)
 369                         sdnh_rate /= 2;
 370                 ret = clk_set_rate(&priv->clkh, sdnh_rate);
 371                 if (ret < 0)
 372                         return ret;
 373         }
 374
 375         ret = clk_set_rate(&priv->clk, sdn_rate);
 376         if (ret < 0)
 377                 return ret;
 378
 379         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 380         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 381         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 382
 383         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 384         if (hs400) {
 385                 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 386                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
 387         } else {
 388                 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 389                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 390         }
 391
 392         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 393
 394         /* Disable HS400 mode adjustment */
 395         if (!hs400)
 396                 renesas_sdhi_adjust_hs400_mode_disable(priv);
 397
 398         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 399                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 400                              RENESAS_SDHI_SCC_DTCNTL);
 401
 402         /* Avoid bad TAP */
 403         if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
 404                 new_tap = (priv->tap_set +
 405                            priv->tap_num + 1) % priv->tap_num;
 406
 407                 if (priv->hs400_bad_tap & BIT(new_tap))
 408                         new_tap = (priv->tap_set +
 409                                    priv->tap_num - 1) % priv->tap_num;
 410
 411                 if (priv->hs400_bad_tap & BIT(new_tap)) {
 412                         new_tap = priv->tap_set;
 413                         debug("Three consecutive bad tap is prohibited\n");
 414                 }
 415
 416                 priv->tap_set = new_tap;
 417                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 418         }
 419
 420         if (taps == 4) {
 421                 tmio_sd_writel(priv, priv->tap_set >> 1,
 422                                RENESAS_SDHI_SCC_TAPSET);
 423                 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
 424                                RENESAS_SDHI_SCC_DT2FF);
 425         } else {
 426                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 427                 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
 428         }
 429
 430         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 431         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 432         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 433
 434         /* Execute adjust hs400 offset after setting to HS400 mode */
 435         if (hs400)
 436                 priv->needs_adjust_hs400 = true;
 437
 438         return 0;
 439 }
 440
 441 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 442                                        unsigned long tap)
 443 {
 444         /* Set sampling clock position */
 445         tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 446 }
 447
 448 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 449 {
 450         /* Get comparison of sampling data */
 451         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 452 }
 453
 454 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 455                                      unsigned int taps)
 456 {
 457         unsigned long tap_cnt;  /* counter of tuning success */
 458         unsigned long tap_start;/* start position of tuning success */
 459         unsigned long tap_end;  /* end position of tuning success */
 460         unsigned long ntap;     /* temporary counter of tuning success */
 461         unsigned long match_cnt;/* counter of matching data */
 462         unsigned long i;
 463         bool select = false;
 464         u32 reg;
 465
 466         priv->needs_adjust_hs400 = false;
 467
 468         /* Clear SCC_RVSREQ */
 469         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 470
 471         /* Merge the results */
 472         for (i = 0; i < priv->tap_num * 2; i++) {
 473                 if (!(taps & BIT(i))) {
 474                         taps &= ~BIT(i % priv->tap_num);
 475                         taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
 476                 }
 477                 if (!(priv->smpcmp & BIT(i))) {
 478                         priv->smpcmp &= ~BIT(i % priv->tap_num);
 479                         priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
 480                 }
 481         }
 482
 483         /*
 484          * Find the longest consecutive run of successful probes.  If that
 485          * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 486          * center index as the tap.
 487          */
 488         tap_cnt = 0;
 489         ntap = 0;
 490         tap_start = 0;
 491         tap_end = 0;
 492         for (i = 0; i < priv->tap_num * 2; i++) {
 493                 if (taps & BIT(i))
 494                         ntap++;
 495                 else {
 496                         if (ntap > tap_cnt) {
 497                                 tap_start = i - ntap;
 498                                 tap_end = i - 1;
 499                                 tap_cnt = ntap;
 500                         }
 501                         ntap = 0;
 502                 }
 503         }
 504
 505         if (ntap > tap_cnt) {
 506                 tap_start = i - ntap;
 507                 tap_end = i - 1;
 508                 tap_cnt = ntap;
 509         }
 510
 511         /*
 512          * If all of the TAP is OK, the sampling clock position is selected by
 513          * identifying the change point of data.
 514          */
 515         if (tap_cnt == priv->tap_num * 2) {
 516                 match_cnt = 0;
 517                 ntap = 0;
 518                 tap_start = 0;
 519                 tap_end = 0;
 520                 for (i = 0; i < priv->tap_num * 2; i++) {
 521                         if (priv->smpcmp & BIT(i))
 522                                 ntap++;
 523                         else {
 524                                 if (ntap > match_cnt) {
 525                                         tap_start = i - ntap;
 526                                         tap_end = i - 1;
 527                                         match_cnt = ntap;
 528                                 }
 529                                 ntap = 0;
 530                         }
 531                 }
 532                 if (ntap > match_cnt) {
 533                         tap_start = i - ntap;
 534                         tap_end = i - 1;
 535                         match_cnt = ntap;
 536                 }
 537                 if (match_cnt)
 538                         select = true;
 539         } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 540                 select = true;
 541
 542         if (select)
 543                 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
 544         else
 545                 return -EIO;
 546
 547         /* Set SCC */
 548         tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 549
 550         /* Enable auto re-tuning */
 551         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 552         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 553         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 554
 555         return 0;
 556 }
 557
 558 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 559 {
 560         struct tmio_sd_priv *priv = dev_get_priv(dev);
 561         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 562         struct mmc *mmc = upriv->mmc;
 563         unsigned int tap_num;
 564         unsigned int taps = 0;
 565         int i, ret = 0;
 566         u32 caps;
 567
 568         /* Only supported on Renesas RCar */
 569         if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 570                 return -EINVAL;
 571
 572         /* clock tuning is not needed for upto 52MHz */
 573         if (!((mmc->selected_mode == MMC_HS_200) ||
 574               (mmc->selected_mode == MMC_HS_400) ||
 575               (mmc->selected_mode == UHS_SDR104) ||
 576               (mmc->selected_mode == UHS_SDR50)))
 577                 return 0;
 578
 579         tap_num = renesas_sdhi_init_tuning(priv);
 580         if (!tap_num)
 581                 /* Tuning is not supported */
 582                 goto out;
 583
 584         priv->tap_num = tap_num;
 585
 586         if (priv->tap_num * 2 >= sizeof(taps) * 8) {
 587                 dev_err(dev,
 588                         "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 589                 goto out;
 590         }
 591
 592         priv->smpcmp = 0;
 593
 594         /* Issue CMD19 twice for each tap */
 595         for (i = 0; i < 2 * priv->tap_num; i++) {
 596                 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
 597
 598                 /* Force PIO for the tuning */
 599                 caps = priv->caps;
 600                 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 601
 602                 ret = mmc_send_tuning(mmc, opcode, NULL);
 603
 604                 priv->caps = caps;
 605
 606                 if (ret == 0)
 607                         taps |= BIT(i);
 608
 609                 ret = renesas_sdhi_compare_scc_data(priv);
 610                 if (ret == 0)
 611                         priv->smpcmp |= BIT(i);
 612
 613                 mdelay(1);
 614
 615                 /*
 616                  * eMMC specification specifies that CMD12 can be used to stop a tuning
 617                  * command, but SD specification does not, so do nothing unless it is
 618                  * eMMC.
 619                  */
 620                 if (ret && (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
 621                         ret = mmc_send_stop_transmission(mmc, false);
 622                         if (ret < 0)
 623                                 dev_dbg(dev, "Tuning abort fail (%d)\n", ret);
 624                 }
 625         }
 626
 627         ret = renesas_sdhi_select_tuning(priv, taps);
 628
 629 out:
 630         if (ret < 0) {
 631                 dev_warn(dev, "Tuning procedure failed\n");
 632                 renesas_sdhi_reset_tuning(priv);
 633         }
 634
 635         return ret;
 636 }
 637 #else
 638 static int renesas_sdhi_hs400(struct udevice *dev)
 639 {
 640         return 0;
 641 }
 642 #endif
 643
 644 static int renesas_sdhi_set_ios(struct udevice *dev)
 645 {
 646         struct tmio_sd_priv *priv = dev_get_priv(dev);
 647         u32 tmp;
 648         int ret;
 649
 650         /* Stop the clock before changing its rate to avoid a glitch signal */
 651         tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 652         tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
 653         tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
 654
 655         ret = renesas_sdhi_hs400(dev);
 656         if (ret)
 657                 return ret;
 658
 659         ret = tmio_sd_set_ios(dev);
 660
 661         mdelay(10);
 662
 663 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 664     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 665     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 666         struct mmc *mmc = mmc_get_mmc_dev(dev);
 667         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 668             (mmc->selected_mode != UHS_SDR104) &&
 669             (mmc->selected_mode != MMC_HS_200) &&
 670             (mmc->selected_mode != MMC_HS_400)) {
 671                 renesas_sdhi_reset_tuning(priv);
 672         }
 673 #endif
 674
 675         return ret;
 676 }
 677
 678 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 679 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
 680                                   int timeout_us)
 681 {
 682         int ret = -ETIMEDOUT;
 683         bool dat0_high;
 684         bool target_dat0_high = !!state;
 685         struct tmio_sd_priv *priv = dev_get_priv(dev);
 686
 687         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 688         while (timeout_us--) {
 689                 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
 690                 if (dat0_high == target_dat0_high) {
 691                         ret = 0;
 692                         break;
 693                 }
 694                 udelay(10);
 695         }
 696
 697         return ret;
 698 }
 699 #endif
 700
 701 #define RENESAS_SDHI_DMA_ALIGNMENT      128
 702
 703 static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
 704                                          size_t len, size_t len_aligned)
 705 {
 706         /* Check if start is aligned */
 707         if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
 708                 debug("Unaligned buffer address %lx\n", ubuf);
 709                 return 0;
 710         }
 711
 712         /* Check if length is aligned */
 713         if (len != len_aligned) {
 714                 debug("Unaligned buffer length %zu\n", len);
 715                 return 0;
 716         }
 717
 718 #ifdef CONFIG_PHYS_64BIT
 719         /* Check if below 32bit boundary */
 720         if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
 721                 debug("Buffer above 32bit boundary %lx-%lx\n",
 722                         ubuf, ubuf + len_aligned);
 723                 return 0;
 724         }
 725 #endif
 726
 727         /* Aligned */
 728         return 1;
 729 }
 730
 731 static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
 732 {
 733         uintptr_t ubuf = (uintptr_t)state->user_buffer;
 734
 735         return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
 736                                              state->len_aligned);
 737 }
 738
 739 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 740                                  struct mmc_data *data)
 741 {
 742         struct bounce_buffer bbstate;
 743         unsigned int bbflags;
 744         bool bbok = false;
 745         size_t len;
 746         void *buf;
 747         int ret;
 748
 749         if (data) {
 750                 if (data->flags & MMC_DATA_READ) {
 751                         buf = data->dest;
 752                         bbflags = GEN_BB_WRITE;
 753                 } else {
 754                         buf = (void *)data->src;
 755                         bbflags = GEN_BB_READ;
 756                 }
 757                 len = data->blocks * data->blocksize;
 758
 759                 ret = bounce_buffer_start_extalign(&bbstate, buf, len, bbflags,
 760                                                    RENESAS_SDHI_DMA_ALIGNMENT,
 761                                                    renesas_sdhi_addr_aligned);
 762                 /*
 763                  * If the amount of data to transfer is too large, we can get
 764                  * -ENOMEM when starting the bounce buffer. If that happens,
 765                  *  fall back to PIO as it was before, otherwise use the BB.
 766                  */
 767                 if (!ret) {
 768                         bbok = true;
 769                         if (data->flags & MMC_DATA_READ)
 770                                 data->dest = bbstate.bounce_buffer;
 771                         else
 772                                 data->src = bbstate.bounce_buffer;
 773                 }
 774         }
 775
 776         ret = tmio_sd_send_cmd(dev, cmd, data);
 777
 778         if (data && bbok) {
 779                 buf = bbstate.user_buffer;
 780
 781                 bounce_buffer_stop(&bbstate);
 782
 783                 if (data->flags & MMC_DATA_READ)
 784                         data->dest = buf;
 785                 else
 786                         data->src = buf;
 787         }
 788
 789         if (ret)
 790                 return ret;
 791
 792 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 793     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 794     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 795         struct tmio_sd_priv *priv = dev_get_priv(dev);
 796
 797         renesas_sdhi_check_scc_error(dev);
 798
 799         if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
 800                 renesas_sdhi_adjust_hs400_mode_enable(priv);
 801 #endif
 802
 803         return 0;
 804 }
 805
 806 int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
 807 {
 808         struct tmio_sd_priv *priv = dev_get_priv(dev);
 809         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 810         struct mmc *mmc = upriv->mmc;
 811         size_t len = blkcnt * mmc->read_bl_len;
 812         size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
 813
 814         if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
 815                 if (priv->quirks & TMIO_SD_CAP_16BIT)
 816                         return U16_MAX;
 817                 else
 818                         return U32_MAX;
 819         } else {
 820                 return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
 821         }
 822 }
 823
 824 static const struct dm_mmc_ops renesas_sdhi_ops = {
 825         .send_cmd = renesas_sdhi_send_cmd,
 826         .set_ios = renesas_sdhi_set_ios,
 827         .get_cd = tmio_sd_get_cd,
 828 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 829     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 830     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 831         .execute_tuning = renesas_sdhi_execute_tuning,
 832 #endif
 833 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 834         .wait_dat0 = renesas_sdhi_wait_dat0,
 835 #endif
 836         .get_b_max = renesas_sdhi_get_b_max,
 837 };
 838
 839 #define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 840 #define RENESAS_GEN3_QUIRKS                             \
 841         TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 842
 843 static const struct udevice_id renesas_sdhi_match[] = {
 844         { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 845         { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 846         { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 847         { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 848         { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 849         { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 850         { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 851         { .compatible = "renesas,sdhi-r8a77961", .data = RENESAS_GEN3_QUIRKS },
 852         { .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS },
 853         { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 854         { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 855         { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 856         { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 857         { .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
 858         { /* sentinel */ }
 859 };
 860
 861 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 862 {
 863         return clk_get_rate(&priv->clk);
 864 }
 865
 866 static void renesas_sdhi_filter_caps(struct udevice *dev)
 867 {
 868         struct tmio_sd_priv *priv = dev_get_priv(dev);
 869
 870         if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
 871                 return;
 872
 873         if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL)
 874                 priv->idma_bus_width = TMIO_SD_DMA_MODE_BUS_WIDTH;
 875
 876 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 877     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 878     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 879         struct tmio_sd_plat *plat = dev_get_plat(dev);
 880
 881         /* HS400 is not supported on H3 ES1.x, M3W ES1.[012], V3M, V3H ES1.x, D3 */
 882         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 883             (rmobile_get_cpu_rev_integer() <= 1)) ||
 884             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 885             (rmobile_get_cpu_rev_integer() == 1) &&
 886             (rmobile_get_cpu_rev_fraction() <= 2)) ||
 887             (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) ||
 888             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) &&
 889             (rmobile_get_cpu_rev_integer() <= 1)) ||
 890             (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
 891                 plat->cfg.host_caps &= ~MMC_MODE_HS400;
 892
 893         /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
 894         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 895             (rmobile_get_cpu_rev_integer() >= 2)) ||
 896             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 897             (rmobile_get_cpu_rev_integer() == 1) &&
 898             (rmobile_get_cpu_rev_fraction() == 2)) ||
 899             (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
 900                 priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
 901
 902         /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
 903         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 904             (rmobile_get_cpu_rev_integer() == 1) &&
 905             (rmobile_get_cpu_rev_fraction() > 2)) {
 906                 priv->adjust_hs400_enable = true;
 907                 priv->adjust_hs400_offset = 3;
 908                 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
 909                 priv->adjust_hs400_calib_table =
 910                         r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)];
 911         }
 912
 913         /* M3W+ bad taps */
 914         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 915             (rmobile_get_cpu_rev_integer() == 3))
 916                 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
 917
 918         /* M3N can use HS400 with manual adjustment */
 919         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
 920                 priv->adjust_hs400_enable = true;
 921                 priv->adjust_hs400_offset = 3;
 922                 priv->adjust_hs400_calib_table =
 923                         r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
 924         }
 925
 926         /* E3 can use HS400 with manual adjustment */
 927         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
 928                 priv->adjust_hs400_enable = true;
 929                 priv->adjust_hs400_offset = 3;
 930                 priv->adjust_hs400_calib_table =
 931                         r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
 932         }
 933
 934         /* H3 ES1.x, ES2.0 and M3W ES1.[0123] uses 4 tuning taps */
 935         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 936             (rmobile_get_cpu_rev_integer() <= 2)) ||
 937             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 938             (rmobile_get_cpu_rev_integer() == 1) &&
 939             (rmobile_get_cpu_rev_fraction() <= 3)))
 940                 priv->nrtaps = 4;
 941         else
 942                 priv->nrtaps = 8;
 943 #endif
 944         /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
 945         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 946             (rmobile_get_cpu_rev_integer() <= 1)) ||
 947             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 948             (rmobile_get_cpu_rev_integer() == 1) &&
 949             (rmobile_get_cpu_rev_fraction() == 0)))
 950                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
 951         else
 952                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
 953
 954         /* V3M handles SD0H differently than other Gen3 SoCs */
 955         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970)
 956                 priv->needs_clkh_fallback = true;
 957         else
 958                 priv->needs_clkh_fallback = false;
 959 }
 960
 961 static int renesas_sdhi_probe(struct udevice *dev)
 962 {
 963         struct tmio_sd_priv *priv = dev_get_priv(dev);
 964         u32 quirks = dev_get_driver_data(dev);
 965         struct fdt_resource reg_res;
 966         DECLARE_GLOBAL_DATA_PTR;
 967         int ret;
 968
 969         priv->clk_get_rate = renesas_sdhi_clk_get_rate;
 970
 971         if (quirks == RENESAS_GEN2_QUIRKS) {
 972                 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 973                                        "reg", 0, &reg_res);
 974                 if (ret < 0) {
 975                         dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 976                                 ret);
 977                         return ret;
 978                 }
 979
 980                 if (fdt_resource_size(&reg_res) == 0x100)
 981                         quirks |= TMIO_SD_CAP_16BIT;
 982         }
 983
 984         ret = clk_get_by_index(dev, 0, &priv->clk);
 985         if (ret < 0) {
 986                 dev_err(dev, "failed to get host clock\n");
 987                 return ret;
 988         }
 989
 990         /* optional SDnH clock */
 991         ret = clk_get_by_name(dev, "clkh", &priv->clkh);
 992         if (ret < 0) {
 993                 dev_dbg(dev, "failed to get clkh\n");
 994         } else {
 995                 ret = clk_set_rate(&priv->clkh, 800000000);
 996                 if (ret < 0) {
 997                         dev_err(dev, "failed to set rate for SDnH clock (%d)\n", ret);
 998                         goto err_clk;
 999                 }
1000         }
1001
1002         /* set to max rate */
1003         ret = clk_set_rate(&priv->clk, 200000000);
1004         if (ret < 0) {
1005                 dev_err(dev, "failed to set rate for SDn clock (%d)\n", ret);
1006                 goto err_clkh;
1007         }
1008
1009         ret = clk_enable(&priv->clk);
1010         if (ret) {
1011                 dev_err(dev, "failed to enable SDn clock (%d)\n", ret);
1012                 goto err_clkh;
1013         }
1014
1015         priv->quirks = quirks;
1016         ret = tmio_sd_probe(dev, quirks);
1017         if (ret)
1018                 goto err_tmio_probe;
1019
1020         renesas_sdhi_filter_caps(dev);
1021
1022 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
1023     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
1024     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1025         if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
1026                 renesas_sdhi_reset_tuning(priv);
1027 #endif
1028         return 0;
1029
1030 err_tmio_probe:
1031         clk_disable(&priv->clk);
1032 err_clkh:
1033         clk_free(&priv->clkh);
1034 err_clk:
1035         clk_free(&priv->clk);
1036         return ret;
1037 }
1038
1039 U_BOOT_DRIVER(renesas_sdhi) = {
1040         .name = "renesas-sdhi",
1041         .id = UCLASS_MMC,
1042         .of_match = renesas_sdhi_match,
1043         .bind = tmio_sd_bind,
1044         .probe = renesas_sdhi_probe,
1045         .priv_auto      = sizeof(struct tmio_sd_priv),
1046         .plat_auto      = sizeof(struct tmio_sd_plat),
1047         .ops = &renesas_sdhi_ops,
1048 };