1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
14 #include <asm/global_data.h>
15 #include <dm/device_compat.h>
16 #include <linux/bitops.h>
17 #include <linux/compat.h>
18 #include <linux/delay.h>
19 #include <linux/dma-direction.h>
21 #include <linux/sizes.h>
22 #include <power/regulator.h>
23 #include <asm/unaligned.h>
24 #include "tmio-common.h"
26 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
27 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
28 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
31 #define RENESAS_SDHI_SCC_DTCNTL 0x800
32 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
33 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
34 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
35 #define RENESAS_SDHI_SCC_TAPSET 0x804
36 #define RENESAS_SDHI_SCC_DT2FF 0x808
37 #define RENESAS_SDHI_SCC_CKSEL 0x80c
38 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
39 #define RENESAS_SDHI_SCC_RVSCNTL 0x810
40 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
41 #define RENESAS_SDHI_SCC_RVSREQ 0x814
42 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
43 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
44 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
45 #define RENESAS_SDHI_SCC_SMPCMP 0x818
46 #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8))
47 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
48 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
49 #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
50 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
51 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
52 #define RENESAS_SDHI_SCC_TMPPORT3 0x828
53 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
54 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
55 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
56 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
57 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
58 #define RENESAS_SDHI_SCC_TMPPORT4 0x82c
59 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
60 #define RENESAS_SDHI_SCC_TMPPORT5 0x830
61 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
62 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
63 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
64 #define RENESAS_SDHI_SCC_TMPPORT6 0x834
65 #define RENESAS_SDHI_SCC_TMPPORT7 0x838
66 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
67 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
68 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
70 #define RENESAS_SDHI_MAX_TAP 3
72 #define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
74 static const u8 r8a7796_rev13_calib_table[2][CALIB_TABLE_MAX] = {
75 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
76 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
77 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
78 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
81 static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
82 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
83 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
84 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
85 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
88 static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
89 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
90 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
91 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
92 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
95 static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
97 /* On R-Car Gen3, MMC0 is at 0xee140000 */
98 return (uintptr_t)(priv->regbase) == 0xee140000;
101 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
104 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
105 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
106 RENESAS_SDHI_SCC_TMPPORT5);
108 /* access start and stop */
109 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
110 RENESAS_SDHI_SCC_TMPPORT4);
111 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
113 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
116 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
119 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
120 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
121 RENESAS_SDHI_SCC_TMPPORT5);
122 tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
124 /* access start and stop */
125 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
126 RENESAS_SDHI_SCC_TMPPORT4);
127 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
130 static bool renesas_sdhi_check_scc_error(struct udevice *dev)
132 struct tmio_sd_priv *priv = dev_get_priv(dev);
133 struct mmc *mmc = mmc_get_mmc_dev(dev);
134 unsigned long new_tap = priv->tap_set;
135 unsigned long error_tap = priv->tap_set;
138 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
139 (mmc->selected_mode != UHS_SDR104) &&
140 (mmc->selected_mode != MMC_HS_200) &&
141 (mmc->selected_mode != MMC_HS_400) &&
145 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
146 /* Handle automatic tuning correction */
147 if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
148 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
149 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
150 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
157 /* Handle manual tuning correction */
158 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
159 if (!reg) /* No error */
162 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
164 if (mmc->selected_mode == MMC_HS_400) {
166 * Correction Error Status contains CMD and DAT signal status.
167 * In HS400, DAT signal based on DS signal, not CLK.
168 * Therefore, use only CMD status.
170 smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
171 RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
175 return false; /* No error in CMD signal */
176 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
177 new_tap = (priv->tap_set +
178 priv->tap_num + 1) % priv->tap_num;
179 error_tap = (priv->tap_set +
180 priv->tap_num - 1) % priv->tap_num;
182 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
183 new_tap = (priv->tap_set +
184 priv->tap_num - 1) % priv->tap_num;
185 error_tap = (priv->tap_set +
186 priv->tap_num + 1) % priv->tap_num;
189 return true; /* Need re-tune */
192 if (priv->hs400_bad_tap & BIT(new_tap)) {
194 * New tap is bad tap (cannot change).
195 * Compare with HS200 tuning result.
196 * In HS200 tuning, when smpcmp[error_tap]
197 * is OK, retune is executed.
199 if (priv->smpcmp & BIT(error_tap))
200 return true; /* Need retune */
202 return false; /* cannot change */
205 priv->tap_set = new_tap;
207 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
208 return true; /* Need re-tune */
209 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
210 priv->tap_set = (priv->tap_set +
211 priv->tap_num + 1) % priv->tap_num;
212 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
213 priv->tap_set = (priv->tap_set +
214 priv->tap_num - 1) % priv->tap_num;
219 /* Set TAP position */
220 tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
221 RENESAS_SDHI_SCC_TAPSET);
226 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
230 if (!priv->adjust_hs400_enable)
233 if (!priv->needs_adjust_hs400)
236 if (!priv->adjust_hs400_calib_table)
240 * Enabled Manual adjust HS400 mode
242 * 1) Disabled Write Protect
243 * W(addr=0x00, WP_DISABLE_CODE)
245 * 2) Read Calibration code
246 * read_value = R(addr=0x26)
247 * 3) Refer to calibration table
248 * Calibration code = table[read_value]
249 * 4) Enabled Manual Calibration
250 * W(addr=0x22, manual mode | Calibration code)
251 * 5) Set Offset value to TMPPORT3 Reg
253 sd_scc_tmpport_write32(priv, 0x00,
254 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
255 calib_code = sd_scc_tmpport_read32(priv, 0x26);
256 calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
257 sd_scc_tmpport_write32(priv, 0x22,
258 RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
259 priv->adjust_hs400_calib_table[calib_code]);
260 tmio_sd_writel(priv, priv->adjust_hs400_offset,
261 RENESAS_SDHI_SCC_TMPPORT3);
264 priv->needs_adjust_hs400 = false;
267 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
270 /* Disabled Manual adjust HS400 mode
272 * 1) Disabled Write Protect
273 * W(addr=0x00, WP_DISABLE_CODE)
274 * 2) Disabled Manual Calibration
276 * 3) Clear offset value to TMPPORT3 Reg
278 sd_scc_tmpport_write32(priv, 0x00,
279 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
280 sd_scc_tmpport_write32(priv, 0x22, 0);
281 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
284 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
289 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
291 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
292 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
293 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
295 /* Set sampling clock selection range */
296 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
297 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
298 RENESAS_SDHI_SCC_DTCNTL);
300 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
301 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
302 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
304 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
305 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
306 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
308 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
309 RENESAS_SDHI_SCC_DT2FF);
311 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
312 reg |= TMIO_SD_CLKCTL_SCLKEN;
313 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
316 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
317 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
318 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
321 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
326 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
327 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
328 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
330 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
331 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
332 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
334 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
335 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
336 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
337 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
339 /* Disable HS400 mode adjustment */
340 renesas_sdhi_adjust_hs400_mode_disable(priv);
342 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
343 reg |= TMIO_SD_CLKCTL_SCLKEN;
344 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
346 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
347 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
348 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
350 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
351 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
352 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
355 static int renesas_sdhi_hs400(struct udevice *dev)
357 struct tmio_sd_priv *priv = dev_get_priv(dev);
358 struct mmc *mmc = mmc_get_mmc_dev(dev);
359 bool hs400 = (mmc->selected_mode == MMC_HS_400);
360 int ret, taps = hs400 ? priv->nrtaps : 8;
361 const u32 sdn_rate = 200000000;
362 u32 sdnh_rate = 800000000;
363 unsigned long new_tap;
366 if (clk_valid(&priv->clkh) && !priv->needs_clkh_fallback) {
367 /* HS400 on 4tap SoC => SDnH=400 MHz, SDn=200 MHz */
370 ret = clk_set_rate(&priv->clkh, sdnh_rate);
375 ret = clk_set_rate(&priv->clk, sdn_rate);
379 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
380 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
381 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
383 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
385 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
386 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
388 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
389 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
392 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
394 /* Disable HS400 mode adjustment */
396 renesas_sdhi_adjust_hs400_mode_disable(priv);
398 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
399 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
400 RENESAS_SDHI_SCC_DTCNTL);
403 if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
404 new_tap = (priv->tap_set +
405 priv->tap_num + 1) % priv->tap_num;
407 if (priv->hs400_bad_tap & BIT(new_tap))
408 new_tap = (priv->tap_set +
409 priv->tap_num - 1) % priv->tap_num;
411 if (priv->hs400_bad_tap & BIT(new_tap)) {
412 new_tap = priv->tap_set;
413 debug("Three consecutive bad tap is prohibited\n");
416 priv->tap_set = new_tap;
417 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
421 tmio_sd_writel(priv, priv->tap_set >> 1,
422 RENESAS_SDHI_SCC_TAPSET);
423 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
424 RENESAS_SDHI_SCC_DT2FF);
426 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
427 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
430 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
431 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
432 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
434 /* Execute adjust hs400 offset after setting to HS400 mode */
436 priv->needs_adjust_hs400 = true;
441 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
444 /* Set sampling clock position */
445 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
448 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
450 /* Get comparison of sampling data */
451 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
454 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
457 unsigned long tap_cnt; /* counter of tuning success */
458 unsigned long tap_start;/* start position of tuning success */
459 unsigned long tap_end; /* end position of tuning success */
460 unsigned long ntap; /* temporary counter of tuning success */
461 unsigned long match_cnt;/* counter of matching data */
466 priv->needs_adjust_hs400 = false;
468 /* Clear SCC_RVSREQ */
469 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
471 /* Merge the results */
472 for (i = 0; i < priv->tap_num * 2; i++) {
473 if (!(taps & BIT(i))) {
474 taps &= ~BIT(i % priv->tap_num);
475 taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
477 if (!(priv->smpcmp & BIT(i))) {
478 priv->smpcmp &= ~BIT(i % priv->tap_num);
479 priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
484 * Find the longest consecutive run of successful probes. If that
485 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
486 * center index as the tap.
492 for (i = 0; i < priv->tap_num * 2; i++) {
496 if (ntap > tap_cnt) {
497 tap_start = i - ntap;
505 if (ntap > tap_cnt) {
506 tap_start = i - ntap;
512 * If all of the TAP is OK, the sampling clock position is selected by
513 * identifying the change point of data.
515 if (tap_cnt == priv->tap_num * 2) {
520 for (i = 0; i < priv->tap_num * 2; i++) {
521 if (priv->smpcmp & BIT(i))
524 if (ntap > match_cnt) {
525 tap_start = i - ntap;
532 if (ntap > match_cnt) {
533 tap_start = i - ntap;
539 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
543 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
548 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
550 /* Enable auto re-tuning */
551 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
552 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
553 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
558 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
560 struct tmio_sd_priv *priv = dev_get_priv(dev);
561 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
562 struct mmc *mmc = upriv->mmc;
563 unsigned int tap_num;
564 unsigned int taps = 0;
568 /* Only supported on Renesas RCar */
569 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
572 /* clock tuning is not needed for upto 52MHz */
573 if (!((mmc->selected_mode == MMC_HS_200) ||
574 (mmc->selected_mode == MMC_HS_400) ||
575 (mmc->selected_mode == UHS_SDR104) ||
576 (mmc->selected_mode == UHS_SDR50)))
579 tap_num = renesas_sdhi_init_tuning(priv);
581 /* Tuning is not supported */
584 priv->tap_num = tap_num;
586 if (priv->tap_num * 2 >= sizeof(taps) * 8) {
588 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
594 /* Issue CMD19 twice for each tap */
595 for (i = 0; i < 2 * priv->tap_num; i++) {
596 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
598 /* Force PIO for the tuning */
600 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
602 ret = mmc_send_tuning(mmc, opcode, NULL);
609 ret = renesas_sdhi_compare_scc_data(priv);
611 priv->smpcmp |= BIT(i);
616 * eMMC specification specifies that CMD12 can be used to stop a tuning
617 * command, but SD specification does not, so do nothing unless it is
620 if (ret && (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
621 ret = mmc_send_stop_transmission(mmc, false);
623 dev_dbg(dev, "Tuning abort fail (%d)\n", ret);
627 ret = renesas_sdhi_select_tuning(priv, taps);
631 dev_warn(dev, "Tuning procedure failed\n");
632 renesas_sdhi_reset_tuning(priv);
638 static int renesas_sdhi_hs400(struct udevice *dev)
644 static int renesas_sdhi_set_ios(struct udevice *dev)
646 struct tmio_sd_priv *priv = dev_get_priv(dev);
650 /* Stop the clock before changing its rate to avoid a glitch signal */
651 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
652 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
653 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
655 ret = renesas_sdhi_hs400(dev);
659 ret = tmio_sd_set_ios(dev);
663 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
664 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
665 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
666 struct mmc *mmc = mmc_get_mmc_dev(dev);
667 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
668 (mmc->selected_mode != UHS_SDR104) &&
669 (mmc->selected_mode != MMC_HS_200) &&
670 (mmc->selected_mode != MMC_HS_400)) {
671 renesas_sdhi_reset_tuning(priv);
678 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
679 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
682 int ret = -ETIMEDOUT;
684 bool target_dat0_high = !!state;
685 struct tmio_sd_priv *priv = dev_get_priv(dev);
687 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
688 while (timeout_us--) {
689 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
690 if (dat0_high == target_dat0_high) {
701 #define RENESAS_SDHI_DMA_ALIGNMENT 128
703 static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
704 size_t len, size_t len_aligned)
706 /* Check if start is aligned */
707 if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
708 debug("Unaligned buffer address %lx\n", ubuf);
712 /* Check if length is aligned */
713 if (len != len_aligned) {
714 debug("Unaligned buffer length %zu\n", len);
718 #ifdef CONFIG_PHYS_64BIT
719 /* Check if below 32bit boundary */
720 if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
721 debug("Buffer above 32bit boundary %lx-%lx\n",
722 ubuf, ubuf + len_aligned);
731 static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
733 uintptr_t ubuf = (uintptr_t)state->user_buffer;
735 return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
739 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
740 struct mmc_data *data)
742 struct bounce_buffer bbstate;
743 unsigned int bbflags;
750 if (data->flags & MMC_DATA_READ) {
752 bbflags = GEN_BB_WRITE;
754 buf = (void *)data->src;
755 bbflags = GEN_BB_READ;
757 len = data->blocks * data->blocksize;
759 ret = bounce_buffer_start_extalign(&bbstate, buf, len, bbflags,
760 RENESAS_SDHI_DMA_ALIGNMENT,
761 renesas_sdhi_addr_aligned);
763 * If the amount of data to transfer is too large, we can get
764 * -ENOMEM when starting the bounce buffer. If that happens,
765 * fall back to PIO as it was before, otherwise use the BB.
769 if (data->flags & MMC_DATA_READ)
770 data->dest = bbstate.bounce_buffer;
772 data->src = bbstate.bounce_buffer;
776 ret = tmio_sd_send_cmd(dev, cmd, data);
779 buf = bbstate.user_buffer;
781 bounce_buffer_stop(&bbstate);
783 if (data->flags & MMC_DATA_READ)
792 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
793 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
794 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
795 struct tmio_sd_priv *priv = dev_get_priv(dev);
797 renesas_sdhi_check_scc_error(dev);
799 if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
800 renesas_sdhi_adjust_hs400_mode_enable(priv);
806 int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
808 struct tmio_sd_priv *priv = dev_get_priv(dev);
809 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
810 struct mmc *mmc = upriv->mmc;
811 size_t len = blkcnt * mmc->read_bl_len;
812 size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
814 if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
815 if (priv->quirks & TMIO_SD_CAP_16BIT)
820 return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
824 static const struct dm_mmc_ops renesas_sdhi_ops = {
825 .send_cmd = renesas_sdhi_send_cmd,
826 .set_ios = renesas_sdhi_set_ios,
827 .get_cd = tmio_sd_get_cd,
828 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
829 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
830 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
831 .execute_tuning = renesas_sdhi_execute_tuning,
833 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
834 .wait_dat0 = renesas_sdhi_wait_dat0,
836 .get_b_max = renesas_sdhi_get_b_max,
839 #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
840 #define RENESAS_GEN3_QUIRKS \
841 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
843 static const struct udevice_id renesas_sdhi_match[] = {
844 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
845 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
846 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
847 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
848 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
849 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
850 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
851 { .compatible = "renesas,sdhi-r8a77961", .data = RENESAS_GEN3_QUIRKS },
852 { .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS },
853 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
854 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
855 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
856 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
857 { .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
861 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
863 return clk_get_rate(&priv->clk);
866 static void renesas_sdhi_filter_caps(struct udevice *dev)
868 struct tmio_sd_priv *priv = dev_get_priv(dev);
870 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
873 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL)
874 priv->idma_bus_width = TMIO_SD_DMA_MODE_BUS_WIDTH;
876 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
877 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
878 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
879 struct tmio_sd_plat *plat = dev_get_plat(dev);
881 /* HS400 is not supported on H3 ES1.x, M3W ES1.[012], V3M, V3H ES1.x, D3 */
882 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
883 (rmobile_get_cpu_rev_integer() <= 1)) ||
884 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
885 (rmobile_get_cpu_rev_integer() == 1) &&
886 (rmobile_get_cpu_rev_fraction() <= 2)) ||
887 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) ||
888 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) &&
889 (rmobile_get_cpu_rev_integer() <= 1)) ||
890 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
891 plat->cfg.host_caps &= ~MMC_MODE_HS400;
893 /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
894 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
895 (rmobile_get_cpu_rev_integer() >= 2)) ||
896 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
897 (rmobile_get_cpu_rev_integer() == 1) &&
898 (rmobile_get_cpu_rev_fraction() == 2)) ||
899 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
900 priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
902 /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
903 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
904 (rmobile_get_cpu_rev_integer() == 1) &&
905 (rmobile_get_cpu_rev_fraction() > 2)) {
906 priv->adjust_hs400_enable = true;
907 priv->adjust_hs400_offset = 3;
908 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
909 priv->adjust_hs400_calib_table =
910 r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)];
914 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
915 (rmobile_get_cpu_rev_integer() == 3))
916 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
918 /* M3N can use HS400 with manual adjustment */
919 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
920 priv->adjust_hs400_enable = true;
921 priv->adjust_hs400_offset = 3;
922 priv->adjust_hs400_calib_table =
923 r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
926 /* E3 can use HS400 with manual adjustment */
927 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
928 priv->adjust_hs400_enable = true;
929 priv->adjust_hs400_offset = 3;
930 priv->adjust_hs400_calib_table =
931 r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
934 /* H3 ES1.x, ES2.0 and M3W ES1.[0123] uses 4 tuning taps */
935 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
936 (rmobile_get_cpu_rev_integer() <= 2)) ||
937 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
938 (rmobile_get_cpu_rev_integer() == 1) &&
939 (rmobile_get_cpu_rev_fraction() <= 3)))
944 /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
945 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
946 (rmobile_get_cpu_rev_integer() <= 1)) ||
947 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
948 (rmobile_get_cpu_rev_integer() == 1) &&
949 (rmobile_get_cpu_rev_fraction() == 0)))
950 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
952 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
954 /* V3M handles SD0H differently than other Gen3 SoCs */
955 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970)
956 priv->needs_clkh_fallback = true;
958 priv->needs_clkh_fallback = false;
961 static int renesas_sdhi_probe(struct udevice *dev)
963 struct tmio_sd_priv *priv = dev_get_priv(dev);
964 u32 quirks = dev_get_driver_data(dev);
965 struct fdt_resource reg_res;
966 DECLARE_GLOBAL_DATA_PTR;
969 priv->clk_get_rate = renesas_sdhi_clk_get_rate;
971 if (quirks == RENESAS_GEN2_QUIRKS) {
972 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
975 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
980 if (fdt_resource_size(®_res) == 0x100)
981 quirks |= TMIO_SD_CAP_16BIT;
984 ret = clk_get_by_index(dev, 0, &priv->clk);
986 dev_err(dev, "failed to get host clock\n");
990 /* optional SDnH clock */
991 ret = clk_get_by_name(dev, "clkh", &priv->clkh);
993 dev_dbg(dev, "failed to get clkh\n");
995 ret = clk_set_rate(&priv->clkh, 800000000);
997 dev_err(dev, "failed to set rate for SDnH clock (%d)\n", ret);
1002 /* set to max rate */
1003 ret = clk_set_rate(&priv->clk, 200000000);
1005 dev_err(dev, "failed to set rate for SDn clock (%d)\n", ret);
1009 ret = clk_enable(&priv->clk);
1011 dev_err(dev, "failed to enable SDn clock (%d)\n", ret);
1015 priv->quirks = quirks;
1016 ret = tmio_sd_probe(dev, quirks);
1018 goto err_tmio_probe;
1020 renesas_sdhi_filter_caps(dev);
1022 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
1023 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
1024 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1025 if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
1026 renesas_sdhi_reset_tuning(priv);
1031 clk_disable(&priv->clk);
1033 clk_free(&priv->clkh);
1035 clk_free(&priv->clk);
1039 U_BOOT_DRIVER(renesas_sdhi) = {
1040 .name = "renesas-sdhi",
1042 .of_match = renesas_sdhi_match,
1043 .bind = tmio_sd_bind,
1044 .probe = renesas_sdhi_probe,
1045 .priv_auto = sizeof(struct tmio_sd_priv),
1046 .plat_auto = sizeof(struct tmio_sd_plat),
1047 .ops = &renesas_sdhi_ops,