1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
11 #include <linux/compat.h>
12 #include <linux/dma-direction.h>
14 #include <linux/sizes.h>
15 #include <power/regulator.h>
16 #include <asm/unaligned.h>
18 #include "tmio-common.h"
20 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
23 #define RENESAS_SDHI_SCC_DTCNTL 0x800
24 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
25 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
26 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
27 #define RENESAS_SDHI_SCC_TAPSET 0x804
28 #define RENESAS_SDHI_SCC_DT2FF 0x808
29 #define RENESAS_SDHI_SCC_CKSEL 0x80c
30 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
31 #define RENESAS_SDHI_SCC_RVSCNTL 0x810
32 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
33 #define RENESAS_SDHI_SCC_RVSREQ 0x814
34 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
35 #define RENESAS_SDHI_SCC_SMPCMP 0x818
36 #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
37 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
38 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
40 #define RENESAS_SDHI_MAX_TAP 3
42 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
47 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
49 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
50 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
51 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
53 /* Set sampling clock selection range */
54 tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
55 RENESAS_SDHI_SCC_DTCNTL);
57 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
58 reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
59 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
61 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
62 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
63 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
65 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
66 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
67 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
69 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
70 RENESAS_SDHI_SCC_DT2FF);
72 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
73 reg |= TMIO_SD_CLKCTL_SCLKEN;
74 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
77 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
78 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
79 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
82 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
87 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
88 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
89 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
91 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
92 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
93 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
95 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
96 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
97 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
98 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
100 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
101 reg |= TMIO_SD_CLKCTL_SCLKEN;
102 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
104 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
105 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
106 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
108 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
109 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
110 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
113 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
116 /* Set sampling clock position */
117 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
120 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
122 /* Get comparison of sampling data */
123 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
126 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
127 unsigned int tap_num, unsigned int taps,
130 unsigned long tap_cnt; /* counter of tuning success */
131 unsigned long tap_set; /* tap position */
132 unsigned long tap_start;/* start position of tuning success */
133 unsigned long tap_end; /* end position of tuning success */
134 unsigned long ntap; /* temporary counter of tuning success */
135 unsigned long match_cnt;/* counter of matching data */
140 /* Clear SCC_RVSREQ */
141 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
143 /* Merge the results */
144 for (i = 0; i < tap_num * 2; i++) {
145 if (!(taps & BIT(i))) {
146 taps &= ~BIT(i % tap_num);
147 taps &= ~BIT((i % tap_num) + tap_num);
149 if (!(smpcmp & BIT(i))) {
150 smpcmp &= ~BIT(i % tap_num);
151 smpcmp &= ~BIT((i % tap_num) + tap_num);
156 * Find the longest consecutive run of successful probes. If that
157 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
158 * center index as the tap.
164 for (i = 0; i < tap_num * 2; i++) {
168 if (ntap > tap_cnt) {
169 tap_start = i - ntap;
177 if (ntap > tap_cnt) {
178 tap_start = i - ntap;
184 * If all of the TAP is OK, the sampling clock position is selected by
185 * identifying the change point of data.
187 if (tap_cnt == tap_num * 2) {
192 for (i = 0; i < tap_num * 2; i++) {
196 if (ntap > match_cnt) {
197 tap_start = i - ntap;
204 if (ntap > match_cnt) {
205 tap_start = i - ntap;
211 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
215 tap_set = ((tap_start + tap_end) / 2) % tap_num;
220 tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
222 /* Enable auto re-tuning */
223 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
224 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
225 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
230 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
232 struct tmio_sd_priv *priv = dev_get_priv(dev);
233 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
234 struct mmc *mmc = upriv->mmc;
235 unsigned int tap_num;
236 unsigned int taps = 0, smpcmp = 0;
240 /* Only supported on Renesas RCar */
241 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
244 /* clock tuning is not needed for upto 52MHz */
245 if (!((mmc->selected_mode == MMC_HS_200) ||
246 (mmc->selected_mode == UHS_SDR104) ||
247 (mmc->selected_mode == UHS_SDR50)))
250 tap_num = renesas_sdhi_init_tuning(priv);
252 /* Tuning is not supported */
255 if (tap_num * 2 >= sizeof(taps) * 8) {
257 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
261 /* Issue CMD19 twice for each tap */
262 for (i = 0; i < 2 * tap_num; i++) {
263 renesas_sdhi_prepare_tuning(priv, i % tap_num);
265 /* Force PIO for the tuning */
267 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
269 ret = mmc_send_tuning(mmc, opcode, NULL);
276 ret = renesas_sdhi_compare_scc_data(priv);
283 ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
287 dev_warn(dev, "Tuning procedure failed\n");
288 renesas_sdhi_reset_tuning(priv);
295 static int renesas_sdhi_set_ios(struct udevice *dev)
297 int ret = tmio_sd_set_ios(dev);
301 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
302 struct tmio_sd_priv *priv = dev_get_priv(dev);
304 if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
305 renesas_sdhi_reset_tuning(priv);
311 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
312 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
314 int ret = -ETIMEDOUT;
316 bool target_dat0_high = !!state;
317 struct tmio_sd_priv *priv = dev_get_priv(dev);
319 timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
321 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
322 if (dat0_high == target_dat0_high) {
333 static const struct dm_mmc_ops renesas_sdhi_ops = {
334 .send_cmd = tmio_sd_send_cmd,
335 .set_ios = renesas_sdhi_set_ios,
336 .get_cd = tmio_sd_get_cd,
337 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
338 .execute_tuning = renesas_sdhi_execute_tuning,
340 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
341 .wait_dat0 = renesas_sdhi_wait_dat0,
345 #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
346 #define RENESAS_GEN3_QUIRKS \
347 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
349 static const struct udevice_id renesas_sdhi_match[] = {
350 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
351 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
352 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
353 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
354 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
355 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
356 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
357 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
358 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
359 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
360 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
364 static int renesas_sdhi_probe(struct udevice *dev)
366 struct tmio_sd_priv *priv = dev_get_priv(dev);
367 u32 quirks = dev_get_driver_data(dev);
368 struct fdt_resource reg_res;
370 DECLARE_GLOBAL_DATA_PTR;
373 if (quirks == RENESAS_GEN2_QUIRKS) {
374 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
377 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
382 if (fdt_resource_size(®_res) == 0x100)
383 quirks |= TMIO_SD_CAP_16BIT;
386 ret = clk_get_by_index(dev, 0, &clk);
388 dev_err(dev, "failed to get host clock\n");
392 /* set to max rate */
393 priv->mclk = clk_set_rate(&clk, ULONG_MAX);
394 if (IS_ERR_VALUE(priv->mclk)) {
395 dev_err(dev, "failed to set rate for host clock\n");
400 ret = clk_enable(&clk);
403 dev_err(dev, "failed to enable host clock\n");
407 ret = tmio_sd_probe(dev, quirks);
408 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
409 if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
410 renesas_sdhi_reset_tuning(priv);
415 U_BOOT_DRIVER(renesas_sdhi) = {
416 .name = "renesas-sdhi",
418 .of_match = renesas_sdhi_match,
419 .bind = tmio_sd_bind,
420 .probe = renesas_sdhi_probe,
421 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
422 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
423 .ops = &renesas_sdhi_ops,