1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
5 * Driver for SD/MMC controller present on Actions Semi S700/S900 SoC, based
6 * on Linux Driver "drivers/mmc/host/owl-mmc.c".
8 * Though, there is a bit (BSEL, BUS or DMA Special Channel Selection) that
9 * controls the data transfer from SDx_DAT register either using CPU AHB Bus
10 * or DMA channel, but seems like, it only works correctly using external DMA
11 * channel, and those special bits used in this driver is picked from vendor
12 * source exclusively for MMC/SD.
22 #include <linux/bitops.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/iopoll.h>
30 #define OWL_REG_SD_EN 0x0000
31 #define OWL_REG_SD_CTL 0x0004
32 #define OWL_REG_SD_STATE 0x0008
33 #define OWL_REG_SD_CMD 0x000c
34 #define OWL_REG_SD_ARG 0x0010
35 #define OWL_REG_SD_RSPBUF0 0x0014
36 #define OWL_REG_SD_RSPBUF1 0x0018
37 #define OWL_REG_SD_RSPBUF2 0x001c
38 #define OWL_REG_SD_RSPBUF3 0x0020
39 #define OWL_REG_SD_RSPBUF4 0x0024
40 #define OWL_REG_SD_DAT 0x0028
41 #define OWL_REG_SD_BLK_SIZE 0x002c
42 #define OWL_REG_SD_BLK_NUM 0x0030
43 #define OWL_REG_SD_BUF_SIZE 0x0034
46 #define OWL_SD_EN_RANE BIT(31)
47 #define OWL_SD_EN_RESE BIT(10)
48 #define OWL_SD_ENABLE BIT(7)
49 #define OWL_SD_EN_BSEL BIT(6)
50 #define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
51 #define OWL_SD_EN_DATAWID_MASK 0x03
54 #define OWL_SD_CTL_TOUTEN BIT(31)
55 #define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
56 #define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
57 #define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
58 #define OWL_SD_CTL_TS BIT(7)
59 #define OWL_SD_CTL_LBE BIT(6)
60 #define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
62 #define OWL_SD_DELAY_LOW_CLK 0x0f
63 #define OWL_SD_DELAY_MID_CLK 0x0a
64 #define OWL_SD_RDELAY_HIGH 0x08
65 #define OWL_SD_WDELAY_HIGH 0x09
68 #define OWL_SD_STATE_DAT0S BIT(7)
69 #define OWL_SD_STATE_CLNR BIT(4)
70 #define OWL_SD_STATE_CRC7ER BIT(0)
72 #define OWL_MMC_OCR (MMC_VDD_32_33 | MMC_VDD_33_34 | \
75 #define DATA_TRANSFER_TIMEOUT 3000000
76 #define DMA_TRANSFER_TIMEOUT 5000000
79 * Simple DMA transfer operations defines for MMC/SD card
81 #define SD_DMA_CHANNEL(base, channel) ((base) + 0x100 + 0x100 * (channel))
83 #define DMA_MODE 0x0000
84 #define DMA_SOURCE 0x0004
85 #define DMA_DESTINATION 0x0008
86 #define DMA_FRAME_LEN 0x000C
87 #define DMA_FRAME_CNT 0x0010
88 #define DMA_START 0x0024
91 #define DMA_MODE_ST(x) (((x) & 0x3) << 8)
92 #define DMA_MODE_ST_DEV DMA_MODE_ST(0)
93 #define DMA_MODE_DT(x) (((x) & 0x3) << 10)
94 #define DMA_MODE_DT_DCU DMA_MODE_DT(2)
95 #define DMA_MODE_SAM(x) (((x) & 0x3) << 16)
96 #define DMA_MODE_SAM_CONST DMA_MODE_SAM(0)
97 #define DMA_MODE_DAM(x) (((x) & 0x3) << 18)
98 #define DMA_MODE_DAM_INC DMA_MODE_DAM(1)
100 #define DMA_ENABLE 0x1
102 struct owl_mmc_plat {
103 struct mmc_config cfg;
107 struct owl_mmc_priv {
111 unsigned int clock; /* Current clock */
112 unsigned int dma_drq; /* Trigger Source */
115 static void owl_dma_config(struct owl_mmc_priv *priv, unsigned int src,
116 unsigned int dst, unsigned int len)
118 unsigned int mode = priv->dma_drq;
120 /* Set Source and Destination adderess mode */
121 mode |= (DMA_MODE_ST_DEV | DMA_MODE_SAM_CONST | DMA_MODE_DT_DCU |
124 writel(mode, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_MODE);
125 writel(src, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_SOURCE);
126 writel(dst, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_DESTINATION);
127 writel(len, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_FRAME_LEN);
128 writel(0x1, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_FRAME_CNT);
131 static void owl_mmc_prepare_data(struct owl_mmc_priv *priv,
132 struct mmc_data *data)
137 setbits_le32(priv->reg_base + OWL_REG_SD_EN, OWL_SD_EN_BSEL);
139 writel(data->blocks, priv->reg_base + OWL_REG_SD_BLK_NUM);
140 writel(data->blocksize, priv->reg_base + OWL_REG_SD_BLK_SIZE);
141 total = data->blocksize * data->blocks;
144 writel(total, priv->reg_base + OWL_REG_SD_BUF_SIZE);
146 writel(512, priv->reg_base + OWL_REG_SD_BUF_SIZE);
149 writel(0x0, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START);
152 if (data->flags == MMC_DATA_READ) {
153 buf = (ulong) (data->dest);
154 owl_dma_config(priv, (ulong) priv->reg_base +
155 OWL_REG_SD_DAT, buf, total);
156 invalidate_dcache_range(buf, buf + total);
158 buf = (ulong) (data->src);
159 owl_dma_config(priv, buf, (ulong) priv->reg_base +
160 OWL_REG_SD_DAT, total);
161 flush_dcache_range(buf, buf + total);
164 writel(0x1, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START);
168 static int owl_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
169 struct mmc_data *data)
171 struct owl_mmc_priv *priv = dev_get_priv(dev);
172 unsigned int cmd_rsp_mask, mode, reg;
175 setbits_le32(priv->reg_base + OWL_REG_SD_EN, OWL_SD_ENABLE);
179 if (cmd->resp_type != MMC_RSP_NONE)
180 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
181 if (cmd->resp_type == MMC_RSP_R1) {
183 if (data->flags == MMC_DATA_READ)
184 mode |= OWL_SD_CTL_TM(4);
186 mode |= OWL_SD_CTL_TM(5);
188 mode |= OWL_SD_CTL_TM(1);
189 } else if (cmd->resp_type == MMC_RSP_R2) {
190 mode = OWL_SD_CTL_TM(2);
191 } else if (cmd->resp_type == MMC_RSP_R1b) {
192 mode = OWL_SD_CTL_TM(3);
193 } else if (cmd->resp_type == MMC_RSP_R3) {
194 cmd_rsp_mask = OWL_SD_STATE_CLNR;
195 mode = OWL_SD_CTL_TM(1);
198 mode |= (readl(priv->reg_base + OWL_REG_SD_CTL) & (0xff << 16));
201 writel(cmd->cmdidx, priv->reg_base + OWL_REG_SD_CMD);
202 writel(cmd->cmdarg, priv->reg_base + OWL_REG_SD_ARG);
204 /* Set LBE to send clk at the end of last read block */
206 mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0xE4000000);
208 mode |= OWL_SD_CTL_TS;
211 owl_mmc_prepare_data(priv, data);
214 writel(mode, priv->reg_base + OWL_REG_SD_CTL);
216 ret = readl_poll_timeout(priv->reg_base + OWL_REG_SD_CTL, reg,
217 !(reg & OWL_SD_CTL_TS), DATA_TRANSFER_TIMEOUT);
219 if (ret == -ETIMEDOUT) {
220 debug("error: transferred data timeout\n");
224 reg = readl(priv->reg_base + OWL_REG_SD_STATE) & cmd_rsp_mask;
225 if (cmd->resp_type & MMC_RSP_PRESENT) {
226 if (reg & OWL_SD_STATE_CLNR) {
227 printf("Error CMD_NO_RSP\n");
231 if (reg & OWL_SD_STATE_CRC7ER) {
232 printf("Error CMD_RSP_CRC\n");
236 if (cmd->resp_type & MMC_RSP_136) {
237 cmd->response[3] = readl(priv->reg_base + OWL_REG_SD_RSPBUF0);
238 cmd->response[2] = readl(priv->reg_base + OWL_REG_SD_RSPBUF1);
239 cmd->response[1] = readl(priv->reg_base + OWL_REG_SD_RSPBUF2);
240 cmd->response[0] = readl(priv->reg_base + OWL_REG_SD_RSPBUF3);
244 rsp[0] = readl(priv->reg_base + OWL_REG_SD_RSPBUF0);
245 rsp[1] = readl(priv->reg_base + OWL_REG_SD_RSPBUF1);
246 cmd->response[0] = rsp[1] << 24 | rsp[0] >> 8;
247 cmd->response[1] = rsp[1] >> 8;
252 ret = readl_poll_timeout(SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START,
253 reg, !(reg & DMA_ENABLE), DMA_TRANSFER_TIMEOUT);
255 if (ret == -ETIMEDOUT) {
256 debug("error: DMA transfer timeout\n");
261 writel(0x0, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START);
262 /* Transmission STOP */
263 while (readl(priv->reg_base + OWL_REG_SD_CTL) & OWL_SD_CTL_TS)
264 clrbits_le32(priv->reg_base + OWL_REG_SD_CTL,
271 static int owl_mmc_clk_set(struct owl_mmc_priv *priv, int rate)
273 u32 reg, wdelay, rdelay;
275 reg = readl(priv->reg_base + OWL_REG_SD_CTL);
276 reg &= ~OWL_SD_CTL_DELAY_MSK;
278 /* Set RDELAY and WDELAY based on the clock */
280 rdelay = wdelay = OWL_SD_DELAY_LOW_CLK;
281 else if ((rate > 1000000) && (rate <= 26000000))
282 rdelay = wdelay = OWL_SD_DELAY_MID_CLK;
283 else if ((rate > 26000000) && (rate <= 52000000)) {
284 rdelay = OWL_SD_RDELAY_HIGH;
285 wdelay = OWL_SD_WDELAY_HIGH;
287 debug("SD clock rate not supported\n");
291 writel(reg | OWL_SD_CTL_RDELAY(rdelay) | OWL_SD_CTL_WDELAY(wdelay),
292 priv->reg_base + OWL_REG_SD_CTL);
297 static int owl_mmc_set_ios(struct udevice *dev)
299 struct owl_mmc_priv *priv = dev_get_priv(dev);
300 struct owl_mmc_plat *plat = dev_get_plat(dev);
301 struct mmc *mmc = &plat->mmc;
304 if (mmc->clock != priv->clock) {
305 priv->clock = mmc->clock;
306 ret = owl_mmc_clk_set(priv, mmc->clock);
307 if (IS_ERR_VALUE(ret))
310 ret = clk_set_rate(&priv->clk, mmc->clock);
311 if (IS_ERR_VALUE(ret))
315 if (mmc->clk_disable)
316 ret = clk_disable(&priv->clk);
318 ret = clk_enable(&priv->clk);
322 /* Set the Bus width */
323 reg = readl(priv->reg_base + OWL_REG_SD_EN);
324 reg &= ~OWL_SD_EN_DATAWID_MASK;
325 if (mmc->bus_width == 8)
326 reg |= OWL_SD_EN_DATAWID(2);
327 else if (mmc->bus_width == 4)
328 reg |= OWL_SD_EN_DATAWID(1);
330 writel(reg, priv->reg_base + OWL_REG_SD_EN);
335 static const struct dm_mmc_ops owl_mmc_ops = {
336 .send_cmd = owl_mmc_send_cmd,
337 .set_ios = owl_mmc_set_ios,
340 static int owl_mmc_probe(struct udevice *dev)
342 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
343 struct owl_mmc_plat *plat = dev_get_plat(dev);
344 struct owl_mmc_priv *priv = dev_get_priv(dev);
345 struct mmc_config *cfg = &plat->cfg;
346 struct ofnode_phandle_args args;
350 cfg->name = dev->name;
351 cfg->voltages = OWL_MMC_OCR;
353 cfg->f_max = 52000000;
355 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
357 ret = mmc_of_parse(dev, cfg);
361 addr = dev_read_addr(dev);
362 if (addr == FDT_ADDR_T_NONE)
365 priv->reg_base = (void *)addr;
367 ret = dev_read_phandle_with_args(dev, "dmas", "#dma-cells", 0, 0,
372 priv->dma_channel = (void *)ofnode_get_addr(args.node);
373 priv->dma_drq = args.args[0];
375 ret = clk_get_by_index(dev, 0, &priv->clk);
377 debug("clk_get_by_index() failed: %d\n", ret);
381 upriv->mmc = &plat->mmc;
386 static int owl_mmc_bind(struct udevice *dev)
388 struct owl_mmc_plat *plat = dev_get_plat(dev);
390 return mmc_bind(dev, &plat->mmc, &plat->cfg);
393 static const struct udevice_id owl_mmc_ids[] = {
394 { .compatible = "actions,s700-mmc" },
395 { .compatible = "actions,owl-mmc" },
399 U_BOOT_DRIVER(owl_mmc_drv) = {
402 .of_match = owl_mmc_ids,
403 .bind = owl_mmc_bind,
404 .probe = owl_mmc_probe,
406 .plat_auto = sizeof(struct owl_mmc_plat),
407 .priv_auto = sizeof(struct owl_mmc_priv),