omap5: pbias ldo9 turn on
[platform/kernel/u-boot.git] / drivers / mmc / omap_hsmmc.c
1 /*
2  * (C) Copyright 2008
3  * Texas Instruments, <www.ti.com>
4  * Sukumar Ghorai <s-ghorai@ti.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation's version 2 of
12  * the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24
25 #include <config.h>
26 #include <common.h>
27 #include <mmc.h>
28 #include <part.h>
29 #include <i2c.h>
30 #include <twl4030.h>
31 #include <twl6030.h>
32 #include <twl6035.h>
33 #include <asm/io.h>
34 #include <asm/arch/mmc_host_def.h>
35 #include <asm/arch/sys_proto.h>
36
37 /* If we fail after 1 second wait, something is really bad */
38 #define MAX_RETRY_MS    1000
39
40 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
41 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
42                         unsigned int siz);
43 static struct mmc hsmmc_dev[2];
44
45 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
46 static void omap4_vmmc_pbias_config(struct mmc *mmc)
47 {
48         u32 value = 0;
49         struct omap_sys_ctrl_regs *const ctrl =
50                 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
51
52
53         value = readl(&ctrl->control_pbiaslite);
54         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
55         writel(value, &ctrl->control_pbiaslite);
56         /* set VMMC to 3V */
57         twl6030_power_mmc_init();
58         value = readl(&ctrl->control_pbiaslite);
59         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
60         writel(value, &ctrl->control_pbiaslite);
61 }
62 #endif
63
64 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
65 static void omap5_pbias_config(struct mmc *mmc)
66 {
67         u32 value = 0;
68         struct omap_sys_ctrl_regs *const ctrl =
69                 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
70
71         value = readl(&ctrl->control_pbias);
72         value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
73         value |= SDCARD_BIAS_HIZ_MODE;
74         writel(value, &ctrl->control_pbias);
75
76         twl6035_mmc1_poweron_ldo();
77
78         value = readl(&ctrl->control_pbias);
79         value &= ~SDCARD_BIAS_HIZ_MODE;
80         value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
81         writel(value, &ctrl->control_pbias);
82
83         value = readl(&ctrl->control_pbias);
84         if (value & (1 << 23)) {
85                 value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
86                 value |= SDCARD_BIAS_HIZ_MODE;
87                 writel(value, &ctrl->control_pbias);
88         }
89 }
90 #endif
91
92 unsigned char mmc_board_init(struct mmc *mmc)
93 {
94 #if defined(CONFIG_TWL4030_POWER)
95         twl4030_power_mmc_init();
96 #endif
97
98 #if defined(CONFIG_OMAP34XX)
99         t2_t *t2_base = (t2_t *)T2_BASE;
100         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
101
102         writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
103                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
104                 &t2_base->pbias_lite);
105
106         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
107                 &t2_base->devconf0);
108
109         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
110                 &t2_base->devconf1);
111
112         /* Change from default of 52MHz to 26MHz if necessary */
113         if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
114                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
115                         &t2_base->ctl_prog_io1);
116
117         writel(readl(&prcm_base->fclken1_core) |
118                 EN_MMC1 | EN_MMC2 | EN_MMC3,
119                 &prcm_base->fclken1_core);
120
121         writel(readl(&prcm_base->iclken1_core) |
122                 EN_MMC1 | EN_MMC2 | EN_MMC3,
123                 &prcm_base->iclken1_core);
124 #endif
125
126 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
127         /* PBIAS config needed for MMC1 only */
128         if (mmc->block_dev.dev == 0)
129                 omap4_vmmc_pbias_config(mmc);
130 #endif
131 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
132         if (mmc->block_dev.dev == 0)
133                 omap5_pbias_config(mmc);
134 #endif
135
136         return 0;
137 }
138
139 void mmc_init_stream(struct hsmmc *mmc_base)
140 {
141         ulong start;
142
143         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
144
145         writel(MMC_CMD0, &mmc_base->cmd);
146         start = get_timer(0);
147         while (!(readl(&mmc_base->stat) & CC_MASK)) {
148                 if (get_timer(0) - start > MAX_RETRY_MS) {
149                         printf("%s: timedout waiting for cc!\n", __func__);
150                         return;
151                 }
152         }
153         writel(CC_MASK, &mmc_base->stat)
154                 ;
155         writel(MMC_CMD0, &mmc_base->cmd)
156                 ;
157         start = get_timer(0);
158         while (!(readl(&mmc_base->stat) & CC_MASK)) {
159                 if (get_timer(0) - start > MAX_RETRY_MS) {
160                         printf("%s: timedout waiting for cc2!\n", __func__);
161                         return;
162                 }
163         }
164         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
165 }
166
167
168 static int mmc_init_setup(struct mmc *mmc)
169 {
170         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
171         unsigned int reg_val;
172         unsigned int dsor;
173         ulong start;
174
175         mmc_board_init(mmc);
176
177         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
178                 &mmc_base->sysconfig);
179         start = get_timer(0);
180         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
181                 if (get_timer(0) - start > MAX_RETRY_MS) {
182                         printf("%s: timedout waiting for cc2!\n", __func__);
183                         return TIMEOUT;
184                 }
185         }
186         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
187         start = get_timer(0);
188         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
189                 if (get_timer(0) - start > MAX_RETRY_MS) {
190                         printf("%s: timedout waiting for softresetall!\n",
191                                 __func__);
192                         return TIMEOUT;
193                 }
194         }
195         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
196         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
197                 &mmc_base->capa);
198
199         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
200
201         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
202                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
203                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
204
205         dsor = 240;
206         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
207                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
208         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
209                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
210         start = get_timer(0);
211         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
212                 if (get_timer(0) - start > MAX_RETRY_MS) {
213                         printf("%s: timedout waiting for ics!\n", __func__);
214                         return TIMEOUT;
215                 }
216         }
217         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
218
219         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
220
221         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
222                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
223                 &mmc_base->ie);
224
225         mmc_init_stream(mmc_base);
226
227         return 0;
228 }
229
230
231 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
232                         struct mmc_data *data)
233 {
234         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
235         unsigned int flags, mmc_stat;
236         ulong start;
237
238         start = get_timer(0);
239         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
240                 if (get_timer(0) - start > MAX_RETRY_MS) {
241                         printf("%s: timedout waiting on cmd inhibit to clear\n",
242                                         __func__);
243                         return TIMEOUT;
244                 }
245         }
246         writel(0xFFFFFFFF, &mmc_base->stat);
247         start = get_timer(0);
248         while (readl(&mmc_base->stat)) {
249                 if (get_timer(0) - start > MAX_RETRY_MS) {
250                         printf("%s: timedout waiting for stat!\n", __func__);
251                         return TIMEOUT;
252                 }
253         }
254         /*
255          * CMDREG
256          * CMDIDX[13:8] : Command index
257          * DATAPRNT[5]  : Data Present Select
258          * ENCMDIDX[4]  : Command Index Check Enable
259          * ENCMDCRC[3]  : Command CRC Check Enable
260          * RSPTYP[1:0]
261          *      00 = No Response
262          *      01 = Length 136
263          *      10 = Length 48
264          *      11 = Length 48 Check busy after response
265          */
266         /* Delay added before checking the status of frq change
267          * retry not supported by mmc.c(core file)
268          */
269         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
270                 udelay(50000); /* wait 50 ms */
271
272         if (!(cmd->resp_type & MMC_RSP_PRESENT))
273                 flags = 0;
274         else if (cmd->resp_type & MMC_RSP_136)
275                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
276         else if (cmd->resp_type & MMC_RSP_BUSY)
277                 flags = RSP_TYPE_LGHT48B;
278         else
279                 flags = RSP_TYPE_LGHT48;
280
281         /* enable default flags */
282         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
283                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
284
285         if (cmd->resp_type & MMC_RSP_CRC)
286                 flags |= CCCE_CHECK;
287         if (cmd->resp_type & MMC_RSP_OPCODE)
288                 flags |= CICE_CHECK;
289
290         if (data) {
291                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
292                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
293                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
294                         data->blocksize = 512;
295                         writel(data->blocksize | (data->blocks << 16),
296                                                         &mmc_base->blk);
297                 } else
298                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
299
300                 if (data->flags & MMC_DATA_READ)
301                         flags |= (DP_DATA | DDIR_READ);
302                 else
303                         flags |= (DP_DATA | DDIR_WRITE);
304         }
305
306         writel(cmd->cmdarg, &mmc_base->arg);
307         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
308
309         start = get_timer(0);
310         do {
311                 mmc_stat = readl(&mmc_base->stat);
312                 if (get_timer(0) - start > MAX_RETRY_MS) {
313                         printf("%s : timeout: No status update\n", __func__);
314                         return TIMEOUT;
315                 }
316         } while (!mmc_stat);
317
318         if ((mmc_stat & IE_CTO) != 0)
319                 return TIMEOUT;
320         else if ((mmc_stat & ERRI_MASK) != 0)
321                 return -1;
322
323         if (mmc_stat & CC_MASK) {
324                 writel(CC_MASK, &mmc_base->stat);
325                 if (cmd->resp_type & MMC_RSP_PRESENT) {
326                         if (cmd->resp_type & MMC_RSP_136) {
327                                 /* response type 2 */
328                                 cmd->response[3] = readl(&mmc_base->rsp10);
329                                 cmd->response[2] = readl(&mmc_base->rsp32);
330                                 cmd->response[1] = readl(&mmc_base->rsp54);
331                                 cmd->response[0] = readl(&mmc_base->rsp76);
332                         } else
333                                 /* response types 1, 1b, 3, 4, 5, 6 */
334                                 cmd->response[0] = readl(&mmc_base->rsp10);
335                 }
336         }
337
338         if (data && (data->flags & MMC_DATA_READ)) {
339                 mmc_read_data(mmc_base, data->dest,
340                                 data->blocksize * data->blocks);
341         } else if (data && (data->flags & MMC_DATA_WRITE)) {
342                 mmc_write_data(mmc_base, data->src,
343                                 data->blocksize * data->blocks);
344         }
345         return 0;
346 }
347
348 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
349 {
350         unsigned int *output_buf = (unsigned int *)buf;
351         unsigned int mmc_stat;
352         unsigned int count;
353
354         /*
355          * Start Polled Read
356          */
357         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
358         count /= 4;
359
360         while (size) {
361                 ulong start = get_timer(0);
362                 do {
363                         mmc_stat = readl(&mmc_base->stat);
364                         if (get_timer(0) - start > MAX_RETRY_MS) {
365                                 printf("%s: timedout waiting for status!\n",
366                                                 __func__);
367                                 return TIMEOUT;
368                         }
369                 } while (mmc_stat == 0);
370
371                 if ((mmc_stat & ERRI_MASK) != 0)
372                         return 1;
373
374                 if (mmc_stat & BRR_MASK) {
375                         unsigned int k;
376
377                         writel(readl(&mmc_base->stat) | BRR_MASK,
378                                 &mmc_base->stat);
379                         for (k = 0; k < count; k++) {
380                                 *output_buf = readl(&mmc_base->data);
381                                 output_buf++;
382                         }
383                         size -= (count*4);
384                 }
385
386                 if (mmc_stat & BWR_MASK)
387                         writel(readl(&mmc_base->stat) | BWR_MASK,
388                                 &mmc_base->stat);
389
390                 if (mmc_stat & TC_MASK) {
391                         writel(readl(&mmc_base->stat) | TC_MASK,
392                                 &mmc_base->stat);
393                         break;
394                 }
395         }
396         return 0;
397 }
398
399 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
400                                 unsigned int size)
401 {
402         unsigned int *input_buf = (unsigned int *)buf;
403         unsigned int mmc_stat;
404         unsigned int count;
405
406         /*
407          * Start Polled Read
408          */
409         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
410         count /= 4;
411
412         while (size) {
413                 ulong start = get_timer(0);
414                 do {
415                         mmc_stat = readl(&mmc_base->stat);
416                         if (get_timer(0) - start > MAX_RETRY_MS) {
417                                 printf("%s: timedout waiting for status!\n",
418                                                 __func__);
419                                 return TIMEOUT;
420                         }
421                 } while (mmc_stat == 0);
422
423                 if ((mmc_stat & ERRI_MASK) != 0)
424                         return 1;
425
426                 if (mmc_stat & BWR_MASK) {
427                         unsigned int k;
428
429                         writel(readl(&mmc_base->stat) | BWR_MASK,
430                                         &mmc_base->stat);
431                         for (k = 0; k < count; k++) {
432                                 writel(*input_buf, &mmc_base->data);
433                                 input_buf++;
434                         }
435                         size -= (count*4);
436                 }
437
438                 if (mmc_stat & BRR_MASK)
439                         writel(readl(&mmc_base->stat) | BRR_MASK,
440                                 &mmc_base->stat);
441
442                 if (mmc_stat & TC_MASK) {
443                         writel(readl(&mmc_base->stat) | TC_MASK,
444                                 &mmc_base->stat);
445                         break;
446                 }
447         }
448         return 0;
449 }
450
451 static void mmc_set_ios(struct mmc *mmc)
452 {
453         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
454         unsigned int dsor = 0;
455         ulong start;
456
457         /* configue bus width */
458         switch (mmc->bus_width) {
459         case 8:
460                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
461                         &mmc_base->con);
462                 break;
463
464         case 4:
465                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
466                         &mmc_base->con);
467                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
468                         &mmc_base->hctl);
469                 break;
470
471         case 1:
472         default:
473                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
474                         &mmc_base->con);
475                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
476                         &mmc_base->hctl);
477                 break;
478         }
479
480         /* configure clock with 96Mhz system clock.
481          */
482         if (mmc->clock != 0) {
483                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
484                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
485                         dsor++;
486         }
487
488         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
489                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
490
491         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
492                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
493
494         start = get_timer(0);
495         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
496                 if (get_timer(0) - start > MAX_RETRY_MS) {
497                         printf("%s: timedout waiting for ics!\n", __func__);
498                         return;
499                 }
500         }
501         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
502 }
503
504 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
505 {
506         struct mmc *mmc;
507
508         mmc = &hsmmc_dev[dev_index];
509
510         sprintf(mmc->name, "OMAP SD/MMC");
511         mmc->send_cmd = mmc_send_cmd;
512         mmc->set_ios = mmc_set_ios;
513         mmc->init = mmc_init_setup;
514         mmc->getcd = NULL;
515
516         switch (dev_index) {
517         case 0:
518                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
519                 break;
520 #ifdef OMAP_HSMMC2_BASE
521         case 1:
522                 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
523                 break;
524 #endif
525 #ifdef OMAP_HSMMC3_BASE
526         case 2:
527                 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
528                 break;
529 #endif
530         default:
531                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
532                 return 1;
533         }
534         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
535         mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
536                                 MMC_MODE_HC) & ~host_caps_mask;
537
538         mmc->f_min = 400000;
539
540         if (f_max != 0)
541                 mmc->f_max = f_max;
542         else {
543                 if (mmc->host_caps & MMC_MODE_HS) {
544                         if (mmc->host_caps & MMC_MODE_HS_52MHz)
545                                 mmc->f_max = 52000000;
546                         else
547                                 mmc->f_max = 26000000;
548                 } else
549                         mmc->f_max = 20000000;
550         }
551
552         mmc->b_max = 0;
553
554 #if defined(CONFIG_OMAP34XX)
555         /*
556          * Silicon revs 2.1 and older do not support multiblock transfers.
557          */
558         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
559                 mmc->b_max = 1;
560 #endif
561
562         mmc_register(mmc);
563
564         return 0;
565 }