3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
37 #include <asm/cache.h>
39 #include <asm/arch/mmc_host_def.h>
40 #ifdef CONFIG_OMAP54XX
41 #include <asm/arch/mux_dra7xx.h>
42 #include <asm/arch/dra7xx_iodelay.h>
44 #if !defined(CONFIG_SOC_KEYSTONE)
46 #include <asm/arch/sys_proto.h>
48 #ifdef CONFIG_MMC_OMAP36XX_PINS
49 #include <asm/arch/mux.h>
52 #include <dm/devres.h>
53 #include <linux/bitops.h>
54 #include <linux/delay.h>
55 #include <linux/err.h>
56 #include <power/regulator.h>
59 DECLARE_GLOBAL_DATA_PTR;
61 /* simplify defines to OMAP_HSMMC_USE_GPIO */
62 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
63 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
64 #define OMAP_HSMMC_USE_GPIO
66 #undef OMAP_HSMMC_USE_GPIO
69 /* common definitions for all OMAPs */
70 #define SYSCTL_SRC (1 << 25)
71 #define SYSCTL_SRD (1 << 26)
73 #ifdef CONFIG_IODELAY_RECALIBRATION
74 struct omap_hsmmc_pinctrl_state {
75 struct pad_conf_entry *padconf;
77 struct iodelay_cfg_entry *iodelay;
82 struct omap_hsmmc_data {
83 struct hsmmc *base_addr;
84 #if !CONFIG_IS_ENABLED(DM_MMC)
85 struct mmc_config cfg;
90 #ifdef OMAP_HSMMC_USE_GPIO
91 #if CONFIG_IS_ENABLED(DM_MMC)
92 struct gpio_desc cd_gpio; /* Change Detect GPIO */
93 struct gpio_desc wp_gpio; /* Write Protect GPIO */
99 #if CONFIG_IS_ENABLED(DM_MMC)
103 #ifdef CONFIG_MMC_OMAP_HS_ADMA
104 struct omap_hsmmc_adma_desc *adma_desc_table;
108 struct udevice *pbias_supply;
110 #ifdef CONFIG_IODELAY_RECALIBRATION
111 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
112 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
113 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
114 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
115 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
116 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
117 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
118 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
119 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
123 struct omap_mmc_of_data {
127 #ifdef CONFIG_MMC_OMAP_HS_ADMA
128 struct omap_hsmmc_adma_desc {
135 #define ADMA_MAX_LEN 63488
137 /* Decriptor table defines */
138 #define ADMA_DESC_ATTR_VALID BIT(0)
139 #define ADMA_DESC_ATTR_END BIT(1)
140 #define ADMA_DESC_ATTR_INT BIT(2)
141 #define ADMA_DESC_ATTR_ACT1 BIT(4)
142 #define ADMA_DESC_ATTR_ACT2 BIT(5)
144 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
145 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
148 /* If we fail after 1 second wait, something is really bad */
149 #define MAX_RETRY_MS 1000
150 #define MMC_TIMEOUT_MS 20
152 /* DMA transfers can take a long time if a lot a data is transferred.
153 * The timeout must take in account the amount of data. Let's assume
154 * that the time will never exceed 333 ms per MB (in other word we assume
155 * that the bandwidth is always above 3MB/s).
157 #define DMA_TIMEOUT_PER_MB 333
158 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
159 #define OMAP_HSMMC_NO_1_8_V BIT(1)
160 #define OMAP_HSMMC_USE_ADMA BIT(2)
161 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
163 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
164 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
166 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
167 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
168 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
170 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
172 #if CONFIG_IS_ENABLED(DM_MMC)
173 return dev_get_priv(mmc->dev);
175 return (struct omap_hsmmc_data *)mmc->priv;
179 #if defined(CONFIG_OMAP34XX) || defined(CONFIG_IODELAY_RECALIBRATION)
180 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
182 #if CONFIG_IS_ENABLED(DM_MMC)
183 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
186 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
191 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
192 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
196 #if !CONFIG_IS_ENABLED(DM_GPIO)
197 if (!gpio_is_valid(gpio))
200 ret = gpio_request(gpio, label);
204 ret = gpio_direction_input(gpio);
212 static unsigned char mmc_board_init(struct mmc *mmc)
214 #if defined(CONFIG_OMAP34XX)
215 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
216 t2_t *t2_base = (t2_t *)T2_BASE;
217 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
219 #ifdef CONFIG_MMC_OMAP36XX_PINS
220 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
223 pbias_lite = readl(&t2_base->pbias_lite);
224 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
225 #ifdef CONFIG_TARGET_OMAP3_CAIRO
226 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
227 pbias_lite &= ~PBIASLITEVMODE0;
229 #ifdef CONFIG_TARGET_OMAP3_LOGIC
230 /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
231 pbias_lite &= ~PBIASLITEVMODE1;
233 #ifdef CONFIG_MMC_OMAP36XX_PINS
234 if (get_cpu_family() == CPU_OMAP36XX) {
235 /* Disable extended drain IO before changing PBIAS */
236 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
237 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
240 writel(pbias_lite, &t2_base->pbias_lite);
242 writel(pbias_lite | PBIASLITEPWRDNZ1 |
243 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
244 &t2_base->pbias_lite);
246 #ifdef CONFIG_MMC_OMAP36XX_PINS
247 if (get_cpu_family() == CPU_OMAP36XX)
248 /* Enable extended drain IO after changing PBIAS */
250 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
251 OMAP34XX_CTRL_WKUP_CTRL);
253 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
256 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
259 /* Change from default of 52MHz to 26MHz if necessary */
260 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
261 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
262 &t2_base->ctl_prog_io1);
264 writel(readl(&prcm_base->fclken1_core) |
265 EN_MMC1 | EN_MMC2 | EN_MMC3,
266 &prcm_base->fclken1_core);
268 writel(readl(&prcm_base->iclken1_core) |
269 EN_MMC1 | EN_MMC2 | EN_MMC3,
270 &prcm_base->iclken1_core);
273 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
274 !CONFIG_IS_ENABLED(DM_REGULATOR)
275 /* PBIAS config needed for MMC1 only */
276 if (mmc_get_blk_desc(mmc)->devnum == 0)
277 vmmc_pbias_config(LDO_VOLT_3V3);
283 void mmc_init_stream(struct hsmmc *mmc_base)
287 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
289 writel(MMC_CMD0, &mmc_base->cmd);
290 start = get_timer(0);
291 while (!(readl(&mmc_base->stat) & CC_MASK)) {
292 if (get_timer(0) - start > MAX_RETRY_MS) {
293 printf("%s: timedout waiting for cc!\n", __func__);
297 writel(CC_MASK, &mmc_base->stat)
299 writel(MMC_CMD0, &mmc_base->cmd)
301 start = get_timer(0);
302 while (!(readl(&mmc_base->stat) & CC_MASK)) {
303 if (get_timer(0) - start > MAX_RETRY_MS) {
304 printf("%s: timedout waiting for cc2!\n", __func__);
308 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
311 #if CONFIG_IS_ENABLED(DM_MMC)
312 #ifdef CONFIG_IODELAY_RECALIBRATION
313 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
315 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
316 struct omap_hsmmc_pinctrl_state *pinctrl_state;
318 switch (priv->mode) {
320 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
323 pinctrl_state = priv->sdr104_pinctrl_state;
326 pinctrl_state = priv->sdr50_pinctrl_state;
329 pinctrl_state = priv->ddr50_pinctrl_state;
332 pinctrl_state = priv->sdr25_pinctrl_state;
335 pinctrl_state = priv->sdr12_pinctrl_state;
340 pinctrl_state = priv->hs_pinctrl_state;
343 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
345 pinctrl_state = priv->default_pinctrl_state;
350 pinctrl_state = priv->default_pinctrl_state;
352 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
353 if (pinctrl_state->iodelay)
354 late_recalibrate_iodelay(pinctrl_state->padconf,
355 pinctrl_state->npads,
356 pinctrl_state->iodelay,
357 pinctrl_state->niodelays);
359 do_set_mux32((*ctrl)->control_padconf_core_base,
360 pinctrl_state->padconf,
361 pinctrl_state->npads);
365 static void omap_hsmmc_set_timing(struct mmc *mmc)
368 struct hsmmc *mmc_base;
369 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
371 mmc_base = priv->base_addr;
373 omap_hsmmc_stop_clock(mmc_base);
374 val = readl(&mmc_base->ac12);
375 val &= ~AC12_UHSMC_MASK;
376 priv->mode = mmc->selected_mode;
378 if (mmc_is_mode_ddr(priv->mode))
379 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
381 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
383 switch (priv->mode) {
386 val |= AC12_UHSMC_SDR104;
389 val |= AC12_UHSMC_SDR50;
393 val |= AC12_UHSMC_DDR50;
398 val |= AC12_UHSMC_SDR25;
403 val |= AC12_UHSMC_SDR12;
406 val |= AC12_UHSMC_RES;
409 writel(val, &mmc_base->ac12);
411 #ifdef CONFIG_IODELAY_RECALIBRATION
412 omap_hsmmc_io_recalibrate(mmc);
414 omap_hsmmc_start_clock(mmc_base);
417 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
419 struct hsmmc *mmc_base;
420 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
423 mmc_base = priv->base_addr;
425 hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
426 ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
428 switch (signal_voltage) {
429 case MMC_SIGNAL_VOLTAGE_330:
432 case MMC_SIGNAL_VOLTAGE_180:
434 ac12 |= AC12_V1V8_SIGEN;
438 writel(hctl, &mmc_base->hctl);
439 writel(ac12, &mmc_base->ac12);
442 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
444 int ret = -ETIMEDOUT;
447 bool target_dat0_high = !!state;
448 struct omap_hsmmc_data *priv = dev_get_priv(dev);
449 struct hsmmc *mmc_base = priv->base_addr;
451 con = readl(&mmc_base->con);
452 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
454 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
455 while (timeout_us--) {
456 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
457 if (dat0_high == target_dat0_high) {
463 writel(con, &mmc_base->con);
468 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
469 #if CONFIG_IS_ENABLED(DM_REGULATOR)
470 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
475 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
477 if (!mmc->vqmmc_supply)
481 ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
485 /* Turn off IO voltage */
486 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
489 /* Program a new IO voltage value */
490 ret = regulator_set_value(mmc->vqmmc_supply, uV);
493 /* Turn on IO voltage */
494 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
498 /* Program PBIAS voltage*/
499 ret = regulator_set_value(priv->pbias_supply, uV);
500 if (ret && ret != -ENOSYS)
503 ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
511 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
513 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
514 struct hsmmc *mmc_base = priv->base_addr;
515 int mv = mmc_voltage_to_mv(mmc->signal_voltage);
517 __maybe_unused u8 palmas_ldo_volt;
523 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
525 capa_mask = VS33_3V3SUP;
526 palmas_ldo_volt = LDO_VOLT_3V3;
527 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
528 capa_mask = VS18_1V8SUP;
529 palmas_ldo_volt = LDO_VOLT_1V8;
534 val = readl(&mmc_base->capa);
535 if (!(val & capa_mask))
538 priv->signal_voltage = mmc->signal_voltage;
540 omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
542 #if CONFIG_IS_ENABLED(DM_REGULATOR)
543 return omap_hsmmc_set_io_regulator(mmc, mv);
544 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
545 defined(CONFIG_PALMAS_POWER)
546 if (mmc_get_blk_desc(mmc)->devnum == 0)
547 vmmc_pbias_config(palmas_ldo_volt);
555 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
557 struct hsmmc *mmc_base;
558 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
561 mmc_base = priv->base_addr;
562 val = readl(&mmc_base->capa);
564 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
565 val |= (VS33_3V3SUP | VS18_1V8SUP);
566 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
574 writel(val, &mmc_base->capa);
579 #ifdef MMC_SUPPORTS_TUNING
580 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
582 struct hsmmc *mmc_base;
583 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
586 mmc_base = priv->base_addr;
587 val = readl(&mmc_base->ac12);
588 val &= ~(AC12_SCLK_SEL);
589 writel(val, &mmc_base->ac12);
591 val = readl(&mmc_base->dll);
592 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
593 writel(val, &mmc_base->dll);
596 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
599 struct hsmmc *mmc_base;
600 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
603 mmc_base = priv->base_addr;
604 val = readl(&mmc_base->dll);
605 val |= DLL_FORCE_VALUE;
606 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
607 val |= (count << DLL_FORCE_SR_C_SHIFT);
608 writel(val, &mmc_base->dll);
611 writel(val, &mmc_base->dll);
612 for (i = 0; i < 1000; i++) {
613 if (readl(&mmc_base->dll) & DLL_CALIB)
617 writel(val, &mmc_base->dll);
620 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
622 struct omap_hsmmc_data *priv = dev_get_priv(dev);
623 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
624 struct mmc *mmc = upriv->mmc;
625 struct hsmmc *mmc_base;
627 u8 cur_match, prev_match = 0;
630 u32 start_window = 0, max_window = 0;
631 u32 length = 0, max_len = 0;
632 bool single_point_failure = false;
633 struct udevice *thermal_dev;
637 mmc_base = priv->base_addr;
638 val = readl(&mmc_base->capa2);
640 /* clock tuning is not needed for upto 52MHz */
641 if (!((mmc->selected_mode == MMC_HS_200) ||
642 (mmc->selected_mode == UHS_SDR104) ||
643 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
646 ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
648 printf("Couldn't get thermal device for tuning\n");
651 ret = thermal_get_temp(thermal_dev, &temperature);
653 printf("Couldn't get temperature for tuning\n");
656 val = readl(&mmc_base->dll);
658 writel(val, &mmc_base->dll);
661 * Stage 1: Search for a maximum pass window ignoring any
662 * any single point failures. If the tuning value ends up
663 * near it, move away from it in stage 2 below
665 while (phase_delay <= MAX_PHASE_DELAY) {
666 omap_hsmmc_set_dll(mmc, phase_delay);
668 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
673 } else if (single_point_failure) {
674 /* ignore single point failure */
676 single_point_failure = false;
678 start_window = phase_delay;
682 single_point_failure = prev_match;
685 if (length > max_len) {
686 max_window = start_window;
690 prev_match = cur_match;
699 val = readl(&mmc_base->ac12);
700 if (!(val & AC12_SCLK_SEL)) {
705 * Assign tuning value as a ratio of maximum pass window based
708 if (temperature < -20000)
709 phase_delay = min(max_window + 4 * max_len - 24,
711 DIV_ROUND_UP(13 * max_len, 16) * 4);
712 else if (temperature < 20000)
713 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
714 else if (temperature < 40000)
715 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
716 else if (temperature < 70000)
717 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
718 else if (temperature < 90000)
719 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
720 else if (temperature < 120000)
721 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
723 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
726 * Stage 2: Search for a single point failure near the chosen tuning
727 * value in two steps. First in the +3 to +10 range and then in the
728 * +2 to -10 range. If found, move away from it in the appropriate
729 * direction by the appropriate amount depending on the temperature.
731 for (i = 3; i <= 10; i++) {
732 omap_hsmmc_set_dll(mmc, phase_delay + i);
733 if (mmc_send_tuning(mmc, opcode, NULL)) {
734 if (temperature < 10000)
735 phase_delay += i + 6;
736 else if (temperature < 20000)
737 phase_delay += i - 12;
738 else if (temperature < 70000)
739 phase_delay += i - 8;
740 else if (temperature < 90000)
741 phase_delay += i - 6;
743 phase_delay += i - 6;
745 goto single_failure_found;
749 for (i = 2; i >= -10; i--) {
750 omap_hsmmc_set_dll(mmc, phase_delay + i);
751 if (mmc_send_tuning(mmc, opcode, NULL)) {
752 if (temperature < 10000)
753 phase_delay += i + 12;
754 else if (temperature < 20000)
755 phase_delay += i + 8;
756 else if (temperature < 70000)
757 phase_delay += i + 8;
758 else if (temperature < 90000)
759 phase_delay += i + 10;
761 phase_delay += i + 12;
763 goto single_failure_found;
767 single_failure_found:
769 omap_hsmmc_set_dll(mmc, phase_delay);
771 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
772 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
778 omap_hsmmc_disable_tuning(mmc);
779 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
780 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
787 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
789 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
790 struct hsmmc *mmc_base = priv->base_addr;
791 u32 irq_mask = INT_EN_MASK;
794 * TODO: Errata i802 indicates only DCRC interrupts can occur during
795 * tuning procedure and DCRC should be disabled. But see occurences
796 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
797 * interrupts occur along with BRR, so the data is actually in the
798 * buffer. It has to be debugged why these interrutps occur
800 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
801 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
803 writel(irq_mask, &mmc_base->ie);
806 static int omap_hsmmc_init_setup(struct mmc *mmc)
808 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
809 struct hsmmc *mmc_base;
810 unsigned int reg_val;
814 mmc_base = priv->base_addr;
817 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
818 &mmc_base->sysconfig);
819 start = get_timer(0);
820 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
821 if (get_timer(0) - start > MAX_RETRY_MS) {
822 printf("%s: timedout waiting for cc2!\n", __func__);
826 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
827 start = get_timer(0);
828 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
829 if (get_timer(0) - start > MAX_RETRY_MS) {
830 printf("%s: timedout waiting for softresetall!\n",
835 #ifdef CONFIG_MMC_OMAP_HS_ADMA
836 reg_val = readl(&mmc_base->hl_hwinfo);
837 if (reg_val & MADMA_EN)
838 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
841 #if CONFIG_IS_ENABLED(DM_MMC)
842 reg_val = omap_hsmmc_set_capabilities(mmc);
843 omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
844 MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
846 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V3, &mmc_base->hctl);
847 writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
851 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
853 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
854 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
855 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
858 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
859 (ICE_STOP | DTO_15THDTO));
860 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
861 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
862 start = get_timer(0);
863 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
864 if (get_timer(0) - start > MAX_RETRY_MS) {
865 printf("%s: timedout waiting for ics!\n", __func__);
869 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
871 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
873 mmc_enable_irq(mmc, NULL);
875 #if !CONFIG_IS_ENABLED(DM_MMC)
876 mmc_init_stream(mmc_base);
883 * MMC controller internal finite state machine reset
885 * Used to reset command or data internal state machines, using respectively
886 * SRC or SRD bit of SYSCTL register
888 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
892 mmc_reg_out(&mmc_base->sysctl, bit, bit);
895 * CMD(DAT) lines reset procedures are slightly different
896 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
897 * According to OMAP3 TRM:
898 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
900 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
901 * procedure steps must be as follows:
902 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
903 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
904 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
905 * 3. Wait until the SRC (SRD) bit returns to 0x0
906 * (reset procedure is completed).
908 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
909 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
910 if (!(readl(&mmc_base->sysctl) & bit)) {
911 start = get_timer(0);
912 while (!(readl(&mmc_base->sysctl) & bit)) {
913 if (get_timer(0) - start > MMC_TIMEOUT_MS)
918 start = get_timer(0);
919 while ((readl(&mmc_base->sysctl) & bit) != 0) {
920 if (get_timer(0) - start > MAX_RETRY_MS) {
921 printf("%s: timedout waiting for sysctl %x to clear\n",
928 #ifdef CONFIG_MMC_OMAP_HS_ADMA
929 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
931 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
932 struct omap_hsmmc_adma_desc *desc;
935 desc = &priv->adma_desc_table[priv->desc_slot];
937 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
941 attr |= ADMA_DESC_ATTR_END;
944 desc->addr = (u32)buf;
949 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
950 struct mmc_data *data)
952 uint total_len = data->blocksize * data->blocks;
953 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
954 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
959 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
960 memalign(ARCH_DMA_MINALIGN, desc_count *
961 sizeof(struct omap_hsmmc_adma_desc));
963 if (data->flags & MMC_DATA_READ)
966 buf = (char *)data->src;
969 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
971 total_len -= ADMA_MAX_LEN;
974 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
976 flush_dcache_range((long)priv->adma_desc_table,
977 (long)priv->adma_desc_table +
979 sizeof(struct omap_hsmmc_adma_desc),
983 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
985 struct hsmmc *mmc_base;
986 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
990 mmc_base = priv->base_addr;
991 omap_hsmmc_prepare_adma_table(mmc, data);
993 if (data->flags & MMC_DATA_READ)
996 buf = (char *)data->src;
998 val = readl(&mmc_base->hctl);
1000 writel(val, &mmc_base->hctl);
1002 val = readl(&mmc_base->con);
1004 writel(val, &mmc_base->con);
1006 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1008 flush_dcache_range((u32)buf,
1010 ROUND(data->blocksize * data->blocks,
1011 ARCH_DMA_MINALIGN));
1014 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1016 struct hsmmc *mmc_base;
1017 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1020 mmc_base = priv->base_addr;
1022 val = readl(&mmc_base->con);
1024 writel(val, &mmc_base->con);
1026 val = readl(&mmc_base->hctl);
1028 writel(val, &mmc_base->hctl);
1030 kfree(priv->adma_desc_table);
1033 #define omap_hsmmc_adma_desc
1034 #define omap_hsmmc_prepare_adma_table
1035 #define omap_hsmmc_prepare_data
1036 #define omap_hsmmc_dma_cleanup
1039 #if !CONFIG_IS_ENABLED(DM_MMC)
1040 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1041 struct mmc_data *data)
1043 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1045 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1046 struct mmc_data *data)
1048 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1049 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1050 struct mmc *mmc = upriv->mmc;
1052 struct hsmmc *mmc_base;
1053 unsigned int flags, mmc_stat;
1055 priv->last_cmd = cmd->cmdidx;
1057 mmc_base = priv->base_addr;
1059 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1062 start = get_timer(0);
1063 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1064 if (get_timer(0) - start > MAX_RETRY_MS) {
1065 printf("%s: timedout waiting on cmd inhibit to clear\n",
1067 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1068 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1072 writel(0xFFFFFFFF, &mmc_base->stat);
1073 if (readl(&mmc_base->stat)) {
1074 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1075 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1080 * CMDIDX[13:8] : Command index
1081 * DATAPRNT[5] : Data Present Select
1082 * ENCMDIDX[4] : Command Index Check Enable
1083 * ENCMDCRC[3] : Command CRC Check Enable
1088 * 11 = Length 48 Check busy after response
1090 /* Delay added before checking the status of frq change
1091 * retry not supported by mmc.c(core file)
1093 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1094 udelay(50000); /* wait 50 ms */
1096 if (!(cmd->resp_type & MMC_RSP_PRESENT))
1098 else if (cmd->resp_type & MMC_RSP_136)
1099 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1100 else if (cmd->resp_type & MMC_RSP_BUSY)
1101 flags = RSP_TYPE_LGHT48B;
1103 flags = RSP_TYPE_LGHT48;
1105 /* enable default flags */
1106 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1108 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1110 if (cmd->resp_type & MMC_RSP_CRC)
1111 flags |= CCCE_CHECK;
1112 if (cmd->resp_type & MMC_RSP_OPCODE)
1113 flags |= CICE_CHECK;
1116 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1117 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1118 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1119 data->blocksize = 512;
1120 writel(data->blocksize | (data->blocks << 16),
1123 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1125 if (data->flags & MMC_DATA_READ)
1126 flags |= (DP_DATA | DDIR_READ);
1128 flags |= (DP_DATA | DDIR_WRITE);
1130 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1131 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1132 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1133 omap_hsmmc_prepare_data(mmc, data);
1139 mmc_enable_irq(mmc, cmd);
1141 writel(cmd->cmdarg, &mmc_base->arg);
1142 udelay(20); /* To fix "No status update" error on eMMC */
1143 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1145 start = get_timer(0);
1147 mmc_stat = readl(&mmc_base->stat);
1148 if (get_timer(start) > MAX_RETRY_MS) {
1149 printf("%s : timeout: No status update\n", __func__);
1152 } while (!mmc_stat);
1154 if ((mmc_stat & IE_CTO) != 0) {
1155 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1157 } else if ((mmc_stat & ERRI_MASK) != 0)
1160 if (mmc_stat & CC_MASK) {
1161 writel(CC_MASK, &mmc_base->stat);
1162 if (cmd->resp_type & MMC_RSP_PRESENT) {
1163 if (cmd->resp_type & MMC_RSP_136) {
1164 /* response type 2 */
1165 cmd->response[3] = readl(&mmc_base->rsp10);
1166 cmd->response[2] = readl(&mmc_base->rsp32);
1167 cmd->response[1] = readl(&mmc_base->rsp54);
1168 cmd->response[0] = readl(&mmc_base->rsp76);
1170 /* response types 1, 1b, 3, 4, 5, 6 */
1171 cmd->response[0] = readl(&mmc_base->rsp10);
1175 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1176 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1177 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1180 if (mmc_stat & IE_ADMAE) {
1181 omap_hsmmc_dma_cleanup(mmc);
1185 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
1186 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1187 if (timeout < MAX_RETRY_MS)
1188 timeout = MAX_RETRY_MS;
1190 start = get_timer(0);
1192 mmc_stat = readl(&mmc_base->stat);
1193 if (mmc_stat & TC_MASK) {
1194 writel(readl(&mmc_base->stat) | TC_MASK,
1198 if (get_timer(start) > timeout) {
1199 printf("%s : DMA timeout: No status update\n",
1205 omap_hsmmc_dma_cleanup(mmc);
1210 if (data && (data->flags & MMC_DATA_READ)) {
1211 mmc_read_data(mmc_base, data->dest,
1212 data->blocksize * data->blocks);
1213 } else if (data && (data->flags & MMC_DATA_WRITE)) {
1214 mmc_write_data(mmc_base, data->src,
1215 data->blocksize * data->blocks);
1220 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1222 unsigned int *output_buf = (unsigned int *)buf;
1223 unsigned int mmc_stat;
1229 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1233 ulong start = get_timer(0);
1235 mmc_stat = readl(&mmc_base->stat);
1236 if (get_timer(0) - start > MAX_RETRY_MS) {
1237 printf("%s: timedout waiting for status!\n",
1241 } while (mmc_stat == 0);
1243 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1244 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1246 if ((mmc_stat & ERRI_MASK) != 0)
1249 if (mmc_stat & BRR_MASK) {
1252 writel(readl(&mmc_base->stat) | BRR_MASK,
1254 for (k = 0; k < count; k++) {
1255 *output_buf = readl(&mmc_base->data);
1261 if (mmc_stat & BWR_MASK)
1262 writel(readl(&mmc_base->stat) | BWR_MASK,
1265 if (mmc_stat & TC_MASK) {
1266 writel(readl(&mmc_base->stat) | TC_MASK,
1274 #if CONFIG_IS_ENABLED(MMC_WRITE)
1275 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1278 unsigned int *input_buf = (unsigned int *)buf;
1279 unsigned int mmc_stat;
1283 * Start Polled Write
1285 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1289 ulong start = get_timer(0);
1291 mmc_stat = readl(&mmc_base->stat);
1292 if (get_timer(0) - start > MAX_RETRY_MS) {
1293 printf("%s: timedout waiting for status!\n",
1297 } while (mmc_stat == 0);
1299 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1300 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1302 if ((mmc_stat & ERRI_MASK) != 0)
1305 if (mmc_stat & BWR_MASK) {
1308 writel(readl(&mmc_base->stat) | BWR_MASK,
1310 for (k = 0; k < count; k++) {
1311 writel(*input_buf, &mmc_base->data);
1317 if (mmc_stat & BRR_MASK)
1318 writel(readl(&mmc_base->stat) | BRR_MASK,
1321 if (mmc_stat & TC_MASK) {
1322 writel(readl(&mmc_base->stat) | TC_MASK,
1330 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1336 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1338 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1341 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1343 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1346 static void omap_hsmmc_set_clock(struct mmc *mmc)
1348 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1349 struct hsmmc *mmc_base;
1350 unsigned int dsor = 0;
1353 mmc_base = priv->base_addr;
1354 omap_hsmmc_stop_clock(mmc_base);
1356 /* TODO: Is setting DTO required here? */
1357 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1358 (ICE_STOP | DTO_15THDTO));
1360 if (mmc->clock != 0) {
1361 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1362 if (dsor > CLKD_MAX)
1368 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1369 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1371 start = get_timer(0);
1372 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1373 if (get_timer(0) - start > MAX_RETRY_MS) {
1374 printf("%s: timedout waiting for ics!\n", __func__);
1379 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1380 mmc->clock = priv->clock;
1381 omap_hsmmc_start_clock(mmc_base);
1384 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1386 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1387 struct hsmmc *mmc_base;
1389 mmc_base = priv->base_addr;
1390 /* configue bus width */
1391 switch (mmc->bus_width) {
1393 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1398 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1400 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1406 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1408 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1413 priv->bus_width = mmc->bus_width;
1416 #if !CONFIG_IS_ENABLED(DM_MMC)
1417 static int omap_hsmmc_set_ios(struct mmc *mmc)
1419 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1421 static int omap_hsmmc_set_ios(struct udevice *dev)
1423 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1424 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1425 struct mmc *mmc = upriv->mmc;
1427 struct hsmmc *mmc_base = priv->base_addr;
1430 if (priv->bus_width != mmc->bus_width)
1431 omap_hsmmc_set_bus_width(mmc);
1433 if (priv->clock != mmc->clock)
1434 omap_hsmmc_set_clock(mmc);
1436 if (mmc->clk_disable)
1437 omap_hsmmc_stop_clock(mmc_base);
1439 omap_hsmmc_start_clock(mmc_base);
1441 #if CONFIG_IS_ENABLED(DM_MMC)
1442 if (priv->mode != mmc->selected_mode)
1443 omap_hsmmc_set_timing(mmc);
1445 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1446 if (priv->signal_voltage != mmc->signal_voltage)
1447 ret = omap_hsmmc_set_signal_voltage(mmc);
1453 #ifdef OMAP_HSMMC_USE_GPIO
1454 #if CONFIG_IS_ENABLED(DM_MMC)
1455 static int omap_hsmmc_getcd(struct udevice *dev)
1458 #if CONFIG_IS_ENABLED(DM_GPIO)
1459 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1460 value = dm_gpio_get_value(&priv->cd_gpio);
1462 /* if no CD return as 1 */
1469 static int omap_hsmmc_getwp(struct udevice *dev)
1472 #if CONFIG_IS_ENABLED(DM_GPIO)
1473 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1474 value = dm_gpio_get_value(&priv->wp_gpio);
1476 /* if no WP return as 0 */
1482 static int omap_hsmmc_getcd(struct mmc *mmc)
1484 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1487 /* if no CD return as 1 */
1488 cd_gpio = priv->cd_gpio;
1492 /* NOTE: assumes card detect signal is active-low */
1493 return !gpio_get_value(cd_gpio);
1496 static int omap_hsmmc_getwp(struct mmc *mmc)
1498 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1501 /* if no WP return as 0 */
1502 wp_gpio = priv->wp_gpio;
1506 /* NOTE: assumes write protect signal is active-high */
1507 return gpio_get_value(wp_gpio);
1512 #if CONFIG_IS_ENABLED(DM_MMC)
1513 static const struct dm_mmc_ops omap_hsmmc_ops = {
1514 .send_cmd = omap_hsmmc_send_cmd,
1515 .set_ios = omap_hsmmc_set_ios,
1516 #ifdef OMAP_HSMMC_USE_GPIO
1517 .get_cd = omap_hsmmc_getcd,
1518 .get_wp = omap_hsmmc_getwp,
1520 #ifdef MMC_SUPPORTS_TUNING
1521 .execute_tuning = omap_hsmmc_execute_tuning,
1523 .wait_dat0 = omap_hsmmc_wait_dat0,
1526 static const struct mmc_ops omap_hsmmc_ops = {
1527 .send_cmd = omap_hsmmc_send_cmd,
1528 .set_ios = omap_hsmmc_set_ios,
1529 .init = omap_hsmmc_init_setup,
1530 #ifdef OMAP_HSMMC_USE_GPIO
1531 .getcd = omap_hsmmc_getcd,
1532 .getwp = omap_hsmmc_getwp,
1537 #if !CONFIG_IS_ENABLED(DM_MMC)
1538 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1542 struct omap_hsmmc_data *priv;
1543 struct mmc_config *cfg;
1546 priv = calloc(1, sizeof(*priv));
1550 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1552 switch (dev_index) {
1554 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1556 #ifdef OMAP_HSMMC2_BASE
1558 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1559 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1560 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1561 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1562 defined(CONFIG_HSMMC2_8BIT)
1563 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1564 host_caps_val |= MMC_MODE_8BIT;
1568 #ifdef OMAP_HSMMC3_BASE
1570 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1571 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1572 /* Enable 8-bit interface for eMMC on DRA7XX */
1573 host_caps_val |= MMC_MODE_8BIT;
1578 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1581 #ifdef OMAP_HSMMC_USE_GPIO
1582 /* on error gpio values are set to -1, which is what we want */
1583 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1584 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1589 cfg->name = "OMAP SD/MMC";
1590 cfg->ops = &omap_hsmmc_ops;
1592 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1593 cfg->host_caps = host_caps_val & ~host_caps_mask;
1595 cfg->f_min = 400000;
1600 if (cfg->host_caps & MMC_MODE_HS) {
1601 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1602 cfg->f_max = 52000000;
1604 cfg->f_max = 26000000;
1606 cfg->f_max = 20000000;
1609 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1611 #if defined(CONFIG_OMAP34XX)
1613 * Silicon revs 2.1 and older do not support multiblock transfers.
1615 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1619 mmc = mmc_create(cfg, priv);
1627 #ifdef CONFIG_IODELAY_RECALIBRATION
1628 static struct pad_conf_entry *
1629 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1632 struct pad_conf_entry *padconf;
1634 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1636 debug("failed to allocate memory\n");
1640 while (index < count) {
1641 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1642 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1649 static struct iodelay_cfg_entry *
1650 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1653 struct iodelay_cfg_entry *iodelay;
1655 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1657 debug("failed to allocate memory\n");
1661 while (index < count) {
1662 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1663 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1664 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1671 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1672 const char *name, int *len)
1674 const void *fdt = gd->fdt_blob;
1676 const fdt32_t *pinctrl;
1678 offset = fdt_node_offset_by_phandle(fdt, phandle);
1680 debug("failed to get pinctrl node %s.\n",
1681 fdt_strerror(offset));
1685 pinctrl = fdt_getprop(fdt, offset, name, len);
1687 debug("failed to get property %s\n", name);
1694 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1697 const void *fdt = gd->fdt_blob;
1698 const __be32 *phandle;
1699 int node = dev_of_offset(mmc->dev);
1701 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1703 debug("failed to get property %s\n", prop_name);
1707 return fdt32_to_cpu(*phandle);
1710 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1713 const void *fdt = gd->fdt_blob;
1714 const __be32 *phandle;
1717 int node = dev_of_offset(mmc->dev);
1719 phandle = fdt_getprop(fdt, node, prop_name, &len);
1721 debug("failed to get property %s\n", prop_name);
1725 /* No manual mode iodelay values if count < 2 */
1726 count = len / sizeof(*phandle);
1730 return fdt32_to_cpu(*(phandle + 1));
1733 static struct pad_conf_entry *
1734 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1738 struct pad_conf_entry *padconf;
1740 const fdt32_t *pinctrl;
1742 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1744 return ERR_PTR(-EINVAL);
1746 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1749 return ERR_PTR(-EINVAL);
1751 count = (len / sizeof(*pinctrl)) / 2;
1752 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1754 return ERR_PTR(-EINVAL);
1761 static struct iodelay_cfg_entry *
1762 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1766 struct iodelay_cfg_entry *iodelay;
1768 const fdt32_t *pinctrl;
1770 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1771 /* Not all modes have manual mode iodelay values. So its not fatal */
1775 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1778 return ERR_PTR(-EINVAL);
1780 count = (len / sizeof(*pinctrl)) / 3;
1781 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1783 return ERR_PTR(-EINVAL);
1790 static struct omap_hsmmc_pinctrl_state *
1791 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1796 const void *fdt = gd->fdt_blob;
1797 int node = dev_of_offset(mmc->dev);
1799 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1801 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1802 malloc(sizeof(*pinctrl_state));
1803 if (!pinctrl_state) {
1804 debug("failed to allocate memory\n");
1808 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1810 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1811 goto err_pinctrl_state;
1814 sprintf(prop_name, "pinctrl-%d", index);
1816 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1818 if (IS_ERR(pinctrl_state->padconf))
1819 goto err_pinctrl_state;
1820 pinctrl_state->npads = npads;
1822 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1824 if (IS_ERR(pinctrl_state->iodelay))
1826 pinctrl_state->niodelays = niodelays;
1828 return pinctrl_state;
1831 kfree(pinctrl_state->padconf);
1834 kfree(pinctrl_state);
1838 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
1840 struct omap_hsmmc_pinctrl_state *s = NULL; \
1842 if (!(cfg->host_caps & capmask)) \
1845 if (priv->hw_rev) { \
1846 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1847 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1851 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1853 if (!s && !optional) { \
1854 debug("%s: no pinctrl for %s\n", \
1855 mmc->dev->name, #mode); \
1856 cfg->host_caps &= ~(capmask); \
1858 priv->mode##_pinctrl_state = s; \
1862 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1864 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1865 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1866 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1868 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1871 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1872 if (!default_pinctrl) {
1873 printf("no pinctrl state for default mode\n");
1877 priv->default_pinctrl_state = default_pinctrl;
1879 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1880 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1881 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1882 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1883 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1885 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1886 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1887 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1893 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1894 #ifdef CONFIG_OMAP54XX
1895 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1901 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1903 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1904 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1906 struct mmc_config *cfg = &plat->cfg;
1907 #ifdef CONFIG_OMAP54XX
1908 const struct mmc_platform_fixups *fixups;
1910 const void *fdt = gd->fdt_blob;
1911 int node = dev_of_offset(dev);
1914 plat->base_addr = map_physmem(dev_read_addr(dev),
1915 sizeof(struct hsmmc *),
1918 ret = mmc_of_parse(dev, cfg);
1923 cfg->f_max = 52000000;
1924 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1925 cfg->f_min = 400000;
1926 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1927 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1928 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1929 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1930 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1931 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1933 plat->controller_flags |= of_data->controller_flags;
1935 #ifdef CONFIG_OMAP54XX
1936 fixups = platform_fixups_mmc(dev_read_addr(dev));
1938 plat->hw_rev = fixups->hw_rev;
1939 cfg->host_caps &= ~fixups->unsupported_caps;
1940 cfg->f_max = fixups->max_freq;
1950 static int omap_hsmmc_bind(struct udevice *dev)
1952 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1953 plat->mmc = calloc(1, sizeof(struct mmc));
1954 return mmc_bind(dev, plat->mmc, &plat->cfg);
1957 static int omap_hsmmc_probe(struct udevice *dev)
1959 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1960 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1961 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1962 struct mmc_config *cfg = &plat->cfg;
1964 #ifdef CONFIG_IODELAY_RECALIBRATION
1968 cfg->name = "OMAP SD/MMC";
1969 priv->base_addr = plat->base_addr;
1970 priv->controller_flags = plat->controller_flags;
1971 priv->hw_rev = plat->hw_rev;
1976 mmc = mmc_create(cfg, priv);
1980 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1981 device_get_supply_regulator(dev, "pbias-supply",
1982 &priv->pbias_supply);
1984 #if defined(OMAP_HSMMC_USE_GPIO)
1985 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1986 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1987 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1994 #ifdef CONFIG_IODELAY_RECALIBRATION
1995 ret = omap_hsmmc_get_pinctrl_state(mmc);
1997 * disable high speed modes for the platforms that require IO delay
1998 * and for which we don't have this information
2001 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
2002 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2003 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2008 return omap_hsmmc_init_setup(mmc);
2011 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2013 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2014 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2017 static const struct udevice_id omap_hsmmc_ids[] = {
2018 { .compatible = "ti,omap3-hsmmc" },
2019 { .compatible = "ti,omap4-hsmmc" },
2020 { .compatible = "ti,am33xx-hsmmc" },
2021 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2026 U_BOOT_DRIVER(omap_hsmmc) = {
2027 .name = "omap_hsmmc",
2029 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2030 .of_match = omap_hsmmc_ids,
2031 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2032 .plat_auto = sizeof(struct omap_hsmmc_plat),
2035 .bind = omap_hsmmc_bind,
2037 .ops = &omap_hsmmc_ops,
2038 .probe = omap_hsmmc_probe,
2039 .priv_auto = sizeof(struct omap_hsmmc_data),
2040 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2041 .flags = DM_FLAG_PRE_RELOC,