3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
37 #include <asm/cache.h>
39 #include <asm/arch/mmc_host_def.h>
40 #ifdef CONFIG_OMAP54XX
41 #include <asm/arch/mux_dra7xx.h>
42 #include <asm/arch/dra7xx_iodelay.h>
44 #if !defined(CONFIG_SOC_KEYSTONE)
46 #include <asm/arch/sys_proto.h>
48 #ifdef CONFIG_MMC_OMAP36XX_PINS
49 #include <asm/arch/mux.h>
52 #include <dm/devres.h>
53 #include <linux/delay.h>
54 #include <linux/err.h>
55 #include <power/regulator.h>
58 DECLARE_GLOBAL_DATA_PTR;
60 /* simplify defines to OMAP_HSMMC_USE_GPIO */
61 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
62 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
63 #define OMAP_HSMMC_USE_GPIO
65 #undef OMAP_HSMMC_USE_GPIO
68 /* common definitions for all OMAPs */
69 #define SYSCTL_SRC (1 << 25)
70 #define SYSCTL_SRD (1 << 26)
72 #ifdef CONFIG_IODELAY_RECALIBRATION
73 struct omap_hsmmc_pinctrl_state {
74 struct pad_conf_entry *padconf;
76 struct iodelay_cfg_entry *iodelay;
81 struct omap_hsmmc_data {
82 struct hsmmc *base_addr;
83 #if !CONFIG_IS_ENABLED(DM_MMC)
84 struct mmc_config cfg;
89 #ifdef OMAP_HSMMC_USE_GPIO
90 #if CONFIG_IS_ENABLED(DM_MMC)
91 struct gpio_desc cd_gpio; /* Change Detect GPIO */
92 struct gpio_desc wp_gpio; /* Write Protect GPIO */
98 #if CONFIG_IS_ENABLED(DM_MMC)
102 #ifdef CONFIG_MMC_OMAP_HS_ADMA
103 struct omap_hsmmc_adma_desc *adma_desc_table;
107 struct udevice *pbias_supply;
109 #ifdef CONFIG_IODELAY_RECALIBRATION
110 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
111 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
112 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
113 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
114 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
115 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
116 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
117 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
118 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
122 struct omap_mmc_of_data {
126 #ifdef CONFIG_MMC_OMAP_HS_ADMA
127 struct omap_hsmmc_adma_desc {
134 #define ADMA_MAX_LEN 63488
136 /* Decriptor table defines */
137 #define ADMA_DESC_ATTR_VALID BIT(0)
138 #define ADMA_DESC_ATTR_END BIT(1)
139 #define ADMA_DESC_ATTR_INT BIT(2)
140 #define ADMA_DESC_ATTR_ACT1 BIT(4)
141 #define ADMA_DESC_ATTR_ACT2 BIT(5)
143 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
144 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
147 /* If we fail after 1 second wait, something is really bad */
148 #define MAX_RETRY_MS 1000
149 #define MMC_TIMEOUT_MS 20
151 /* DMA transfers can take a long time if a lot a data is transferred.
152 * The timeout must take in account the amount of data. Let's assume
153 * that the time will never exceed 333 ms per MB (in other word we assume
154 * that the bandwidth is always above 3MB/s).
156 #define DMA_TIMEOUT_PER_MB 333
157 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
158 #define OMAP_HSMMC_NO_1_8_V BIT(1)
159 #define OMAP_HSMMC_USE_ADMA BIT(2)
160 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
162 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
163 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
165 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
166 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
167 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
169 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
171 #if CONFIG_IS_ENABLED(DM_MMC)
172 return dev_get_priv(mmc->dev);
174 return (struct omap_hsmmc_data *)mmc->priv;
177 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
179 #if CONFIG_IS_ENABLED(DM_MMC)
180 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
183 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
187 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
188 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
192 #if !CONFIG_IS_ENABLED(DM_GPIO)
193 if (!gpio_is_valid(gpio))
196 ret = gpio_request(gpio, label);
200 ret = gpio_direction_input(gpio);
208 static unsigned char mmc_board_init(struct mmc *mmc)
210 #if defined(CONFIG_OMAP34XX)
211 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
212 t2_t *t2_base = (t2_t *)T2_BASE;
213 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
215 #ifdef CONFIG_MMC_OMAP36XX_PINS
216 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
219 pbias_lite = readl(&t2_base->pbias_lite);
220 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
221 #ifdef CONFIG_TARGET_OMAP3_CAIRO
222 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
223 pbias_lite &= ~PBIASLITEVMODE0;
225 #ifdef CONFIG_TARGET_OMAP3_LOGIC
226 /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
227 pbias_lite &= ~PBIASLITEVMODE1;
229 #ifdef CONFIG_MMC_OMAP36XX_PINS
230 if (get_cpu_family() == CPU_OMAP36XX) {
231 /* Disable extended drain IO before changing PBIAS */
232 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
233 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
236 writel(pbias_lite, &t2_base->pbias_lite);
238 writel(pbias_lite | PBIASLITEPWRDNZ1 |
239 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
240 &t2_base->pbias_lite);
242 #ifdef CONFIG_MMC_OMAP36XX_PINS
243 if (get_cpu_family() == CPU_OMAP36XX)
244 /* Enable extended drain IO after changing PBIAS */
246 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
247 OMAP34XX_CTRL_WKUP_CTRL);
249 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
252 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
255 /* Change from default of 52MHz to 26MHz if necessary */
256 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
257 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
258 &t2_base->ctl_prog_io1);
260 writel(readl(&prcm_base->fclken1_core) |
261 EN_MMC1 | EN_MMC2 | EN_MMC3,
262 &prcm_base->fclken1_core);
264 writel(readl(&prcm_base->iclken1_core) |
265 EN_MMC1 | EN_MMC2 | EN_MMC3,
266 &prcm_base->iclken1_core);
269 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
270 !CONFIG_IS_ENABLED(DM_REGULATOR)
271 /* PBIAS config needed for MMC1 only */
272 if (mmc_get_blk_desc(mmc)->devnum == 0)
273 vmmc_pbias_config(LDO_VOLT_3V3);
279 void mmc_init_stream(struct hsmmc *mmc_base)
283 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
285 writel(MMC_CMD0, &mmc_base->cmd);
286 start = get_timer(0);
287 while (!(readl(&mmc_base->stat) & CC_MASK)) {
288 if (get_timer(0) - start > MAX_RETRY_MS) {
289 printf("%s: timedout waiting for cc!\n", __func__);
293 writel(CC_MASK, &mmc_base->stat)
295 writel(MMC_CMD0, &mmc_base->cmd)
297 start = get_timer(0);
298 while (!(readl(&mmc_base->stat) & CC_MASK)) {
299 if (get_timer(0) - start > MAX_RETRY_MS) {
300 printf("%s: timedout waiting for cc2!\n", __func__);
304 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
307 #if CONFIG_IS_ENABLED(DM_MMC)
308 #ifdef CONFIG_IODELAY_RECALIBRATION
309 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
311 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
312 struct omap_hsmmc_pinctrl_state *pinctrl_state;
314 switch (priv->mode) {
316 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
319 pinctrl_state = priv->sdr104_pinctrl_state;
322 pinctrl_state = priv->sdr50_pinctrl_state;
325 pinctrl_state = priv->ddr50_pinctrl_state;
328 pinctrl_state = priv->sdr25_pinctrl_state;
331 pinctrl_state = priv->sdr12_pinctrl_state;
336 pinctrl_state = priv->hs_pinctrl_state;
339 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
341 pinctrl_state = priv->default_pinctrl_state;
346 pinctrl_state = priv->default_pinctrl_state;
348 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
349 if (pinctrl_state->iodelay)
350 late_recalibrate_iodelay(pinctrl_state->padconf,
351 pinctrl_state->npads,
352 pinctrl_state->iodelay,
353 pinctrl_state->niodelays);
355 do_set_mux32((*ctrl)->control_padconf_core_base,
356 pinctrl_state->padconf,
357 pinctrl_state->npads);
361 static void omap_hsmmc_set_timing(struct mmc *mmc)
364 struct hsmmc *mmc_base;
365 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
367 mmc_base = priv->base_addr;
369 omap_hsmmc_stop_clock(mmc_base);
370 val = readl(&mmc_base->ac12);
371 val &= ~AC12_UHSMC_MASK;
372 priv->mode = mmc->selected_mode;
374 if (mmc_is_mode_ddr(priv->mode))
375 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
377 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
379 switch (priv->mode) {
382 val |= AC12_UHSMC_SDR104;
385 val |= AC12_UHSMC_SDR50;
389 val |= AC12_UHSMC_DDR50;
394 val |= AC12_UHSMC_SDR25;
399 val |= AC12_UHSMC_SDR12;
402 val |= AC12_UHSMC_RES;
405 writel(val, &mmc_base->ac12);
407 #ifdef CONFIG_IODELAY_RECALIBRATION
408 omap_hsmmc_io_recalibrate(mmc);
410 omap_hsmmc_start_clock(mmc_base);
413 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
415 struct hsmmc *mmc_base;
416 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
419 mmc_base = priv->base_addr;
421 hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
422 ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
424 switch (signal_voltage) {
425 case MMC_SIGNAL_VOLTAGE_330:
428 case MMC_SIGNAL_VOLTAGE_180:
430 ac12 |= AC12_V1V8_SIGEN;
434 writel(hctl, &mmc_base->hctl);
435 writel(ac12, &mmc_base->ac12);
438 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
440 int ret = -ETIMEDOUT;
443 bool target_dat0_high = !!state;
444 struct omap_hsmmc_data *priv = dev_get_priv(dev);
445 struct hsmmc *mmc_base = priv->base_addr;
447 con = readl(&mmc_base->con);
448 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
450 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
451 while (timeout_us--) {
452 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
453 if (dat0_high == target_dat0_high) {
459 writel(con, &mmc_base->con);
464 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
465 #if CONFIG_IS_ENABLED(DM_REGULATOR)
466 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
471 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
473 if (!mmc->vqmmc_supply)
477 ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
481 /* Turn off IO voltage */
482 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
485 /* Program a new IO voltage value */
486 ret = regulator_set_value(mmc->vqmmc_supply, uV);
489 /* Turn on IO voltage */
490 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
494 /* Program PBIAS voltage*/
495 ret = regulator_set_value(priv->pbias_supply, uV);
496 if (ret && ret != -ENOSYS)
499 ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
507 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
509 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
510 struct hsmmc *mmc_base = priv->base_addr;
511 int mv = mmc_voltage_to_mv(mmc->signal_voltage);
513 __maybe_unused u8 palmas_ldo_volt;
519 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
521 capa_mask = VS33_3V3SUP;
522 palmas_ldo_volt = LDO_VOLT_3V3;
523 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
524 capa_mask = VS18_1V8SUP;
525 palmas_ldo_volt = LDO_VOLT_1V8;
530 val = readl(&mmc_base->capa);
531 if (!(val & capa_mask))
534 priv->signal_voltage = mmc->signal_voltage;
536 omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
538 #if CONFIG_IS_ENABLED(DM_REGULATOR)
539 return omap_hsmmc_set_io_regulator(mmc, mv);
540 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
541 defined(CONFIG_PALMAS_POWER)
542 if (mmc_get_blk_desc(mmc)->devnum == 0)
543 vmmc_pbias_config(palmas_ldo_volt);
551 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
553 struct hsmmc *mmc_base;
554 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
557 mmc_base = priv->base_addr;
558 val = readl(&mmc_base->capa);
560 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
561 val |= (VS33_3V3SUP | VS18_1V8SUP);
562 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
570 writel(val, &mmc_base->capa);
575 #ifdef MMC_SUPPORTS_TUNING
576 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
578 struct hsmmc *mmc_base;
579 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
582 mmc_base = priv->base_addr;
583 val = readl(&mmc_base->ac12);
584 val &= ~(AC12_SCLK_SEL);
585 writel(val, &mmc_base->ac12);
587 val = readl(&mmc_base->dll);
588 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
589 writel(val, &mmc_base->dll);
592 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
595 struct hsmmc *mmc_base;
596 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
599 mmc_base = priv->base_addr;
600 val = readl(&mmc_base->dll);
601 val |= DLL_FORCE_VALUE;
602 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
603 val |= (count << DLL_FORCE_SR_C_SHIFT);
604 writel(val, &mmc_base->dll);
607 writel(val, &mmc_base->dll);
608 for (i = 0; i < 1000; i++) {
609 if (readl(&mmc_base->dll) & DLL_CALIB)
613 writel(val, &mmc_base->dll);
616 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
618 struct omap_hsmmc_data *priv = dev_get_priv(dev);
619 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
620 struct mmc *mmc = upriv->mmc;
621 struct hsmmc *mmc_base;
623 u8 cur_match, prev_match = 0;
626 u32 start_window = 0, max_window = 0;
627 u32 length = 0, max_len = 0;
628 bool single_point_failure = false;
629 struct udevice *thermal_dev;
633 mmc_base = priv->base_addr;
634 val = readl(&mmc_base->capa2);
636 /* clock tuning is not needed for upto 52MHz */
637 if (!((mmc->selected_mode == MMC_HS_200) ||
638 (mmc->selected_mode == UHS_SDR104) ||
639 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
642 ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
644 printf("Couldn't get thermal device for tuning\n");
647 ret = thermal_get_temp(thermal_dev, &temperature);
649 printf("Couldn't get temperature for tuning\n");
652 val = readl(&mmc_base->dll);
654 writel(val, &mmc_base->dll);
657 * Stage 1: Search for a maximum pass window ignoring any
658 * any single point failures. If the tuning value ends up
659 * near it, move away from it in stage 2 below
661 while (phase_delay <= MAX_PHASE_DELAY) {
662 omap_hsmmc_set_dll(mmc, phase_delay);
664 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
669 } else if (single_point_failure) {
670 /* ignore single point failure */
672 single_point_failure = false;
674 start_window = phase_delay;
678 single_point_failure = prev_match;
681 if (length > max_len) {
682 max_window = start_window;
686 prev_match = cur_match;
695 val = readl(&mmc_base->ac12);
696 if (!(val & AC12_SCLK_SEL)) {
701 * Assign tuning value as a ratio of maximum pass window based
704 if (temperature < -20000)
705 phase_delay = min(max_window + 4 * max_len - 24,
707 DIV_ROUND_UP(13 * max_len, 16) * 4);
708 else if (temperature < 20000)
709 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
710 else if (temperature < 40000)
711 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
712 else if (temperature < 70000)
713 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
714 else if (temperature < 90000)
715 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
716 else if (temperature < 120000)
717 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
719 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
722 * Stage 2: Search for a single point failure near the chosen tuning
723 * value in two steps. First in the +3 to +10 range and then in the
724 * +2 to -10 range. If found, move away from it in the appropriate
725 * direction by the appropriate amount depending on the temperature.
727 for (i = 3; i <= 10; i++) {
728 omap_hsmmc_set_dll(mmc, phase_delay + i);
729 if (mmc_send_tuning(mmc, opcode, NULL)) {
730 if (temperature < 10000)
731 phase_delay += i + 6;
732 else if (temperature < 20000)
733 phase_delay += i - 12;
734 else if (temperature < 70000)
735 phase_delay += i - 8;
736 else if (temperature < 90000)
737 phase_delay += i - 6;
739 phase_delay += i - 6;
741 goto single_failure_found;
745 for (i = 2; i >= -10; i--) {
746 omap_hsmmc_set_dll(mmc, phase_delay + i);
747 if (mmc_send_tuning(mmc, opcode, NULL)) {
748 if (temperature < 10000)
749 phase_delay += i + 12;
750 else if (temperature < 20000)
751 phase_delay += i + 8;
752 else if (temperature < 70000)
753 phase_delay += i + 8;
754 else if (temperature < 90000)
755 phase_delay += i + 10;
757 phase_delay += i + 12;
759 goto single_failure_found;
763 single_failure_found:
765 omap_hsmmc_set_dll(mmc, phase_delay);
767 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
768 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
774 omap_hsmmc_disable_tuning(mmc);
775 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
776 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
783 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
785 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
786 struct hsmmc *mmc_base = priv->base_addr;
787 u32 irq_mask = INT_EN_MASK;
790 * TODO: Errata i802 indicates only DCRC interrupts can occur during
791 * tuning procedure and DCRC should be disabled. But see occurences
792 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
793 * interrupts occur along with BRR, so the data is actually in the
794 * buffer. It has to be debugged why these interrutps occur
796 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
797 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
799 writel(irq_mask, &mmc_base->ie);
802 static int omap_hsmmc_init_setup(struct mmc *mmc)
804 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
805 struct hsmmc *mmc_base;
806 unsigned int reg_val;
810 mmc_base = priv->base_addr;
813 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
814 &mmc_base->sysconfig);
815 start = get_timer(0);
816 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
817 if (get_timer(0) - start > MAX_RETRY_MS) {
818 printf("%s: timedout waiting for cc2!\n", __func__);
822 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
823 start = get_timer(0);
824 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
825 if (get_timer(0) - start > MAX_RETRY_MS) {
826 printf("%s: timedout waiting for softresetall!\n",
831 #ifdef CONFIG_MMC_OMAP_HS_ADMA
832 reg_val = readl(&mmc_base->hl_hwinfo);
833 if (reg_val & MADMA_EN)
834 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
837 #if CONFIG_IS_ENABLED(DM_MMC)
838 reg_val = omap_hsmmc_set_capabilities(mmc);
839 omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
840 MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
842 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
843 writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
847 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
849 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
850 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
851 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
854 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
855 (ICE_STOP | DTO_15THDTO));
856 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
857 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
858 start = get_timer(0);
859 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
860 if (get_timer(0) - start > MAX_RETRY_MS) {
861 printf("%s: timedout waiting for ics!\n", __func__);
865 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
867 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
869 mmc_enable_irq(mmc, NULL);
871 #if !CONFIG_IS_ENABLED(DM_MMC)
872 mmc_init_stream(mmc_base);
879 * MMC controller internal finite state machine reset
881 * Used to reset command or data internal state machines, using respectively
882 * SRC or SRD bit of SYSCTL register
884 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
888 mmc_reg_out(&mmc_base->sysctl, bit, bit);
891 * CMD(DAT) lines reset procedures are slightly different
892 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
893 * According to OMAP3 TRM:
894 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
896 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
897 * procedure steps must be as follows:
898 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
899 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
900 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
901 * 3. Wait until the SRC (SRD) bit returns to 0x0
902 * (reset procedure is completed).
904 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
905 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
906 if (!(readl(&mmc_base->sysctl) & bit)) {
907 start = get_timer(0);
908 while (!(readl(&mmc_base->sysctl) & bit)) {
909 if (get_timer(0) - start > MMC_TIMEOUT_MS)
914 start = get_timer(0);
915 while ((readl(&mmc_base->sysctl) & bit) != 0) {
916 if (get_timer(0) - start > MAX_RETRY_MS) {
917 printf("%s: timedout waiting for sysctl %x to clear\n",
924 #ifdef CONFIG_MMC_OMAP_HS_ADMA
925 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
927 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
928 struct omap_hsmmc_adma_desc *desc;
931 desc = &priv->adma_desc_table[priv->desc_slot];
933 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
937 attr |= ADMA_DESC_ATTR_END;
940 desc->addr = (u32)buf;
945 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
946 struct mmc_data *data)
948 uint total_len = data->blocksize * data->blocks;
949 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
950 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
955 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
956 memalign(ARCH_DMA_MINALIGN, desc_count *
957 sizeof(struct omap_hsmmc_adma_desc));
959 if (data->flags & MMC_DATA_READ)
962 buf = (char *)data->src;
965 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
967 total_len -= ADMA_MAX_LEN;
970 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
972 flush_dcache_range((long)priv->adma_desc_table,
973 (long)priv->adma_desc_table +
975 sizeof(struct omap_hsmmc_adma_desc),
979 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
981 struct hsmmc *mmc_base;
982 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
986 mmc_base = priv->base_addr;
987 omap_hsmmc_prepare_adma_table(mmc, data);
989 if (data->flags & MMC_DATA_READ)
992 buf = (char *)data->src;
994 val = readl(&mmc_base->hctl);
996 writel(val, &mmc_base->hctl);
998 val = readl(&mmc_base->con);
1000 writel(val, &mmc_base->con);
1002 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1004 flush_dcache_range((u32)buf,
1006 ROUND(data->blocksize * data->blocks,
1007 ARCH_DMA_MINALIGN));
1010 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1012 struct hsmmc *mmc_base;
1013 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1016 mmc_base = priv->base_addr;
1018 val = readl(&mmc_base->con);
1020 writel(val, &mmc_base->con);
1022 val = readl(&mmc_base->hctl);
1024 writel(val, &mmc_base->hctl);
1026 kfree(priv->adma_desc_table);
1029 #define omap_hsmmc_adma_desc
1030 #define omap_hsmmc_prepare_adma_table
1031 #define omap_hsmmc_prepare_data
1032 #define omap_hsmmc_dma_cleanup
1035 #if !CONFIG_IS_ENABLED(DM_MMC)
1036 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1037 struct mmc_data *data)
1039 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1041 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1042 struct mmc_data *data)
1044 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1045 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1046 struct mmc *mmc = upriv->mmc;
1048 struct hsmmc *mmc_base;
1049 unsigned int flags, mmc_stat;
1051 priv->last_cmd = cmd->cmdidx;
1053 mmc_base = priv->base_addr;
1055 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1058 start = get_timer(0);
1059 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1060 if (get_timer(0) - start > MAX_RETRY_MS) {
1061 printf("%s: timedout waiting on cmd inhibit to clear\n",
1063 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1064 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1068 writel(0xFFFFFFFF, &mmc_base->stat);
1069 if (readl(&mmc_base->stat)) {
1070 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1071 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1076 * CMDIDX[13:8] : Command index
1077 * DATAPRNT[5] : Data Present Select
1078 * ENCMDIDX[4] : Command Index Check Enable
1079 * ENCMDCRC[3] : Command CRC Check Enable
1084 * 11 = Length 48 Check busy after response
1086 /* Delay added before checking the status of frq change
1087 * retry not supported by mmc.c(core file)
1089 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1090 udelay(50000); /* wait 50 ms */
1092 if (!(cmd->resp_type & MMC_RSP_PRESENT))
1094 else if (cmd->resp_type & MMC_RSP_136)
1095 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1096 else if (cmd->resp_type & MMC_RSP_BUSY)
1097 flags = RSP_TYPE_LGHT48B;
1099 flags = RSP_TYPE_LGHT48;
1101 /* enable default flags */
1102 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1104 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1106 if (cmd->resp_type & MMC_RSP_CRC)
1107 flags |= CCCE_CHECK;
1108 if (cmd->resp_type & MMC_RSP_OPCODE)
1109 flags |= CICE_CHECK;
1112 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1113 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1114 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1115 data->blocksize = 512;
1116 writel(data->blocksize | (data->blocks << 16),
1119 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1121 if (data->flags & MMC_DATA_READ)
1122 flags |= (DP_DATA | DDIR_READ);
1124 flags |= (DP_DATA | DDIR_WRITE);
1126 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1127 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1128 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1129 omap_hsmmc_prepare_data(mmc, data);
1135 mmc_enable_irq(mmc, cmd);
1137 writel(cmd->cmdarg, &mmc_base->arg);
1138 udelay(20); /* To fix "No status update" error on eMMC */
1139 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1141 start = get_timer(0);
1143 mmc_stat = readl(&mmc_base->stat);
1144 if (get_timer(start) > MAX_RETRY_MS) {
1145 printf("%s : timeout: No status update\n", __func__);
1148 } while (!mmc_stat);
1150 if ((mmc_stat & IE_CTO) != 0) {
1151 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1153 } else if ((mmc_stat & ERRI_MASK) != 0)
1156 if (mmc_stat & CC_MASK) {
1157 writel(CC_MASK, &mmc_base->stat);
1158 if (cmd->resp_type & MMC_RSP_PRESENT) {
1159 if (cmd->resp_type & MMC_RSP_136) {
1160 /* response type 2 */
1161 cmd->response[3] = readl(&mmc_base->rsp10);
1162 cmd->response[2] = readl(&mmc_base->rsp32);
1163 cmd->response[1] = readl(&mmc_base->rsp54);
1164 cmd->response[0] = readl(&mmc_base->rsp76);
1166 /* response types 1, 1b, 3, 4, 5, 6 */
1167 cmd->response[0] = readl(&mmc_base->rsp10);
1171 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1172 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1173 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1176 if (mmc_stat & IE_ADMAE) {
1177 omap_hsmmc_dma_cleanup(mmc);
1181 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
1182 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1183 if (timeout < MAX_RETRY_MS)
1184 timeout = MAX_RETRY_MS;
1186 start = get_timer(0);
1188 mmc_stat = readl(&mmc_base->stat);
1189 if (mmc_stat & TC_MASK) {
1190 writel(readl(&mmc_base->stat) | TC_MASK,
1194 if (get_timer(start) > timeout) {
1195 printf("%s : DMA timeout: No status update\n",
1201 omap_hsmmc_dma_cleanup(mmc);
1206 if (data && (data->flags & MMC_DATA_READ)) {
1207 mmc_read_data(mmc_base, data->dest,
1208 data->blocksize * data->blocks);
1209 } else if (data && (data->flags & MMC_DATA_WRITE)) {
1210 mmc_write_data(mmc_base, data->src,
1211 data->blocksize * data->blocks);
1216 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1218 unsigned int *output_buf = (unsigned int *)buf;
1219 unsigned int mmc_stat;
1225 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1229 ulong start = get_timer(0);
1231 mmc_stat = readl(&mmc_base->stat);
1232 if (get_timer(0) - start > MAX_RETRY_MS) {
1233 printf("%s: timedout waiting for status!\n",
1237 } while (mmc_stat == 0);
1239 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1240 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1242 if ((mmc_stat & ERRI_MASK) != 0)
1245 if (mmc_stat & BRR_MASK) {
1248 writel(readl(&mmc_base->stat) | BRR_MASK,
1250 for (k = 0; k < count; k++) {
1251 *output_buf = readl(&mmc_base->data);
1257 if (mmc_stat & BWR_MASK)
1258 writel(readl(&mmc_base->stat) | BWR_MASK,
1261 if (mmc_stat & TC_MASK) {
1262 writel(readl(&mmc_base->stat) | TC_MASK,
1270 #if CONFIG_IS_ENABLED(MMC_WRITE)
1271 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1274 unsigned int *input_buf = (unsigned int *)buf;
1275 unsigned int mmc_stat;
1279 * Start Polled Write
1281 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1285 ulong start = get_timer(0);
1287 mmc_stat = readl(&mmc_base->stat);
1288 if (get_timer(0) - start > MAX_RETRY_MS) {
1289 printf("%s: timedout waiting for status!\n",
1293 } while (mmc_stat == 0);
1295 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1296 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1298 if ((mmc_stat & ERRI_MASK) != 0)
1301 if (mmc_stat & BWR_MASK) {
1304 writel(readl(&mmc_base->stat) | BWR_MASK,
1306 for (k = 0; k < count; k++) {
1307 writel(*input_buf, &mmc_base->data);
1313 if (mmc_stat & BRR_MASK)
1314 writel(readl(&mmc_base->stat) | BRR_MASK,
1317 if (mmc_stat & TC_MASK) {
1318 writel(readl(&mmc_base->stat) | TC_MASK,
1326 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1332 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1334 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1337 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1339 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1342 static void omap_hsmmc_set_clock(struct mmc *mmc)
1344 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1345 struct hsmmc *mmc_base;
1346 unsigned int dsor = 0;
1349 mmc_base = priv->base_addr;
1350 omap_hsmmc_stop_clock(mmc_base);
1352 /* TODO: Is setting DTO required here? */
1353 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1354 (ICE_STOP | DTO_15THDTO));
1356 if (mmc->clock != 0) {
1357 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1358 if (dsor > CLKD_MAX)
1364 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1365 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1367 start = get_timer(0);
1368 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1369 if (get_timer(0) - start > MAX_RETRY_MS) {
1370 printf("%s: timedout waiting for ics!\n", __func__);
1375 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1376 mmc->clock = priv->clock;
1377 omap_hsmmc_start_clock(mmc_base);
1380 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1382 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1383 struct hsmmc *mmc_base;
1385 mmc_base = priv->base_addr;
1386 /* configue bus width */
1387 switch (mmc->bus_width) {
1389 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1394 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1396 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1402 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1404 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1409 priv->bus_width = mmc->bus_width;
1412 #if !CONFIG_IS_ENABLED(DM_MMC)
1413 static int omap_hsmmc_set_ios(struct mmc *mmc)
1415 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1417 static int omap_hsmmc_set_ios(struct udevice *dev)
1419 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1420 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1421 struct mmc *mmc = upriv->mmc;
1423 struct hsmmc *mmc_base = priv->base_addr;
1426 if (priv->bus_width != mmc->bus_width)
1427 omap_hsmmc_set_bus_width(mmc);
1429 if (priv->clock != mmc->clock)
1430 omap_hsmmc_set_clock(mmc);
1432 if (mmc->clk_disable)
1433 omap_hsmmc_stop_clock(mmc_base);
1435 omap_hsmmc_start_clock(mmc_base);
1437 #if CONFIG_IS_ENABLED(DM_MMC)
1438 if (priv->mode != mmc->selected_mode)
1439 omap_hsmmc_set_timing(mmc);
1441 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1442 if (priv->signal_voltage != mmc->signal_voltage)
1443 ret = omap_hsmmc_set_signal_voltage(mmc);
1449 #ifdef OMAP_HSMMC_USE_GPIO
1450 #if CONFIG_IS_ENABLED(DM_MMC)
1451 static int omap_hsmmc_getcd(struct udevice *dev)
1454 #if CONFIG_IS_ENABLED(DM_GPIO)
1455 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1456 value = dm_gpio_get_value(&priv->cd_gpio);
1458 /* if no CD return as 1 */
1465 static int omap_hsmmc_getwp(struct udevice *dev)
1468 #if CONFIG_IS_ENABLED(DM_GPIO)
1469 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1470 value = dm_gpio_get_value(&priv->wp_gpio);
1472 /* if no WP return as 0 */
1478 static int omap_hsmmc_getcd(struct mmc *mmc)
1480 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1483 /* if no CD return as 1 */
1484 cd_gpio = priv->cd_gpio;
1488 /* NOTE: assumes card detect signal is active-low */
1489 return !gpio_get_value(cd_gpio);
1492 static int omap_hsmmc_getwp(struct mmc *mmc)
1494 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1497 /* if no WP return as 0 */
1498 wp_gpio = priv->wp_gpio;
1502 /* NOTE: assumes write protect signal is active-high */
1503 return gpio_get_value(wp_gpio);
1508 #if CONFIG_IS_ENABLED(DM_MMC)
1509 static const struct dm_mmc_ops omap_hsmmc_ops = {
1510 .send_cmd = omap_hsmmc_send_cmd,
1511 .set_ios = omap_hsmmc_set_ios,
1512 #ifdef OMAP_HSMMC_USE_GPIO
1513 .get_cd = omap_hsmmc_getcd,
1514 .get_wp = omap_hsmmc_getwp,
1516 #ifdef MMC_SUPPORTS_TUNING
1517 .execute_tuning = omap_hsmmc_execute_tuning,
1519 .wait_dat0 = omap_hsmmc_wait_dat0,
1522 static const struct mmc_ops omap_hsmmc_ops = {
1523 .send_cmd = omap_hsmmc_send_cmd,
1524 .set_ios = omap_hsmmc_set_ios,
1525 .init = omap_hsmmc_init_setup,
1526 #ifdef OMAP_HSMMC_USE_GPIO
1527 .getcd = omap_hsmmc_getcd,
1528 .getwp = omap_hsmmc_getwp,
1533 #if !CONFIG_IS_ENABLED(DM_MMC)
1534 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1538 struct omap_hsmmc_data *priv;
1539 struct mmc_config *cfg;
1542 priv = calloc(1, sizeof(*priv));
1546 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1548 switch (dev_index) {
1550 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1552 #ifdef OMAP_HSMMC2_BASE
1554 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1555 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1556 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1557 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1558 defined(CONFIG_HSMMC2_8BIT)
1559 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1560 host_caps_val |= MMC_MODE_8BIT;
1564 #ifdef OMAP_HSMMC3_BASE
1566 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1567 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1568 /* Enable 8-bit interface for eMMC on DRA7XX */
1569 host_caps_val |= MMC_MODE_8BIT;
1574 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1577 #ifdef OMAP_HSMMC_USE_GPIO
1578 /* on error gpio values are set to -1, which is what we want */
1579 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1580 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1585 cfg->name = "OMAP SD/MMC";
1586 cfg->ops = &omap_hsmmc_ops;
1588 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1589 cfg->host_caps = host_caps_val & ~host_caps_mask;
1591 cfg->f_min = 400000;
1596 if (cfg->host_caps & MMC_MODE_HS) {
1597 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1598 cfg->f_max = 52000000;
1600 cfg->f_max = 26000000;
1602 cfg->f_max = 20000000;
1605 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1607 #if defined(CONFIG_OMAP34XX)
1609 * Silicon revs 2.1 and older do not support multiblock transfers.
1611 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1615 mmc = mmc_create(cfg, priv);
1623 #ifdef CONFIG_IODELAY_RECALIBRATION
1624 static struct pad_conf_entry *
1625 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1628 struct pad_conf_entry *padconf;
1630 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1632 debug("failed to allocate memory\n");
1636 while (index < count) {
1637 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1638 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1645 static struct iodelay_cfg_entry *
1646 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1649 struct iodelay_cfg_entry *iodelay;
1651 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1653 debug("failed to allocate memory\n");
1657 while (index < count) {
1658 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1659 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1660 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1667 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1668 const char *name, int *len)
1670 const void *fdt = gd->fdt_blob;
1672 const fdt32_t *pinctrl;
1674 offset = fdt_node_offset_by_phandle(fdt, phandle);
1676 debug("failed to get pinctrl node %s.\n",
1677 fdt_strerror(offset));
1681 pinctrl = fdt_getprop(fdt, offset, name, len);
1683 debug("failed to get property %s\n", name);
1690 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1693 const void *fdt = gd->fdt_blob;
1694 const __be32 *phandle;
1695 int node = dev_of_offset(mmc->dev);
1697 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1699 debug("failed to get property %s\n", prop_name);
1703 return fdt32_to_cpu(*phandle);
1706 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1709 const void *fdt = gd->fdt_blob;
1710 const __be32 *phandle;
1713 int node = dev_of_offset(mmc->dev);
1715 phandle = fdt_getprop(fdt, node, prop_name, &len);
1717 debug("failed to get property %s\n", prop_name);
1721 /* No manual mode iodelay values if count < 2 */
1722 count = len / sizeof(*phandle);
1726 return fdt32_to_cpu(*(phandle + 1));
1729 static struct pad_conf_entry *
1730 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1734 struct pad_conf_entry *padconf;
1736 const fdt32_t *pinctrl;
1738 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1740 return ERR_PTR(-EINVAL);
1742 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1745 return ERR_PTR(-EINVAL);
1747 count = (len / sizeof(*pinctrl)) / 2;
1748 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1750 return ERR_PTR(-EINVAL);
1757 static struct iodelay_cfg_entry *
1758 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1762 struct iodelay_cfg_entry *iodelay;
1764 const fdt32_t *pinctrl;
1766 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1767 /* Not all modes have manual mode iodelay values. So its not fatal */
1771 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1774 return ERR_PTR(-EINVAL);
1776 count = (len / sizeof(*pinctrl)) / 3;
1777 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1779 return ERR_PTR(-EINVAL);
1786 static struct omap_hsmmc_pinctrl_state *
1787 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1792 const void *fdt = gd->fdt_blob;
1793 int node = dev_of_offset(mmc->dev);
1795 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1797 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1798 malloc(sizeof(*pinctrl_state));
1799 if (!pinctrl_state) {
1800 debug("failed to allocate memory\n");
1804 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1806 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1807 goto err_pinctrl_state;
1810 sprintf(prop_name, "pinctrl-%d", index);
1812 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1814 if (IS_ERR(pinctrl_state->padconf))
1815 goto err_pinctrl_state;
1816 pinctrl_state->npads = npads;
1818 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1820 if (IS_ERR(pinctrl_state->iodelay))
1822 pinctrl_state->niodelays = niodelays;
1824 return pinctrl_state;
1827 kfree(pinctrl_state->padconf);
1830 kfree(pinctrl_state);
1834 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
1836 struct omap_hsmmc_pinctrl_state *s = NULL; \
1838 if (!(cfg->host_caps & capmask)) \
1841 if (priv->hw_rev) { \
1842 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1843 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1847 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1849 if (!s && !optional) { \
1850 debug("%s: no pinctrl for %s\n", \
1851 mmc->dev->name, #mode); \
1852 cfg->host_caps &= ~(capmask); \
1854 priv->mode##_pinctrl_state = s; \
1858 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1860 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1861 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1862 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1864 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1867 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1868 if (!default_pinctrl) {
1869 printf("no pinctrl state for default mode\n");
1873 priv->default_pinctrl_state = default_pinctrl;
1875 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1876 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1877 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1878 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1879 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1881 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1882 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1883 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1889 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1890 #ifdef CONFIG_OMAP54XX
1891 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1897 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1899 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1900 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1902 struct mmc_config *cfg = &plat->cfg;
1903 #ifdef CONFIG_OMAP54XX
1904 const struct mmc_platform_fixups *fixups;
1906 const void *fdt = gd->fdt_blob;
1907 int node = dev_of_offset(dev);
1910 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1911 sizeof(struct hsmmc *),
1914 ret = mmc_of_parse(dev, cfg);
1919 cfg->f_max = 52000000;
1920 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1921 cfg->f_min = 400000;
1922 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1923 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1924 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1925 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1926 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1927 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1929 plat->controller_flags |= of_data->controller_flags;
1931 #ifdef CONFIG_OMAP54XX
1932 fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1934 plat->hw_rev = fixups->hw_rev;
1935 cfg->host_caps &= ~fixups->unsupported_caps;
1936 cfg->f_max = fixups->max_freq;
1946 static int omap_hsmmc_bind(struct udevice *dev)
1948 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1949 plat->mmc = calloc(1, sizeof(struct mmc));
1950 return mmc_bind(dev, plat->mmc, &plat->cfg);
1953 static int omap_hsmmc_probe(struct udevice *dev)
1955 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1956 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1957 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1958 struct mmc_config *cfg = &plat->cfg;
1960 #ifdef CONFIG_IODELAY_RECALIBRATION
1964 cfg->name = "OMAP SD/MMC";
1965 priv->base_addr = plat->base_addr;
1966 priv->controller_flags = plat->controller_flags;
1967 priv->hw_rev = plat->hw_rev;
1972 mmc = mmc_create(cfg, priv);
1976 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1977 device_get_supply_regulator(dev, "pbias-supply",
1978 &priv->pbias_supply);
1980 #if defined(OMAP_HSMMC_USE_GPIO)
1981 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1982 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1983 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1990 #ifdef CONFIG_IODELAY_RECALIBRATION
1991 ret = omap_hsmmc_get_pinctrl_state(mmc);
1993 * disable high speed modes for the platforms that require IO delay
1994 * and for which we don't have this information
1997 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1998 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1999 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2004 return omap_hsmmc_init_setup(mmc);
2007 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2009 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2010 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2013 static const struct udevice_id omap_hsmmc_ids[] = {
2014 { .compatible = "ti,omap3-hsmmc" },
2015 { .compatible = "ti,omap4-hsmmc" },
2016 { .compatible = "ti,am33xx-hsmmc" },
2017 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2022 U_BOOT_DRIVER(omap_hsmmc) = {
2023 .name = "omap_hsmmc",
2025 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2026 .of_match = omap_hsmmc_ids,
2027 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2028 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2031 .bind = omap_hsmmc_bind,
2033 .ops = &omap_hsmmc_ops,
2034 .probe = omap_hsmmc_probe,
2035 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2036 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2037 .flags = DM_FLAG_PRE_RELOC,