drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #ifdef CONFIG_OMAP54XX
  38 #include <asm/arch/mux_dra7xx.h>
  39 #include <asm/arch/dra7xx_iodelay.h>
  40 #endif
  41 #if !defined(CONFIG_SOC_KEYSTONE)
  42 #include <asm/gpio.h>
  43 #include <asm/arch/sys_proto.h>
  44 #endif
  45 #ifdef CONFIG_MMC_OMAP36XX_PINS
  46 #include <asm/arch/mux.h>
  47 #endif
  48 #include <dm.h>
  49 #include <power/regulator.h>
  50 #include <thermal.h>
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  55 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  56         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  57 #define OMAP_HSMMC_USE_GPIO
  58 #else
  59 #undef OMAP_HSMMC_USE_GPIO
  60 #endif
  61
  62 /* common definitions for all OMAPs */
  63 #define SYSCTL_SRC      (1 << 25)
  64 #define SYSCTL_SRD      (1 << 26)
  65
  66 #ifdef CONFIG_IODELAY_RECALIBRATION
  67 struct omap_hsmmc_pinctrl_state {
  68         struct pad_conf_entry *padconf;
  69         int npads;
  70         struct iodelay_cfg_entry *iodelay;
  71         int niodelays;
  72 };
  73 #endif
  74
  75 struct omap_hsmmc_data {
  76         struct hsmmc *base_addr;
  77 #if !CONFIG_IS_ENABLED(DM_MMC)
  78         struct mmc_config cfg;
  79 #endif
  80         uint bus_width;
  81         uint clock;
  82         ushort last_cmd;
  83 #ifdef OMAP_HSMMC_USE_GPIO
  84 #if CONFIG_IS_ENABLED(DM_MMC)
  85         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  86         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  87 #else
  88         int cd_gpio;
  89         int wp_gpio;
  90 #endif
  91 #endif
  92 #if CONFIG_IS_ENABLED(DM_MMC)
  93         enum bus_mode mode;
  94 #endif
  95         u8 controller_flags;
  96 #ifdef CONFIG_MMC_OMAP_HS_ADMA
  97         struct omap_hsmmc_adma_desc *adma_desc_table;
  98         uint desc_slot;
  99 #endif
 100         const char *hw_rev;
 101         struct udevice *pbias_supply;
 102         uint signal_voltage;
 103 #ifdef CONFIG_IODELAY_RECALIBRATION
 104         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 105         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 106         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 107         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 108         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 109         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 110         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 111         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 113 #endif
 114 };
 115
 116 struct omap_mmc_of_data {
 117         u8 controller_flags;
 118 };
 119
 120 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 121 struct omap_hsmmc_adma_desc {
 122         u8 attr;
 123         u8 reserved;
 124         u16 len;
 125         u32 addr;
 126 };
 127
 128 #define ADMA_MAX_LEN    63488
 129
 130 /* Decriptor table defines */
 131 #define ADMA_DESC_ATTR_VALID            BIT(0)
 132 #define ADMA_DESC_ATTR_END              BIT(1)
 133 #define ADMA_DESC_ATTR_INT              BIT(2)
 134 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 135 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 136
 137 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 138 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 139 #endif
 140
 141 /* If we fail after 1 second wait, something is really bad */
 142 #define MAX_RETRY_MS    1000
 143 #define MMC_TIMEOUT_MS  20
 144
 145 /* DMA transfers can take a long time if a lot a data is transferred.
 146  * The timeout must take in account the amount of data. Let's assume
 147  * that the time will never exceed 333 ms per MB (in other word we assume
 148  * that the bandwidth is always above 3MB/s).
 149  */
 150 #define DMA_TIMEOUT_PER_MB      333
 151 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 152 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 153 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 154 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 155
 156 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 157 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 158                         unsigned int siz);
 159 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 160 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 161 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 162
 163 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 164 {
 165 #if CONFIG_IS_ENABLED(DM_MMC)
 166         return dev_get_priv(mmc->dev);
 167 #else
 168         return (struct omap_hsmmc_data *)mmc->priv;
 169 #endif
 170 }
 171 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 172 {
 173 #if CONFIG_IS_ENABLED(DM_MMC)
 174         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 175         return &plat->cfg;
 176 #else
 177         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 178 #endif
 179 }
 180
 181 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 182 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 183 {
 184         int ret;
 185
 186 #ifndef CONFIG_DM_GPIO
 187         if (!gpio_is_valid(gpio))
 188                 return -1;
 189 #endif
 190         ret = gpio_request(gpio, label);
 191         if (ret)
 192                 return ret;
 193
 194         ret = gpio_direction_input(gpio);
 195         if (ret)
 196                 return ret;
 197
 198         return gpio;
 199 }
 200 #endif
 201
 202 static unsigned char mmc_board_init(struct mmc *mmc)
 203 {
 204 #if defined(CONFIG_OMAP34XX)
 205         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 206         t2_t *t2_base = (t2_t *)T2_BASE;
 207         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 208         u32 pbias_lite;
 209 #ifdef CONFIG_MMC_OMAP36XX_PINS
 210         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 211 #endif
 212
 213         pbias_lite = readl(&t2_base->pbias_lite);
 214         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 215 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 216         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 217         pbias_lite &= ~PBIASLITEVMODE0;
 218 #endif
 219 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 220         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 221         pbias_lite &= ~PBIASLITEVMODE1;
 222 #endif
 223 #ifdef CONFIG_MMC_OMAP36XX_PINS
 224         if (get_cpu_family() == CPU_OMAP36XX) {
 225                 /* Disable extended drain IO before changing PBIAS */
 226                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 227                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 228         }
 229 #endif
 230         writel(pbias_lite, &t2_base->pbias_lite);
 231
 232         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 233                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 234                 &t2_base->pbias_lite);
 235
 236 #ifdef CONFIG_MMC_OMAP36XX_PINS
 237         if (get_cpu_family() == CPU_OMAP36XX)
 238                 /* Enable extended drain IO after changing PBIAS */
 239                 writel(wkup_ctrl |
 240                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 241                                 OMAP34XX_CTRL_WKUP_CTRL);
 242 #endif
 243         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 244                 &t2_base->devconf0);
 245
 246         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 247                 &t2_base->devconf1);
 248
 249         /* Change from default of 52MHz to 26MHz if necessary */
 250         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 251                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 252                         &t2_base->ctl_prog_io1);
 253
 254         writel(readl(&prcm_base->fclken1_core) |
 255                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 256                 &prcm_base->fclken1_core);
 257
 258         writel(readl(&prcm_base->iclken1_core) |
 259                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 260                 &prcm_base->iclken1_core);
 261 #endif
 262
 263 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 264         !CONFIG_IS_ENABLED(DM_REGULATOR)
 265         /* PBIAS config needed for MMC1 only */
 266         if (mmc_get_blk_desc(mmc)->devnum == 0)
 267                 vmmc_pbias_config(LDO_VOLT_3V3);
 268 #endif
 269
 270         return 0;
 271 }
 272
 273 void mmc_init_stream(struct hsmmc *mmc_base)
 274 {
 275         ulong start;
 276
 277         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 278
 279         writel(MMC_CMD0, &mmc_base->cmd);
 280         start = get_timer(0);
 281         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 282                 if (get_timer(0) - start > MAX_RETRY_MS) {
 283                         printf("%s: timedout waiting for cc!\n", __func__);
 284                         return;
 285                 }
 286         }
 287         writel(CC_MASK, &mmc_base->stat)
 288                 ;
 289         writel(MMC_CMD0, &mmc_base->cmd)
 290                 ;
 291         start = get_timer(0);
 292         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 293                 if (get_timer(0) - start > MAX_RETRY_MS) {
 294                         printf("%s: timedout waiting for cc2!\n", __func__);
 295                         return;
 296                 }
 297         }
 298         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 299 }
 300
 301 #if CONFIG_IS_ENABLED(DM_MMC)
 302 #ifdef CONFIG_IODELAY_RECALIBRATION
 303 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 304 {
 305         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 306         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 307
 308         switch (priv->mode) {
 309         case MMC_HS_200:
 310                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 311                 break;
 312         case UHS_SDR104:
 313                 pinctrl_state = priv->sdr104_pinctrl_state;
 314                 break;
 315         case UHS_SDR50:
 316                 pinctrl_state = priv->sdr50_pinctrl_state;
 317                 break;
 318         case UHS_DDR50:
 319                 pinctrl_state = priv->ddr50_pinctrl_state;
 320                 break;
 321         case UHS_SDR25:
 322                 pinctrl_state = priv->sdr25_pinctrl_state;
 323                 break;
 324         case UHS_SDR12:
 325                 pinctrl_state = priv->sdr12_pinctrl_state;
 326                 break;
 327         case SD_HS:
 328         case MMC_HS:
 329         case MMC_HS_52:
 330                 pinctrl_state = priv->hs_pinctrl_state;
 331                 break;
 332         case MMC_DDR_52:
 333                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 334         default:
 335                 pinctrl_state = priv->default_pinctrl_state;
 336                 break;
 337         }
 338
 339         if (!pinctrl_state)
 340                 pinctrl_state = priv->default_pinctrl_state;
 341
 342         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 343                 if (pinctrl_state->iodelay)
 344                         late_recalibrate_iodelay(pinctrl_state->padconf,
 345                                                  pinctrl_state->npads,
 346                                                  pinctrl_state->iodelay,
 347                                                  pinctrl_state->niodelays);
 348                 else
 349                         do_set_mux32((*ctrl)->control_padconf_core_base,
 350                                      pinctrl_state->padconf,
 351                                      pinctrl_state->npads);
 352         }
 353 }
 354 #endif
 355 static void omap_hsmmc_set_timing(struct mmc *mmc)
 356 {
 357         u32 val;
 358         struct hsmmc *mmc_base;
 359         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 360
 361         mmc_base = priv->base_addr;
 362
 363         omap_hsmmc_stop_clock(mmc_base);
 364         val = readl(&mmc_base->ac12);
 365         val &= ~AC12_UHSMC_MASK;
 366         priv->mode = mmc->selected_mode;
 367
 368         if (mmc_is_mode_ddr(priv->mode))
 369                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 370         else
 371                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 372
 373         switch (priv->mode) {
 374         case MMC_HS_200:
 375         case UHS_SDR104:
 376                 val |= AC12_UHSMC_SDR104;
 377                 break;
 378         case UHS_SDR50:
 379                 val |= AC12_UHSMC_SDR50;
 380                 break;
 381         case MMC_DDR_52:
 382         case UHS_DDR50:
 383                 val |= AC12_UHSMC_DDR50;
 384                 break;
 385         case SD_HS:
 386         case MMC_HS_52:
 387         case UHS_SDR25:
 388                 val |= AC12_UHSMC_SDR25;
 389                 break;
 390         case MMC_LEGACY:
 391         case MMC_HS:
 392         case SD_LEGACY:
 393         case UHS_SDR12:
 394                 val |= AC12_UHSMC_SDR12;
 395                 break;
 396         default:
 397                 val |= AC12_UHSMC_RES;
 398                 break;
 399         }
 400         writel(val, &mmc_base->ac12);
 401
 402 #ifdef CONFIG_IODELAY_RECALIBRATION
 403         omap_hsmmc_io_recalibrate(mmc);
 404 #endif
 405         omap_hsmmc_start_clock(mmc_base);
 406 }
 407
 408 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 409 {
 410         struct hsmmc *mmc_base;
 411         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 412         u32 hctl, ac12;
 413
 414         mmc_base = priv->base_addr;
 415
 416         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 417         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 418
 419         switch (signal_voltage) {
 420         case MMC_SIGNAL_VOLTAGE_330:
 421                 hctl |= SDVS_3V3;
 422                 break;
 423         case MMC_SIGNAL_VOLTAGE_180:
 424                 hctl |= SDVS_1V8;
 425                 ac12 |= AC12_V1V8_SIGEN;
 426                 break;
 427         }
 428
 429         writel(hctl, &mmc_base->hctl);
 430         writel(ac12, &mmc_base->ac12);
 431 }
 432
 433 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 434 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout)
 435 {
 436         int ret = -ETIMEDOUT;
 437         u32 con;
 438         bool dat0_high;
 439         bool target_dat0_high = !!state;
 440         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 441         struct hsmmc *mmc_base = priv->base_addr;
 442
 443         con = readl(&mmc_base->con);
 444         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 445
 446         timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
 447         while (timeout--)       {
 448                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 449                 if (dat0_high == target_dat0_high) {
 450                         ret = 0;
 451                         break;
 452                 }
 453                 udelay(10);
 454         }
 455         writel(con, &mmc_base->con);
 456
 457         return ret;
 458 }
 459 #endif
 460
 461 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 462 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 463 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 464 {
 465         int ret = 0;
 466         int uV = mV * 1000;
 467
 468         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 469
 470         if (!mmc->vqmmc_supply)
 471                 return 0;
 472
 473         /* Disable PBIAS */
 474         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 475         if (ret)
 476                 return ret;
 477
 478         /* Turn off IO voltage */
 479         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 480         if (ret)
 481                 return ret;
 482         /* Program a new IO voltage value */
 483         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 484         if (ret)
 485                 return ret;
 486         /* Turn on IO voltage */
 487         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 488         if (ret)
 489                 return ret;
 490
 491         /* Program PBIAS voltage*/
 492         ret = regulator_set_value(priv->pbias_supply, uV);
 493         if (ret && ret != -ENOSYS)
 494                 return ret;
 495         /* Enable PBIAS */
 496         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 497         if (ret)
 498                 return ret;
 499
 500         return 0;
 501 }
 502 #endif
 503
 504 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 505 {
 506         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 507         struct hsmmc *mmc_base = priv->base_addr;
 508         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 509         u32 capa_mask;
 510         __maybe_unused u8 palmas_ldo_volt;
 511         u32 val;
 512
 513         if (mv < 0)
 514                 return -EINVAL;
 515
 516         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 517                 mv = 3300;
 518                 capa_mask = VS33_3V3SUP;
 519                 palmas_ldo_volt = LDO_VOLT_3V3;
 520         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 521                 capa_mask = VS18_1V8SUP;
 522                 palmas_ldo_volt = LDO_VOLT_1V8;
 523         } else {
 524                 return -EOPNOTSUPP;
 525         }
 526
 527         val = readl(&mmc_base->capa);
 528         if (!(val & capa_mask))
 529                 return -EOPNOTSUPP;
 530
 531         priv->signal_voltage = mmc->signal_voltage;
 532
 533         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 534
 535 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 536         return omap_hsmmc_set_io_regulator(mmc, mv);
 537 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 538         defined(CONFIG_PALMAS_POWER)
 539         if (mmc_get_blk_desc(mmc)->devnum == 0)
 540                 vmmc_pbias_config(palmas_ldo_volt);
 541         return 0;
 542 #else
 543         return 0;
 544 #endif
 545 }
 546 #endif
 547
 548 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 549 {
 550         struct hsmmc *mmc_base;
 551         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 552         u32 val;
 553
 554         mmc_base = priv->base_addr;
 555         val = readl(&mmc_base->capa);
 556
 557         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 558                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 559         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 560                 val |= VS33_3V3SUP;
 561                 val &= ~VS18_1V8SUP;
 562         } else {
 563                 val |= VS18_1V8SUP;
 564                 val &= ~VS33_3V3SUP;
 565         }
 566
 567         writel(val, &mmc_base->capa);
 568
 569         return val;
 570 }
 571
 572 #ifdef MMC_SUPPORTS_TUNING
 573 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 574 {
 575         struct hsmmc *mmc_base;
 576         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 577         u32 val;
 578
 579         mmc_base = priv->base_addr;
 580         val = readl(&mmc_base->ac12);
 581         val &= ~(AC12_SCLK_SEL);
 582         writel(val, &mmc_base->ac12);
 583
 584         val = readl(&mmc_base->dll);
 585         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 586         writel(val, &mmc_base->dll);
 587 }
 588
 589 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 590 {
 591         int i;
 592         struct hsmmc *mmc_base;
 593         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 594         u32 val;
 595
 596         mmc_base = priv->base_addr;
 597         val = readl(&mmc_base->dll);
 598         val |= DLL_FORCE_VALUE;
 599         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 600         val |= (count << DLL_FORCE_SR_C_SHIFT);
 601         writel(val, &mmc_base->dll);
 602
 603         val |= DLL_CALIB;
 604         writel(val, &mmc_base->dll);
 605         for (i = 0; i < 1000; i++) {
 606                 if (readl(&mmc_base->dll) & DLL_CALIB)
 607                         break;
 608         }
 609         val &= ~DLL_CALIB;
 610         writel(val, &mmc_base->dll);
 611 }
 612
 613 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 614 {
 615         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 616         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 617         struct mmc *mmc = upriv->mmc;
 618         struct hsmmc *mmc_base;
 619         u32 val;
 620         u8 cur_match, prev_match = 0;
 621         int ret;
 622         u32 phase_delay = 0;
 623         u32 start_window = 0, max_window = 0;
 624         u32 length = 0, max_len = 0;
 625         bool single_point_failure = false;
 626         struct udevice *thermal_dev;
 627         int temperature;
 628         int i;
 629
 630         mmc_base = priv->base_addr;
 631         val = readl(&mmc_base->capa2);
 632
 633         /* clock tuning is not needed for upto 52MHz */
 634         if (!((mmc->selected_mode == MMC_HS_200) ||
 635               (mmc->selected_mode == UHS_SDR104) ||
 636               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 637                 return 0;
 638
 639         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 640         if (ret) {
 641                 printf("Couldn't get thermal device for tuning\n");
 642                 return ret;
 643         }
 644         ret = thermal_get_temp(thermal_dev, &temperature);
 645         if (ret) {
 646                 printf("Couldn't get temperature for tuning\n");
 647                 return ret;
 648         }
 649         val = readl(&mmc_base->dll);
 650         val |= DLL_SWT;
 651         writel(val, &mmc_base->dll);
 652
 653         /*
 654          * Stage 1: Search for a maximum pass window ignoring any
 655          * any single point failures. If the tuning value ends up
 656          * near it, move away from it in stage 2 below
 657          */
 658         while (phase_delay <= MAX_PHASE_DELAY) {
 659                 omap_hsmmc_set_dll(mmc, phase_delay);
 660
 661                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 662
 663                 if (cur_match) {
 664                         if (prev_match) {
 665                                 length++;
 666                         } else if (single_point_failure) {
 667                                 /* ignore single point failure */
 668                                 length++;
 669                                 single_point_failure = false;
 670                         } else {
 671                                 start_window = phase_delay;
 672                                 length = 1;
 673                         }
 674                 } else {
 675                         single_point_failure = prev_match;
 676                 }
 677
 678                 if (length > max_len) {
 679                         max_window = start_window;
 680                         max_len = length;
 681                 }
 682
 683                 prev_match = cur_match;
 684                 phase_delay += 4;
 685         }
 686
 687         if (!max_len) {
 688                 ret = -EIO;
 689                 goto tuning_error;
 690         }
 691
 692         val = readl(&mmc_base->ac12);
 693         if (!(val & AC12_SCLK_SEL)) {
 694                 ret = -EIO;
 695                 goto tuning_error;
 696         }
 697         /*
 698          * Assign tuning value as a ratio of maximum pass window based
 699          * on temperature
 700          */
 701         if (temperature < -20000)
 702                 phase_delay = min(max_window + 4 * max_len - 24,
 703                                   max_window +
 704                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 705         else if (temperature < 20000)
 706                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 707         else if (temperature < 40000)
 708                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 709         else if (temperature < 70000)
 710                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 711         else if (temperature < 90000)
 712                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 713         else if (temperature < 120000)
 714                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 715         else
 716                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 717
 718         /*
 719          * Stage 2: Search for a single point failure near the chosen tuning
 720          * value in two steps. First in the +3 to +10 range and then in the
 721          * +2 to -10 range. If found, move away from it in the appropriate
 722          * direction by the appropriate amount depending on the temperature.
 723          */
 724         for (i = 3; i <= 10; i++) {
 725                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 726                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 727                         if (temperature < 10000)
 728                                 phase_delay += i + 6;
 729                         else if (temperature < 20000)
 730                                 phase_delay += i - 12;
 731                         else if (temperature < 70000)
 732                                 phase_delay += i - 8;
 733                         else if (temperature < 90000)
 734                                 phase_delay += i - 6;
 735                         else
 736                                 phase_delay += i - 6;
 737
 738                         goto single_failure_found;
 739                 }
 740         }
 741
 742         for (i = 2; i >= -10; i--) {
 743                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 744                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 745                         if (temperature < 10000)
 746                                 phase_delay += i + 12;
 747                         else if (temperature < 20000)
 748                                 phase_delay += i + 8;
 749                         else if (temperature < 70000)
 750                                 phase_delay += i + 8;
 751                         else if (temperature < 90000)
 752                                 phase_delay += i + 10;
 753                         else
 754                                 phase_delay += i + 12;
 755
 756                         goto single_failure_found;
 757                 }
 758         }
 759
 760 single_failure_found:
 761
 762         omap_hsmmc_set_dll(mmc, phase_delay);
 763
 764         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 765         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 766
 767         return 0;
 768
 769 tuning_error:
 770
 771         omap_hsmmc_disable_tuning(mmc);
 772         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 773         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 774
 775         return ret;
 776 }
 777 #endif
 778
 779 static void omap_hsmmc_send_init_stream(struct udevice *dev)
 780 {
 781         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 782         struct hsmmc *mmc_base = priv->base_addr;
 783
 784         mmc_init_stream(mmc_base);
 785 }
 786 #endif
 787
 788 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 789 {
 790         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 791         struct hsmmc *mmc_base = priv->base_addr;
 792         u32 irq_mask = INT_EN_MASK;
 793
 794         /*
 795          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 796          * tuning procedure and DCRC should be disabled. But see occurences
 797          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 798          * interrupts occur along with BRR, so the data is actually in the
 799          * buffer. It has to be debugged why these interrutps occur
 800          */
 801         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 802                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 803
 804         writel(irq_mask, &mmc_base->ie);
 805 }
 806
 807 static int omap_hsmmc_init_setup(struct mmc *mmc)
 808 {
 809         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 810         struct hsmmc *mmc_base;
 811         unsigned int reg_val;
 812         unsigned int dsor;
 813         ulong start;
 814
 815         mmc_base = priv->base_addr;
 816         mmc_board_init(mmc);
 817
 818         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 819                 &mmc_base->sysconfig);
 820         start = get_timer(0);
 821         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 822                 if (get_timer(0) - start > MAX_RETRY_MS) {
 823                         printf("%s: timedout waiting for cc2!\n", __func__);
 824                         return -ETIMEDOUT;
 825                 }
 826         }
 827         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 828         start = get_timer(0);
 829         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 830                 if (get_timer(0) - start > MAX_RETRY_MS) {
 831                         printf("%s: timedout waiting for softresetall!\n",
 832                                 __func__);
 833                         return -ETIMEDOUT;
 834                 }
 835         }
 836 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 837         reg_val = readl(&mmc_base->hl_hwinfo);
 838         if (reg_val & MADMA_EN)
 839                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 840 #endif
 841
 842 #if CONFIG_IS_ENABLED(DM_MMC)
 843         reg_val = omap_hsmmc_set_capabilities(mmc);
 844         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 845                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 846 #else
 847         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 848         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 849                 &mmc_base->capa);
 850 #endif
 851
 852         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 853
 854         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 855                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 856                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 857
 858         dsor = 240;
 859         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 860                 (ICE_STOP | DTO_15THDTO));
 861         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 862                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 863         start = get_timer(0);
 864         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 865                 if (get_timer(0) - start > MAX_RETRY_MS) {
 866                         printf("%s: timedout waiting for ics!\n", __func__);
 867                         return -ETIMEDOUT;
 868                 }
 869         }
 870         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 871
 872         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 873
 874         mmc_enable_irq(mmc, NULL);
 875
 876 #if !CONFIG_IS_ENABLED(DM_MMC)
 877         mmc_init_stream(mmc_base);
 878 #endif
 879
 880         return 0;
 881 }
 882
 883 /*
 884  * MMC controller internal finite state machine reset
 885  *
 886  * Used to reset command or data internal state machines, using respectively
 887  * SRC or SRD bit of SYSCTL register
 888  */
 889 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 890 {
 891         ulong start;
 892
 893         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 894
 895         /*
 896          * CMD(DAT) lines reset procedures are slightly different
 897          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 898          * According to OMAP3 TRM:
 899          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 900          * returns to 0x0.
 901          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 902          * procedure steps must be as follows:
 903          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 904          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 905          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 906          * 3. Wait until the SRC (SRD) bit returns to 0x0
 907          *    (reset procedure is completed).
 908          */
 909 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 910         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 911         if (!(readl(&mmc_base->sysctl) & bit)) {
 912                 start = get_timer(0);
 913                 while (!(readl(&mmc_base->sysctl) & bit)) {
 914                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 915                                 return;
 916                 }
 917         }
 918 #endif
 919         start = get_timer(0);
 920         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 921                 if (get_timer(0) - start > MAX_RETRY_MS) {
 922                         printf("%s: timedout waiting for sysctl %x to clear\n",
 923                                 __func__, bit);
 924                         return;
 925                 }
 926         }
 927 }
 928
 929 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 930 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 931 {
 932         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 933         struct omap_hsmmc_adma_desc *desc;
 934         u8 attr;
 935
 936         desc = &priv->adma_desc_table[priv->desc_slot];
 937
 938         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 939         if (!end)
 940                 priv->desc_slot++;
 941         else
 942                 attr |= ADMA_DESC_ATTR_END;
 943
 944         desc->len = len;
 945         desc->addr = (u32)buf;
 946         desc->reserved = 0;
 947         desc->attr = attr;
 948 }
 949
 950 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 951                                           struct mmc_data *data)
 952 {
 953         uint total_len = data->blocksize * data->blocks;
 954         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 955         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 956         int i = desc_count;
 957         char *buf;
 958
 959         priv->desc_slot = 0;
 960         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 961                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 962                                 sizeof(struct omap_hsmmc_adma_desc));
 963
 964         if (data->flags & MMC_DATA_READ)
 965                 buf = data->dest;
 966         else
 967                 buf = (char *)data->src;
 968
 969         while (--i) {
 970                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 971                 buf += ADMA_MAX_LEN;
 972                 total_len -= ADMA_MAX_LEN;
 973         }
 974
 975         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 976
 977         flush_dcache_range((long)priv->adma_desc_table,
 978                            (long)priv->adma_desc_table +
 979                            ROUND(desc_count *
 980                            sizeof(struct omap_hsmmc_adma_desc),
 981                            ARCH_DMA_MINALIGN));
 982 }
 983
 984 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 985 {
 986         struct hsmmc *mmc_base;
 987         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 988         u32 val;
 989         char *buf;
 990
 991         mmc_base = priv->base_addr;
 992         omap_hsmmc_prepare_adma_table(mmc, data);
 993
 994         if (data->flags & MMC_DATA_READ)
 995                 buf = data->dest;
 996         else
 997                 buf = (char *)data->src;
 998
 999         val = readl(&mmc_base->hctl);
1000         val |= DMA_SELECT;
1001         writel(val, &mmc_base->hctl);
1002
1003         val = readl(&mmc_base->con);
1004         val |= DMA_MASTER;
1005         writel(val, &mmc_base->con);
1006
1007         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1008
1009         flush_dcache_range((u32)buf,
1010                            (u32)buf +
1011                            ROUND(data->blocksize * data->blocks,
1012                                  ARCH_DMA_MINALIGN));
1013 }
1014
1015 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1016 {
1017         struct hsmmc *mmc_base;
1018         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1019         u32 val;
1020
1021         mmc_base = priv->base_addr;
1022
1023         val = readl(&mmc_base->con);
1024         val &= ~DMA_MASTER;
1025         writel(val, &mmc_base->con);
1026
1027         val = readl(&mmc_base->hctl);
1028         val &= ~DMA_SELECT;
1029         writel(val, &mmc_base->hctl);
1030
1031         kfree(priv->adma_desc_table);
1032 }
1033 #else
1034 #define omap_hsmmc_adma_desc
1035 #define omap_hsmmc_prepare_adma_table
1036 #define omap_hsmmc_prepare_data
1037 #define omap_hsmmc_dma_cleanup
1038 #endif
1039
1040 #if !CONFIG_IS_ENABLED(DM_MMC)
1041 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1042                         struct mmc_data *data)
1043 {
1044         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1045 #else
1046 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1047                         struct mmc_data *data)
1048 {
1049         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1050         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1051         struct mmc *mmc = upriv->mmc;
1052 #endif
1053         struct hsmmc *mmc_base;
1054         unsigned int flags, mmc_stat;
1055         ulong start;
1056         priv->last_cmd = cmd->cmdidx;
1057
1058         mmc_base = priv->base_addr;
1059
1060         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1061                 return 0;
1062
1063         start = get_timer(0);
1064         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1065                 if (get_timer(0) - start > MAX_RETRY_MS) {
1066                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1067                                         __func__);
1068                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1069                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1070                         return -ETIMEDOUT;
1071                 }
1072         }
1073         writel(0xFFFFFFFF, &mmc_base->stat);
1074         if (readl(&mmc_base->stat)) {
1075                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1076                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1077         }
1078
1079         /*
1080          * CMDREG
1081          * CMDIDX[13:8] : Command index
1082          * DATAPRNT[5]  : Data Present Select
1083          * ENCMDIDX[4]  : Command Index Check Enable
1084          * ENCMDCRC[3]  : Command CRC Check Enable
1085          * RSPTYP[1:0]
1086          *      00 = No Response
1087          *      01 = Length 136
1088          *      10 = Length 48
1089          *      11 = Length 48 Check busy after response
1090          */
1091         /* Delay added before checking the status of frq change
1092          * retry not supported by mmc.c(core file)
1093          */
1094         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1095                 udelay(50000); /* wait 50 ms */
1096
1097         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1098                 flags = 0;
1099         else if (cmd->resp_type & MMC_RSP_136)
1100                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1101         else if (cmd->resp_type & MMC_RSP_BUSY)
1102                 flags = RSP_TYPE_LGHT48B;
1103         else
1104                 flags = RSP_TYPE_LGHT48;
1105
1106         /* enable default flags */
1107         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1108                         MSBS_SGLEBLK);
1109         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1110
1111         if (cmd->resp_type & MMC_RSP_CRC)
1112                 flags |= CCCE_CHECK;
1113         if (cmd->resp_type & MMC_RSP_OPCODE)
1114                 flags |= CICE_CHECK;
1115
1116         if (data) {
1117                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1118                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1119                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1120                         data->blocksize = 512;
1121                         writel(data->blocksize | (data->blocks << 16),
1122                                                         &mmc_base->blk);
1123                 } else
1124                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1125
1126                 if (data->flags & MMC_DATA_READ)
1127                         flags |= (DP_DATA | DDIR_READ);
1128                 else
1129                         flags |= (DP_DATA | DDIR_WRITE);
1130
1131 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1132                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1133                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1134                         omap_hsmmc_prepare_data(mmc, data);
1135                         flags |= DE_ENABLE;
1136                 }
1137 #endif
1138         }
1139
1140         mmc_enable_irq(mmc, cmd);
1141
1142         writel(cmd->cmdarg, &mmc_base->arg);
1143         udelay(20);             /* To fix "No status update" error on eMMC */
1144         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1145
1146         start = get_timer(0);
1147         do {
1148                 mmc_stat = readl(&mmc_base->stat);
1149                 if (get_timer(start) > MAX_RETRY_MS) {
1150                         printf("%s : timeout: No status update\n", __func__);
1151                         return -ETIMEDOUT;
1152                 }
1153         } while (!mmc_stat);
1154
1155         if ((mmc_stat & IE_CTO) != 0) {
1156                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1157                 return -ETIMEDOUT;
1158         } else if ((mmc_stat & ERRI_MASK) != 0)
1159                 return -1;
1160
1161         if (mmc_stat & CC_MASK) {
1162                 writel(CC_MASK, &mmc_base->stat);
1163                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1164                         if (cmd->resp_type & MMC_RSP_136) {
1165                                 /* response type 2 */
1166                                 cmd->response[3] = readl(&mmc_base->rsp10);
1167                                 cmd->response[2] = readl(&mmc_base->rsp32);
1168                                 cmd->response[1] = readl(&mmc_base->rsp54);
1169                                 cmd->response[0] = readl(&mmc_base->rsp76);
1170                         } else
1171                                 /* response types 1, 1b, 3, 4, 5, 6 */
1172                                 cmd->response[0] = readl(&mmc_base->rsp10);
1173                 }
1174         }
1175
1176 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1177         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1178             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1179                 u32 sz_mb, timeout;
1180
1181                 if (mmc_stat & IE_ADMAE) {
1182                         omap_hsmmc_dma_cleanup(mmc);
1183                         return -EIO;
1184                 }
1185
1186                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1187                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1188                 if (timeout < MAX_RETRY_MS)
1189                         timeout = MAX_RETRY_MS;
1190
1191                 start = get_timer(0);
1192                 do {
1193                         mmc_stat = readl(&mmc_base->stat);
1194                         if (mmc_stat & TC_MASK) {
1195                                 writel(readl(&mmc_base->stat) | TC_MASK,
1196                                        &mmc_base->stat);
1197                                 break;
1198                         }
1199                         if (get_timer(start) > timeout) {
1200                                 printf("%s : DMA timeout: No status update\n",
1201                                        __func__);
1202                                 return -ETIMEDOUT;
1203                         }
1204                 } while (1);
1205
1206                 omap_hsmmc_dma_cleanup(mmc);
1207                 return 0;
1208         }
1209 #endif
1210
1211         if (data && (data->flags & MMC_DATA_READ)) {
1212                 mmc_read_data(mmc_base, data->dest,
1213                                 data->blocksize * data->blocks);
1214         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1215                 mmc_write_data(mmc_base, data->src,
1216                                 data->blocksize * data->blocks);
1217         }
1218         return 0;
1219 }
1220
1221 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1222 {
1223         unsigned int *output_buf = (unsigned int *)buf;
1224         unsigned int mmc_stat;
1225         unsigned int count;
1226
1227         /*
1228          * Start Polled Read
1229          */
1230         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1231         count /= 4;
1232
1233         while (size) {
1234                 ulong start = get_timer(0);
1235                 do {
1236                         mmc_stat = readl(&mmc_base->stat);
1237                         if (get_timer(0) - start > MAX_RETRY_MS) {
1238                                 printf("%s: timedout waiting for status!\n",
1239                                                 __func__);
1240                                 return -ETIMEDOUT;
1241                         }
1242                 } while (mmc_stat == 0);
1243
1244                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1245                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1246
1247                 if ((mmc_stat & ERRI_MASK) != 0)
1248                         return 1;
1249
1250                 if (mmc_stat & BRR_MASK) {
1251                         unsigned int k;
1252
1253                         writel(readl(&mmc_base->stat) | BRR_MASK,
1254                                 &mmc_base->stat);
1255                         for (k = 0; k < count; k++) {
1256                                 *output_buf = readl(&mmc_base->data);
1257                                 output_buf++;
1258                         }
1259                         size -= (count*4);
1260                 }
1261
1262                 if (mmc_stat & BWR_MASK)
1263                         writel(readl(&mmc_base->stat) | BWR_MASK,
1264                                 &mmc_base->stat);
1265
1266                 if (mmc_stat & TC_MASK) {
1267                         writel(readl(&mmc_base->stat) | TC_MASK,
1268                                 &mmc_base->stat);
1269                         break;
1270                 }
1271         }
1272         return 0;
1273 }
1274
1275 #if CONFIG_IS_ENABLED(MMC_WRITE)
1276 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1277                           unsigned int size)
1278 {
1279         unsigned int *input_buf = (unsigned int *)buf;
1280         unsigned int mmc_stat;
1281         unsigned int count;
1282
1283         /*
1284          * Start Polled Write
1285          */
1286         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1287         count /= 4;
1288
1289         while (size) {
1290                 ulong start = get_timer(0);
1291                 do {
1292                         mmc_stat = readl(&mmc_base->stat);
1293                         if (get_timer(0) - start > MAX_RETRY_MS) {
1294                                 printf("%s: timedout waiting for status!\n",
1295                                                 __func__);
1296                                 return -ETIMEDOUT;
1297                         }
1298                 } while (mmc_stat == 0);
1299
1300                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1301                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1302
1303                 if ((mmc_stat & ERRI_MASK) != 0)
1304                         return 1;
1305
1306                 if (mmc_stat & BWR_MASK) {
1307                         unsigned int k;
1308
1309                         writel(readl(&mmc_base->stat) | BWR_MASK,
1310                                         &mmc_base->stat);
1311                         for (k = 0; k < count; k++) {
1312                                 writel(*input_buf, &mmc_base->data);
1313                                 input_buf++;
1314                         }
1315                         size -= (count*4);
1316                 }
1317
1318                 if (mmc_stat & BRR_MASK)
1319                         writel(readl(&mmc_base->stat) | BRR_MASK,
1320                                 &mmc_base->stat);
1321
1322                 if (mmc_stat & TC_MASK) {
1323                         writel(readl(&mmc_base->stat) | TC_MASK,
1324                                 &mmc_base->stat);
1325                         break;
1326                 }
1327         }
1328         return 0;
1329 }
1330 #else
1331 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1332                           unsigned int size)
1333 {
1334         return -ENOTSUPP;
1335 }
1336 #endif
1337 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1338 {
1339         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1340 }
1341
1342 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1343 {
1344         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1345 }
1346
1347 static void omap_hsmmc_set_clock(struct mmc *mmc)
1348 {
1349         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1350         struct hsmmc *mmc_base;
1351         unsigned int dsor = 0;
1352         ulong start;
1353
1354         mmc_base = priv->base_addr;
1355         omap_hsmmc_stop_clock(mmc_base);
1356
1357         /* TODO: Is setting DTO required here? */
1358         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1359                     (ICE_STOP | DTO_15THDTO));
1360
1361         if (mmc->clock != 0) {
1362                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1363                 if (dsor > CLKD_MAX)
1364                         dsor = CLKD_MAX;
1365         } else {
1366                 dsor = CLKD_MAX;
1367         }
1368
1369         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1370                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1371
1372         start = get_timer(0);
1373         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1374                 if (get_timer(0) - start > MAX_RETRY_MS) {
1375                         printf("%s: timedout waiting for ics!\n", __func__);
1376                         return;
1377                 }
1378         }
1379
1380         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1381         mmc->clock = priv->clock;
1382         omap_hsmmc_start_clock(mmc_base);
1383 }
1384
1385 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1386 {
1387         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1388         struct hsmmc *mmc_base;
1389
1390         mmc_base = priv->base_addr;
1391         /* configue bus width */
1392         switch (mmc->bus_width) {
1393         case 8:
1394                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1395                         &mmc_base->con);
1396                 break;
1397
1398         case 4:
1399                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1400                         &mmc_base->con);
1401                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1402                         &mmc_base->hctl);
1403                 break;
1404
1405         case 1:
1406         default:
1407                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1408                         &mmc_base->con);
1409                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1410                         &mmc_base->hctl);
1411                 break;
1412         }
1413
1414         priv->bus_width = mmc->bus_width;
1415 }
1416
1417 #if !CONFIG_IS_ENABLED(DM_MMC)
1418 static int omap_hsmmc_set_ios(struct mmc *mmc)
1419 {
1420         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1421 #else
1422 static int omap_hsmmc_set_ios(struct udevice *dev)
1423 {
1424         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1425         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1426         struct mmc *mmc = upriv->mmc;
1427 #endif
1428         struct hsmmc *mmc_base = priv->base_addr;
1429         int ret = 0;
1430
1431         if (priv->bus_width != mmc->bus_width)
1432                 omap_hsmmc_set_bus_width(mmc);
1433
1434         if (priv->clock != mmc->clock)
1435                 omap_hsmmc_set_clock(mmc);
1436
1437         if (mmc->clk_disable)
1438                 omap_hsmmc_stop_clock(mmc_base);
1439         else
1440                 omap_hsmmc_start_clock(mmc_base);
1441
1442 #if CONFIG_IS_ENABLED(DM_MMC)
1443         if (priv->mode != mmc->selected_mode)
1444                 omap_hsmmc_set_timing(mmc);
1445
1446 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1447         if (priv->signal_voltage != mmc->signal_voltage)
1448                 ret = omap_hsmmc_set_signal_voltage(mmc);
1449 #endif
1450 #endif
1451         return ret;
1452 }
1453
1454 #ifdef OMAP_HSMMC_USE_GPIO
1455 #if CONFIG_IS_ENABLED(DM_MMC)
1456 static int omap_hsmmc_getcd(struct udevice *dev)
1457 {
1458         int value = -1;
1459 #if CONFIG_IS_ENABLED(DM_GPIO)
1460         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1461         value = dm_gpio_get_value(&priv->cd_gpio);
1462 #endif
1463         /* if no CD return as 1 */
1464         if (value < 0)
1465                 return 1;
1466
1467         return value;
1468 }
1469
1470 static int omap_hsmmc_getwp(struct udevice *dev)
1471 {
1472         int value = 0;
1473 #if CONFIG_IS_ENABLED(DM_GPIO)
1474         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1475         value = dm_gpio_get_value(&priv->wp_gpio);
1476 #endif
1477         /* if no WP return as 0 */
1478         if (value < 0)
1479                 return 0;
1480         return value;
1481 }
1482 #else
1483 static int omap_hsmmc_getcd(struct mmc *mmc)
1484 {
1485         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1486         int cd_gpio;
1487
1488         /* if no CD return as 1 */
1489         cd_gpio = priv->cd_gpio;
1490         if (cd_gpio < 0)
1491                 return 1;
1492
1493         /* NOTE: assumes card detect signal is active-low */
1494         return !gpio_get_value(cd_gpio);
1495 }
1496
1497 static int omap_hsmmc_getwp(struct mmc *mmc)
1498 {
1499         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1500         int wp_gpio;
1501
1502         /* if no WP return as 0 */
1503         wp_gpio = priv->wp_gpio;
1504         if (wp_gpio < 0)
1505                 return 0;
1506
1507         /* NOTE: assumes write protect signal is active-high */
1508         return gpio_get_value(wp_gpio);
1509 }
1510 #endif
1511 #endif
1512
1513 #if CONFIG_IS_ENABLED(DM_MMC)
1514 static const struct dm_mmc_ops omap_hsmmc_ops = {
1515         .send_cmd       = omap_hsmmc_send_cmd,
1516         .set_ios        = omap_hsmmc_set_ios,
1517 #ifdef OMAP_HSMMC_USE_GPIO
1518         .get_cd         = omap_hsmmc_getcd,
1519         .get_wp         = omap_hsmmc_getwp,
1520 #endif
1521 #ifdef MMC_SUPPORTS_TUNING
1522         .execute_tuning = omap_hsmmc_execute_tuning,
1523 #endif
1524         .send_init_stream       = omap_hsmmc_send_init_stream,
1525 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1526         .wait_dat0      = omap_hsmmc_wait_dat0,
1527 #endif
1528 };
1529 #else
1530 static const struct mmc_ops omap_hsmmc_ops = {
1531         .send_cmd       = omap_hsmmc_send_cmd,
1532         .set_ios        = omap_hsmmc_set_ios,
1533         .init           = omap_hsmmc_init_setup,
1534 #ifdef OMAP_HSMMC_USE_GPIO
1535         .getcd          = omap_hsmmc_getcd,
1536         .getwp          = omap_hsmmc_getwp,
1537 #endif
1538 };
1539 #endif
1540
1541 #if !CONFIG_IS_ENABLED(DM_MMC)
1542 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1543                 int wp_gpio)
1544 {
1545         struct mmc *mmc;
1546         struct omap_hsmmc_data *priv;
1547         struct mmc_config *cfg;
1548         uint host_caps_val;
1549
1550         priv = calloc(1, sizeof(*priv));
1551         if (priv == NULL)
1552                 return -1;
1553
1554         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1555
1556         switch (dev_index) {
1557         case 0:
1558                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1559                 break;
1560 #ifdef OMAP_HSMMC2_BASE
1561         case 1:
1562                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1563 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1564         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1565         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1566                 defined(CONFIG_HSMMC2_8BIT)
1567                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1568                 host_caps_val |= MMC_MODE_8BIT;
1569 #endif
1570                 break;
1571 #endif
1572 #ifdef OMAP_HSMMC3_BASE
1573         case 2:
1574                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1575 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1576                 /* Enable 8-bit interface for eMMC on DRA7XX */
1577                 host_caps_val |= MMC_MODE_8BIT;
1578 #endif
1579                 break;
1580 #endif
1581         default:
1582                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1583                 return 1;
1584         }
1585 #ifdef OMAP_HSMMC_USE_GPIO
1586         /* on error gpio values are set to -1, which is what we want */
1587         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1588         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1589 #endif
1590
1591         cfg = &priv->cfg;
1592
1593         cfg->name = "OMAP SD/MMC";
1594         cfg->ops = &omap_hsmmc_ops;
1595
1596         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1597         cfg->host_caps = host_caps_val & ~host_caps_mask;
1598
1599         cfg->f_min = 400000;
1600
1601         if (f_max != 0)
1602                 cfg->f_max = f_max;
1603         else {
1604                 if (cfg->host_caps & MMC_MODE_HS) {
1605                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1606                                 cfg->f_max = 52000000;
1607                         else
1608                                 cfg->f_max = 26000000;
1609                 } else
1610                         cfg->f_max = 20000000;
1611         }
1612
1613         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1614
1615 #if defined(CONFIG_OMAP34XX)
1616         /*
1617          * Silicon revs 2.1 and older do not support multiblock transfers.
1618          */
1619         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1620                 cfg->b_max = 1;
1621 #endif
1622
1623         mmc = mmc_create(cfg, priv);
1624         if (mmc == NULL)
1625                 return -1;
1626
1627         return 0;
1628 }
1629 #else
1630
1631 #ifdef CONFIG_IODELAY_RECALIBRATION
1632 static struct pad_conf_entry *
1633 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1634 {
1635         int index = 0;
1636         struct pad_conf_entry *padconf;
1637
1638         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1639         if (!padconf) {
1640                 debug("failed to allocate memory\n");
1641                 return 0;
1642         }
1643
1644         while (index < count) {
1645                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1646                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1647                 index++;
1648         }
1649
1650         return padconf;
1651 }
1652
1653 static struct iodelay_cfg_entry *
1654 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1655 {
1656         int index = 0;
1657         struct iodelay_cfg_entry *iodelay;
1658
1659         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1660         if (!iodelay) {
1661                 debug("failed to allocate memory\n");
1662                 return 0;
1663         }
1664
1665         while (index < count) {
1666                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1667                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1668                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1669                 index++;
1670         }
1671
1672         return iodelay;
1673 }
1674
1675 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1676                                                    const char *name, int *len)
1677 {
1678         const void *fdt = gd->fdt_blob;
1679         int offset;
1680         const fdt32_t *pinctrl;
1681
1682         offset = fdt_node_offset_by_phandle(fdt, phandle);
1683         if (offset < 0) {
1684                 debug("failed to get pinctrl node %s.\n",
1685                       fdt_strerror(offset));
1686                 return 0;
1687         }
1688
1689         pinctrl = fdt_getprop(fdt, offset, name, len);
1690         if (!pinctrl) {
1691                 debug("failed to get property %s\n", name);
1692                 return 0;
1693         }
1694
1695         return pinctrl;
1696 }
1697
1698 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1699                                                 char *prop_name)
1700 {
1701         const void *fdt = gd->fdt_blob;
1702         const __be32 *phandle;
1703         int node = dev_of_offset(mmc->dev);
1704
1705         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1706         if (!phandle) {
1707                 debug("failed to get property %s\n", prop_name);
1708                 return 0;
1709         }
1710
1711         return fdt32_to_cpu(*phandle);
1712 }
1713
1714 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1715                                                char *prop_name)
1716 {
1717         const void *fdt = gd->fdt_blob;
1718         const __be32 *phandle;
1719         int len;
1720         int count;
1721         int node = dev_of_offset(mmc->dev);
1722
1723         phandle = fdt_getprop(fdt, node, prop_name, &len);
1724         if (!phandle) {
1725                 debug("failed to get property %s\n", prop_name);
1726                 return 0;
1727         }
1728
1729         /* No manual mode iodelay values if count < 2 */
1730         count = len / sizeof(*phandle);
1731         if (count < 2)
1732                 return 0;
1733
1734         return fdt32_to_cpu(*(phandle + 1));
1735 }
1736
1737 static struct pad_conf_entry *
1738 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1739 {
1740         int len;
1741         int count;
1742         struct pad_conf_entry *padconf;
1743         u32 phandle;
1744         const fdt32_t *pinctrl;
1745
1746         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1747         if (!phandle)
1748                 return ERR_PTR(-EINVAL);
1749
1750         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1751                                                &len);
1752         if (!pinctrl)
1753                 return ERR_PTR(-EINVAL);
1754
1755         count = (len / sizeof(*pinctrl)) / 2;
1756         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1757         if (!padconf)
1758                 return ERR_PTR(-EINVAL);
1759
1760         *npads = count;
1761
1762         return padconf;
1763 }
1764
1765 static struct iodelay_cfg_entry *
1766 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1767 {
1768         int len;
1769         int count;
1770         struct iodelay_cfg_entry *iodelay;
1771         u32 phandle;
1772         const fdt32_t *pinctrl;
1773
1774         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1775         /* Not all modes have manual mode iodelay values. So its not fatal */
1776         if (!phandle)
1777                 return 0;
1778
1779         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1780                                                &len);
1781         if (!pinctrl)
1782                 return ERR_PTR(-EINVAL);
1783
1784         count = (len / sizeof(*pinctrl)) / 3;
1785         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1786         if (!iodelay)
1787                 return ERR_PTR(-EINVAL);
1788
1789         *niodelay = count;
1790
1791         return iodelay;
1792 }
1793
1794 static struct omap_hsmmc_pinctrl_state *
1795 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1796 {
1797         int index;
1798         int npads = 0;
1799         int niodelays = 0;
1800         const void *fdt = gd->fdt_blob;
1801         int node = dev_of_offset(mmc->dev);
1802         char prop_name[11];
1803         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1804
1805         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1806                          malloc(sizeof(*pinctrl_state));
1807         if (!pinctrl_state) {
1808                 debug("failed to allocate memory\n");
1809                 return 0;
1810         }
1811
1812         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1813         if (index < 0) {
1814                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1815                 goto err_pinctrl_state;
1816         }
1817
1818         sprintf(prop_name, "pinctrl-%d", index);
1819
1820         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1821                                                          &npads);
1822         if (IS_ERR(pinctrl_state->padconf))
1823                 goto err_pinctrl_state;
1824         pinctrl_state->npads = npads;
1825
1826         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1827                                                         &niodelays);
1828         if (IS_ERR(pinctrl_state->iodelay))
1829                 goto err_padconf;
1830         pinctrl_state->niodelays = niodelays;
1831
1832         return pinctrl_state;
1833
1834 err_padconf:
1835         kfree(pinctrl_state->padconf);
1836
1837 err_pinctrl_state:
1838         kfree(pinctrl_state);
1839         return 0;
1840 }
1841
1842 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1843         do {                                                            \
1844                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1845                 char str[20];                                           \
1846                 if (!(cfg->host_caps & capmask))                        \
1847                         break;                                          \
1848                                                                         \
1849                 if (priv->hw_rev) {                                     \
1850                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1851                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1852                 }                                                       \
1853                                                                         \
1854                 if (!s)                                                 \
1855                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1856                                                                         \
1857                 if (!s && !optional) {                                  \
1858                         debug("%s: no pinctrl for %s\n",                \
1859                               mmc->dev->name, #mode);                   \
1860                         cfg->host_caps &= ~(capmask);                   \
1861                 } else {                                                \
1862                         priv->mode##_pinctrl_state = s;                 \
1863                 }                                                       \
1864         } while (0)
1865
1866 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1867 {
1868         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1869         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1870         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1871
1872         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1873                 return 0;
1874
1875         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1876         if (!default_pinctrl) {
1877                 printf("no pinctrl state for default mode\n");
1878                 return -EINVAL;
1879         }
1880
1881         priv->default_pinctrl_state = default_pinctrl;
1882
1883         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1884         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1885         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1886         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1887         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1888
1889         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1890         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1891         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1892
1893         return 0;
1894 }
1895 #endif
1896
1897 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1898 #ifdef CONFIG_OMAP54XX
1899 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1900 {
1901         return NULL;
1902 }
1903 #endif
1904
1905 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1906 {
1907         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1908         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1909
1910         struct mmc_config *cfg = &plat->cfg;
1911 #ifdef CONFIG_OMAP54XX
1912         const struct mmc_platform_fixups *fixups;
1913 #endif
1914         const void *fdt = gd->fdt_blob;
1915         int node = dev_of_offset(dev);
1916         int ret;
1917
1918         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1919                                       sizeof(struct hsmmc *),
1920                                       MAP_NOCACHE);
1921
1922         ret = mmc_of_parse(dev, cfg);
1923         if (ret < 0)
1924                 return ret;
1925
1926         if (!cfg->f_max)
1927                 cfg->f_max = 52000000;
1928         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1929         cfg->f_min = 400000;
1930         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1931         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1932         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1933                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1934         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1935                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1936         if (of_data)
1937                 plat->controller_flags |= of_data->controller_flags;
1938
1939 #ifdef CONFIG_OMAP54XX
1940         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1941         if (fixups) {
1942                 plat->hw_rev = fixups->hw_rev;
1943                 cfg->host_caps &= ~fixups->unsupported_caps;
1944                 cfg->f_max = fixups->max_freq;
1945         }
1946 #endif
1947
1948         return 0;
1949 }
1950 #endif
1951
1952 #ifdef CONFIG_BLK
1953
1954 static int omap_hsmmc_bind(struct udevice *dev)
1955 {
1956         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1957         plat->mmc = calloc(1, sizeof(struct mmc));
1958         return mmc_bind(dev, plat->mmc, &plat->cfg);
1959 }
1960 #endif
1961 static int omap_hsmmc_probe(struct udevice *dev)
1962 {
1963         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1964         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1965         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1966         struct mmc_config *cfg = &plat->cfg;
1967         struct mmc *mmc;
1968 #ifdef CONFIG_IODELAY_RECALIBRATION
1969         int ret;
1970 #endif
1971
1972         cfg->name = "OMAP SD/MMC";
1973         priv->base_addr = plat->base_addr;
1974         priv->controller_flags = plat->controller_flags;
1975         priv->hw_rev = plat->hw_rev;
1976
1977 #ifdef CONFIG_BLK
1978         mmc = plat->mmc;
1979 #else
1980         mmc = mmc_create(cfg, priv);
1981         if (mmc == NULL)
1982                 return -1;
1983 #endif
1984 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1985         device_get_supply_regulator(dev, "pbias-supply",
1986                                     &priv->pbias_supply);
1987 #endif
1988 #if defined(OMAP_HSMMC_USE_GPIO)
1989 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1990         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1991         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1992 #endif
1993 #endif
1994
1995         mmc->dev = dev;
1996         upriv->mmc = mmc;
1997
1998 #ifdef CONFIG_IODELAY_RECALIBRATION
1999         ret = omap_hsmmc_get_pinctrl_state(mmc);
2000         /*
2001          * disable high speed modes for the platforms that require IO delay
2002          * and for which we don't have this information
2003          */
2004         if ((ret < 0) &&
2005             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
2006                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2007                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2008                                     UHS_CAPS);
2009         }
2010 #endif
2011
2012         return omap_hsmmc_init_setup(mmc);
2013 }
2014
2015 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2016
2017 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2018         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2019 };
2020
2021 static const struct udevice_id omap_hsmmc_ids[] = {
2022         { .compatible = "ti,omap3-hsmmc" },
2023         { .compatible = "ti,omap4-hsmmc" },
2024         { .compatible = "ti,am33xx-hsmmc" },
2025         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2026         { }
2027 };
2028 #endif
2029
2030 U_BOOT_DRIVER(omap_hsmmc) = {
2031         .name   = "omap_hsmmc",
2032         .id     = UCLASS_MMC,
2033 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2034         .of_match = omap_hsmmc_ids,
2035         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2036         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2037 #endif
2038 #ifdef CONFIG_BLK
2039         .bind = omap_hsmmc_bind,
2040 #endif
2041         .ops = &omap_hsmmc_ops,
2042         .probe  = omap_hsmmc_probe,
2043         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2044 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2045         .flags  = DM_FLAG_PRE_RELOC,
2046 #endif
2047 };
2048 #endif