drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <cpu_func.h>
  28 #include <log.h>
  29 #include <malloc.h>
  30 #include <memalign.h>
  31 #include <mmc.h>
  32 #include <part.h>
  33 #include <i2c.h>
  34 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  35 #include <palmas.h>
  36 #endif
  37 #include <asm/cache.h>
  38 #include <asm/global_data.h>
  39 #include <asm/io.h>
  40 #include <asm/arch/mmc_host_def.h>
  41 #ifdef CONFIG_OMAP54XX
  42 #include <asm/arch/mux_dra7xx.h>
  43 #include <asm/arch/dra7xx_iodelay.h>
  44 #endif
  45 #if !defined(CONFIG_ARCH_KEYSTONE)
  46 #include <asm/gpio.h>
  47 #include <asm/arch/sys_proto.h>
  48 #endif
  49 #ifdef CONFIG_MMC_OMAP36XX_PINS
  50 #include <asm/arch/mux.h>
  51 #endif
  52 #include <dm.h>
  53 #include <dm/devres.h>
  54 #include <linux/bitops.h>
  55 #include <linux/delay.h>
  56 #include <linux/err.h>
  57 #include <power/regulator.h>
  58 #include <thermal.h>
  59
  60 DECLARE_GLOBAL_DATA_PTR;
  61
  62 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  63 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  64         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
  65 #define OMAP_HSMMC_USE_GPIO
  66 #else
  67 #undef OMAP_HSMMC_USE_GPIO
  68 #endif
  69
  70 /* common definitions for all OMAPs */
  71 #define SYSCTL_SRC      (1 << 25)
  72 #define SYSCTL_SRD      (1 << 26)
  73
  74 #ifdef CONFIG_IODELAY_RECALIBRATION
  75 struct omap_hsmmc_pinctrl_state {
  76         struct pad_conf_entry *padconf;
  77         int npads;
  78         struct iodelay_cfg_entry *iodelay;
  79         int niodelays;
  80 };
  81 #endif
  82
  83 struct omap_hsmmc_data {
  84         struct hsmmc *base_addr;
  85 #if !CONFIG_IS_ENABLED(DM_MMC)
  86         struct mmc_config cfg;
  87 #endif
  88         uint bus_width;
  89         uint clock;
  90         ushort last_cmd;
  91 #ifdef OMAP_HSMMC_USE_GPIO
  92 #if CONFIG_IS_ENABLED(DM_MMC)
  93         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  94         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  95 #else
  96         int cd_gpio;
  97         int wp_gpio;
  98 #endif
  99 #endif
 100 #if CONFIG_IS_ENABLED(DM_MMC)
 101         enum bus_mode mode;
 102 #endif
 103         u8 controller_flags;
 104 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 105         struct omap_hsmmc_adma_desc *adma_desc_table;
 106         uint desc_slot;
 107 #endif
 108         const char *hw_rev;
 109         struct udevice *pbias_supply;
 110         uint signal_voltage;
 111 #ifdef CONFIG_IODELAY_RECALIBRATION
 112         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 113         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 114         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 115         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 116         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 117         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 118         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 119         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 120         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 121 #endif
 122 };
 123
 124 struct omap_mmc_of_data {
 125         u8 controller_flags;
 126 };
 127
 128 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 129 struct omap_hsmmc_adma_desc {
 130         u8 attr;
 131         u8 reserved;
 132         u16 len;
 133         u32 addr;
 134 };
 135
 136 #define ADMA_MAX_LEN    63488
 137
 138 /* Decriptor table defines */
 139 #define ADMA_DESC_ATTR_VALID            BIT(0)
 140 #define ADMA_DESC_ATTR_END              BIT(1)
 141 #define ADMA_DESC_ATTR_INT              BIT(2)
 142 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 143 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 144
 145 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 146 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 147 #endif
 148
 149 /* If we fail after 1 second wait, something is really bad */
 150 #define MAX_RETRY_MS    1000
 151 #define MMC_TIMEOUT_MS  20
 152
 153 /* DMA transfers can take a long time if a lot a data is transferred.
 154  * The timeout must take in account the amount of data. Let's assume
 155  * that the time will never exceed 333 ms per MB (in other word we assume
 156  * that the bandwidth is always above 3MB/s).
 157  */
 158 #define DMA_TIMEOUT_PER_MB      333
 159 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 160 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 161 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 162 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 163
 164 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 165 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 166                         unsigned int siz);
 167 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 168 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 169 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 170
 171 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 172 {
 173 #if CONFIG_IS_ENABLED(DM_MMC)
 174         return dev_get_priv(mmc->dev);
 175 #else
 176         return (struct omap_hsmmc_data *)mmc->priv;
 177 #endif
 178 }
 179
 180 #if defined(CONFIG_OMAP34XX) || defined(CONFIG_IODELAY_RECALIBRATION)
 181 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 182 {
 183 #if CONFIG_IS_ENABLED(DM_MMC)
 184         struct omap_hsmmc_plat *plat = dev_get_plat(mmc->dev);
 185         return &plat->cfg;
 186 #else
 187         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 188 #endif
 189 }
 190 #endif
 191
 192 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 193 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 194 {
 195         int ret;
 196
 197 #if !CONFIG_IS_ENABLED(DM_GPIO)
 198         if (!gpio_is_valid(gpio))
 199                 return -1;
 200 #endif
 201         ret = gpio_request(gpio, label);
 202         if (ret)
 203                 return ret;
 204
 205         ret = gpio_direction_input(gpio);
 206         if (ret)
 207                 return ret;
 208
 209         return gpio;
 210 }
 211 #endif
 212
 213 static unsigned char mmc_board_init(struct mmc *mmc)
 214 {
 215 #if defined(CONFIG_OMAP34XX)
 216         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 217         t2_t *t2_base = (t2_t *)T2_BASE;
 218         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 219         u32 pbias_lite;
 220 #ifdef CONFIG_MMC_OMAP36XX_PINS
 221         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 222 #endif
 223
 224         pbias_lite = readl(&t2_base->pbias_lite);
 225         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 226 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 227         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 228         pbias_lite &= ~PBIASLITEVMODE0;
 229 #endif
 230 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 231         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 232         pbias_lite &= ~PBIASLITEVMODE1;
 233 #endif
 234 #ifdef CONFIG_MMC_OMAP36XX_PINS
 235         if (get_cpu_family() == CPU_OMAP36XX) {
 236                 /* Disable extended drain IO before changing PBIAS */
 237                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 238                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 239         }
 240 #endif
 241         writel(pbias_lite, &t2_base->pbias_lite);
 242
 243         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 244                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 245                 &t2_base->pbias_lite);
 246
 247 #ifdef CONFIG_MMC_OMAP36XX_PINS
 248         if (get_cpu_family() == CPU_OMAP36XX)
 249                 /* Enable extended drain IO after changing PBIAS */
 250                 writel(wkup_ctrl |
 251                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 252                                 OMAP34XX_CTRL_WKUP_CTRL);
 253 #endif
 254         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 255                 &t2_base->devconf0);
 256
 257         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 258                 &t2_base->devconf1);
 259
 260         /* Change from default of 52MHz to 26MHz if necessary */
 261         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 262                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 263                         &t2_base->ctl_prog_io1);
 264
 265         writel(readl(&prcm_base->fclken1_core) |
 266                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 267                 &prcm_base->fclken1_core);
 268
 269         writel(readl(&prcm_base->iclken1_core) |
 270                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 271                 &prcm_base->iclken1_core);
 272 #endif
 273
 274 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 275         !CONFIG_IS_ENABLED(DM_REGULATOR)
 276         /* PBIAS config needed for MMC1 only */
 277         if (mmc_get_blk_desc(mmc)->devnum == 0)
 278                 vmmc_pbias_config(LDO_VOLT_3V3);
 279 #endif
 280
 281         return 0;
 282 }
 283
 284 void mmc_init_stream(struct hsmmc *mmc_base)
 285 {
 286         ulong start;
 287
 288         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 289
 290         writel(MMC_CMD0, &mmc_base->cmd);
 291         start = get_timer(0);
 292         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 293                 if (get_timer(0) - start > MAX_RETRY_MS) {
 294                         printf("%s: timedout waiting for cc!\n", __func__);
 295                         return;
 296                 }
 297         }
 298         writel(CC_MASK, &mmc_base->stat)
 299                 ;
 300         writel(MMC_CMD0, &mmc_base->cmd)
 301                 ;
 302         start = get_timer(0);
 303         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 304                 if (get_timer(0) - start > MAX_RETRY_MS) {
 305                         printf("%s: timedout waiting for cc2!\n", __func__);
 306                         return;
 307                 }
 308         }
 309         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 310 }
 311
 312 #if CONFIG_IS_ENABLED(DM_MMC)
 313 #ifdef CONFIG_IODELAY_RECALIBRATION
 314 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 315 {
 316         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 317         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 318
 319         switch (priv->mode) {
 320         case MMC_HS_200:
 321                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 322                 break;
 323         case UHS_SDR104:
 324                 pinctrl_state = priv->sdr104_pinctrl_state;
 325                 break;
 326         case UHS_SDR50:
 327                 pinctrl_state = priv->sdr50_pinctrl_state;
 328                 break;
 329         case UHS_DDR50:
 330                 pinctrl_state = priv->ddr50_pinctrl_state;
 331                 break;
 332         case UHS_SDR25:
 333                 pinctrl_state = priv->sdr25_pinctrl_state;
 334                 break;
 335         case UHS_SDR12:
 336                 pinctrl_state = priv->sdr12_pinctrl_state;
 337                 break;
 338         case SD_HS:
 339         case MMC_HS:
 340         case MMC_HS_52:
 341                 pinctrl_state = priv->hs_pinctrl_state;
 342                 break;
 343         case MMC_DDR_52:
 344                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 345         default:
 346                 pinctrl_state = priv->default_pinctrl_state;
 347                 break;
 348         }
 349
 350         if (!pinctrl_state)
 351                 pinctrl_state = priv->default_pinctrl_state;
 352
 353         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 354                 if (pinctrl_state->iodelay)
 355                         late_recalibrate_iodelay(pinctrl_state->padconf,
 356                                                  pinctrl_state->npads,
 357                                                  pinctrl_state->iodelay,
 358                                                  pinctrl_state->niodelays);
 359                 else
 360                         do_set_mux32((*ctrl)->control_padconf_core_base,
 361                                      pinctrl_state->padconf,
 362                                      pinctrl_state->npads);
 363         }
 364 }
 365 #endif
 366 static void omap_hsmmc_set_timing(struct mmc *mmc)
 367 {
 368         u32 val;
 369         struct hsmmc *mmc_base;
 370         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 371
 372         mmc_base = priv->base_addr;
 373
 374         omap_hsmmc_stop_clock(mmc_base);
 375         val = readl(&mmc_base->ac12);
 376         val &= ~AC12_UHSMC_MASK;
 377         priv->mode = mmc->selected_mode;
 378
 379         if (mmc_is_mode_ddr(priv->mode))
 380                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 381         else
 382                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 383
 384         switch (priv->mode) {
 385         case MMC_HS_200:
 386         case UHS_SDR104:
 387                 val |= AC12_UHSMC_SDR104;
 388                 break;
 389         case UHS_SDR50:
 390                 val |= AC12_UHSMC_SDR50;
 391                 break;
 392         case MMC_DDR_52:
 393         case UHS_DDR50:
 394                 val |= AC12_UHSMC_DDR50;
 395                 break;
 396         case SD_HS:
 397         case MMC_HS_52:
 398         case UHS_SDR25:
 399                 val |= AC12_UHSMC_SDR25;
 400                 break;
 401         case MMC_LEGACY:
 402         case MMC_HS:
 403         case UHS_SDR12:
 404                 val |= AC12_UHSMC_SDR12;
 405                 break;
 406         default:
 407                 val |= AC12_UHSMC_RES;
 408                 break;
 409         }
 410         writel(val, &mmc_base->ac12);
 411
 412 #ifdef CONFIG_IODELAY_RECALIBRATION
 413         omap_hsmmc_io_recalibrate(mmc);
 414 #endif
 415         omap_hsmmc_start_clock(mmc_base);
 416 }
 417
 418 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 419 {
 420         struct hsmmc *mmc_base;
 421         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 422         u32 hctl, ac12;
 423
 424         mmc_base = priv->base_addr;
 425
 426         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 427         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 428
 429         switch (signal_voltage) {
 430         case MMC_SIGNAL_VOLTAGE_330:
 431                 hctl |= SDVS_3V3;
 432                 break;
 433         case MMC_SIGNAL_VOLTAGE_180:
 434                 hctl |= SDVS_1V8;
 435                 ac12 |= AC12_V1V8_SIGEN;
 436                 break;
 437         }
 438
 439         writel(hctl, &mmc_base->hctl);
 440         writel(ac12, &mmc_base->ac12);
 441 }
 442
 443 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
 444 {
 445         int ret = -ETIMEDOUT;
 446         u32 con;
 447         bool dat0_high;
 448         bool target_dat0_high = !!state;
 449         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 450         struct hsmmc *mmc_base = priv->base_addr;
 451
 452         con = readl(&mmc_base->con);
 453         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 454
 455         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 456         while (timeout_us--) {
 457                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 458                 if (dat0_high == target_dat0_high) {
 459                         ret = 0;
 460                         break;
 461                 }
 462                 udelay(10);
 463         }
 464         writel(con, &mmc_base->con);
 465
 466         return ret;
 467 }
 468
 469 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 470 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 471 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 472 {
 473         int ret = 0;
 474         int uV = mV * 1000;
 475
 476         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 477
 478         if (!mmc->vqmmc_supply)
 479                 return 0;
 480
 481         /* Disable PBIAS */
 482         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 483         if (ret)
 484                 return ret;
 485
 486         /* Turn off IO voltage */
 487         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 488         if (ret)
 489                 return ret;
 490         /* Program a new IO voltage value */
 491         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 492         if (ret)
 493                 return ret;
 494         /* Turn on IO voltage */
 495         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 496         if (ret)
 497                 return ret;
 498
 499         /* Program PBIAS voltage*/
 500         ret = regulator_set_value(priv->pbias_supply, uV);
 501         if (ret && ret != -ENOSYS)
 502                 return ret;
 503         /* Enable PBIAS */
 504         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 505         if (ret)
 506                 return ret;
 507
 508         return 0;
 509 }
 510 #endif
 511
 512 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 513 {
 514         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 515         struct hsmmc *mmc_base = priv->base_addr;
 516         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 517         u32 capa_mask;
 518         __maybe_unused u8 palmas_ldo_volt;
 519         u32 val;
 520
 521         if (mv < 0)
 522                 return -EINVAL;
 523
 524         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 525                 mv = 3300;
 526                 capa_mask = VS33_3V3SUP;
 527                 palmas_ldo_volt = LDO_VOLT_3V3;
 528         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 529                 capa_mask = VS18_1V8SUP;
 530                 palmas_ldo_volt = LDO_VOLT_1V8;
 531         } else {
 532                 return -EOPNOTSUPP;
 533         }
 534
 535         val = readl(&mmc_base->capa);
 536         if (!(val & capa_mask))
 537                 return -EOPNOTSUPP;
 538
 539         priv->signal_voltage = mmc->signal_voltage;
 540
 541         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 542
 543 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 544         return omap_hsmmc_set_io_regulator(mmc, mv);
 545 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 546         defined(CONFIG_PALMAS_POWER)
 547         if (mmc_get_blk_desc(mmc)->devnum == 0)
 548                 vmmc_pbias_config(palmas_ldo_volt);
 549         return 0;
 550 #else
 551         return 0;
 552 #endif
 553 }
 554 #endif
 555
 556 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 557 {
 558         struct hsmmc *mmc_base;
 559         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 560         u32 val;
 561
 562         mmc_base = priv->base_addr;
 563         val = readl(&mmc_base->capa);
 564
 565         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 566                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 567         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 568                 val |= VS33_3V3SUP;
 569                 val &= ~VS18_1V8SUP;
 570         } else {
 571                 val |= VS18_1V8SUP;
 572                 val &= ~VS33_3V3SUP;
 573         }
 574
 575         writel(val, &mmc_base->capa);
 576
 577         return val;
 578 }
 579
 580 #ifdef MMC_SUPPORTS_TUNING
 581 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 582 {
 583         struct hsmmc *mmc_base;
 584         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 585         u32 val;
 586
 587         mmc_base = priv->base_addr;
 588         val = readl(&mmc_base->ac12);
 589         val &= ~(AC12_SCLK_SEL);
 590         writel(val, &mmc_base->ac12);
 591
 592         val = readl(&mmc_base->dll);
 593         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 594         writel(val, &mmc_base->dll);
 595 }
 596
 597 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 598 {
 599         int i;
 600         struct hsmmc *mmc_base;
 601         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 602         u32 val;
 603
 604         mmc_base = priv->base_addr;
 605         val = readl(&mmc_base->dll);
 606         val |= DLL_FORCE_VALUE;
 607         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 608         val |= (count << DLL_FORCE_SR_C_SHIFT);
 609         writel(val, &mmc_base->dll);
 610
 611         val |= DLL_CALIB;
 612         writel(val, &mmc_base->dll);
 613         for (i = 0; i < 1000; i++) {
 614                 if (readl(&mmc_base->dll) & DLL_CALIB)
 615                         break;
 616         }
 617         val &= ~DLL_CALIB;
 618         writel(val, &mmc_base->dll);
 619 }
 620
 621 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 622 {
 623         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 624         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 625         struct mmc *mmc = upriv->mmc;
 626         struct hsmmc *mmc_base;
 627         u32 val;
 628         u8 cur_match, prev_match = 0;
 629         int ret;
 630         u32 phase_delay = 0;
 631         u32 start_window = 0, max_window = 0;
 632         u32 length = 0, max_len = 0;
 633         bool single_point_failure = false;
 634         struct udevice *thermal_dev;
 635         int temperature;
 636         int i;
 637
 638         mmc_base = priv->base_addr;
 639         val = readl(&mmc_base->capa2);
 640
 641         /* clock tuning is not needed for upto 52MHz */
 642         if (!((mmc->selected_mode == MMC_HS_200) ||
 643               (mmc->selected_mode == UHS_SDR104) ||
 644               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 645                 return 0;
 646
 647         ret = uclass_first_device_err(UCLASS_THERMAL, &thermal_dev);
 648         if (ret) {
 649                 printf("Couldn't get thermal device for tuning\n");
 650                 return ret;
 651         }
 652         ret = thermal_get_temp(thermal_dev, &temperature);
 653         if (ret) {
 654                 printf("Couldn't get temperature for tuning\n");
 655                 return ret;
 656         }
 657         val = readl(&mmc_base->dll);
 658         val |= DLL_SWT;
 659         writel(val, &mmc_base->dll);
 660
 661         /*
 662          * Stage 1: Search for a maximum pass window ignoring any
 663          * any single point failures. If the tuning value ends up
 664          * near it, move away from it in stage 2 below
 665          */
 666         while (phase_delay <= MAX_PHASE_DELAY) {
 667                 omap_hsmmc_set_dll(mmc, phase_delay);
 668
 669                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 670
 671                 if (cur_match) {
 672                         if (prev_match) {
 673                                 length++;
 674                         } else if (single_point_failure) {
 675                                 /* ignore single point failure */
 676                                 length++;
 677                                 single_point_failure = false;
 678                         } else {
 679                                 start_window = phase_delay;
 680                                 length = 1;
 681                         }
 682                 } else {
 683                         single_point_failure = prev_match;
 684                 }
 685
 686                 if (length > max_len) {
 687                         max_window = start_window;
 688                         max_len = length;
 689                 }
 690
 691                 prev_match = cur_match;
 692                 phase_delay += 4;
 693         }
 694
 695         if (!max_len) {
 696                 ret = -EIO;
 697                 goto tuning_error;
 698         }
 699
 700         val = readl(&mmc_base->ac12);
 701         if (!(val & AC12_SCLK_SEL)) {
 702                 ret = -EIO;
 703                 goto tuning_error;
 704         }
 705         /*
 706          * Assign tuning value as a ratio of maximum pass window based
 707          * on temperature
 708          */
 709         if (temperature < -20000)
 710                 phase_delay = min(max_window + 4 * max_len - 24,
 711                                   max_window +
 712                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 713         else if (temperature < 20000)
 714                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 715         else if (temperature < 40000)
 716                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 717         else if (temperature < 70000)
 718                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 719         else if (temperature < 90000)
 720                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 721         else if (temperature < 120000)
 722                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 723         else
 724                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 725
 726         /*
 727          * Stage 2: Search for a single point failure near the chosen tuning
 728          * value in two steps. First in the +3 to +10 range and then in the
 729          * +2 to -10 range. If found, move away from it in the appropriate
 730          * direction by the appropriate amount depending on the temperature.
 731          */
 732         for (i = 3; i <= 10; i++) {
 733                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 734                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 735                         if (temperature < 10000)
 736                                 phase_delay += i + 6;
 737                         else if (temperature < 20000)
 738                                 phase_delay += i - 12;
 739                         else if (temperature < 70000)
 740                                 phase_delay += i - 8;
 741                         else if (temperature < 90000)
 742                                 phase_delay += i - 6;
 743                         else
 744                                 phase_delay += i - 6;
 745
 746                         goto single_failure_found;
 747                 }
 748         }
 749
 750         for (i = 2; i >= -10; i--) {
 751                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 752                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 753                         if (temperature < 10000)
 754                                 phase_delay += i + 12;
 755                         else if (temperature < 20000)
 756                                 phase_delay += i + 8;
 757                         else if (temperature < 70000)
 758                                 phase_delay += i + 8;
 759                         else if (temperature < 90000)
 760                                 phase_delay += i + 10;
 761                         else
 762                                 phase_delay += i + 12;
 763
 764                         goto single_failure_found;
 765                 }
 766         }
 767
 768 single_failure_found:
 769
 770         omap_hsmmc_set_dll(mmc, phase_delay);
 771
 772         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 773         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 774
 775         return 0;
 776
 777 tuning_error:
 778
 779         omap_hsmmc_disable_tuning(mmc);
 780         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 781         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 782
 783         return ret;
 784 }
 785 #endif
 786 #endif
 787
 788 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 789 {
 790         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 791         struct hsmmc *mmc_base = priv->base_addr;
 792         u32 irq_mask = INT_EN_MASK;
 793
 794         /*
 795          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 796          * tuning procedure and DCRC should be disabled. But see occurences
 797          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 798          * interrupts occur along with BRR, so the data is actually in the
 799          * buffer. It has to be debugged why these interrutps occur
 800          */
 801         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 802                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 803
 804         writel(irq_mask, &mmc_base->ie);
 805 }
 806
 807 static int omap_hsmmc_init_setup(struct mmc *mmc)
 808 {
 809         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 810         struct hsmmc *mmc_base;
 811         unsigned int reg_val;
 812         unsigned int dsor;
 813         ulong start;
 814
 815         mmc_base = priv->base_addr;
 816         mmc_board_init(mmc);
 817
 818         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 819                 &mmc_base->sysconfig);
 820         start = get_timer(0);
 821         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 822                 if (get_timer(0) - start > MAX_RETRY_MS) {
 823                         printf("%s: timedout waiting for cc2!\n", __func__);
 824                         return -ETIMEDOUT;
 825                 }
 826         }
 827         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 828         start = get_timer(0);
 829         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 830                 if (get_timer(0) - start > MAX_RETRY_MS) {
 831                         printf("%s: timedout waiting for softresetall!\n",
 832                                 __func__);
 833                         return -ETIMEDOUT;
 834                 }
 835         }
 836 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 837         reg_val = readl(&mmc_base->hl_hwinfo);
 838         if (reg_val & MADMA_EN)
 839                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 840 #endif
 841
 842 #if CONFIG_IS_ENABLED(DM_MMC)
 843         reg_val = omap_hsmmc_set_capabilities(mmc);
 844         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 845                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 846 #else
 847         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V3, &mmc_base->hctl);
 848         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 849                 &mmc_base->capa);
 850 #endif
 851
 852         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 853
 854         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 855                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 856                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 857
 858         dsor = 240;
 859         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 860                 (ICE_STOP | DTO_15THDTO));
 861         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 862                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 863         start = get_timer(0);
 864         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 865                 if (get_timer(0) - start > MAX_RETRY_MS) {
 866                         printf("%s: timedout waiting for ics!\n", __func__);
 867                         return -ETIMEDOUT;
 868                 }
 869         }
 870         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 871
 872         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 873
 874         mmc_enable_irq(mmc, NULL);
 875
 876 #if !CONFIG_IS_ENABLED(DM_MMC)
 877         mmc_init_stream(mmc_base);
 878 #endif
 879
 880         return 0;
 881 }
 882
 883 /*
 884  * MMC controller internal finite state machine reset
 885  *
 886  * Used to reset command or data internal state machines, using respectively
 887  * SRC or SRD bit of SYSCTL register
 888  */
 889 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 890 {
 891         ulong start;
 892
 893         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 894
 895         /*
 896          * CMD(DAT) lines reset procedures are slightly different
 897          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 898          * According to OMAP3 TRM:
 899          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 900          * returns to 0x0.
 901          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 902          * procedure steps must be as follows:
 903          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 904          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 905          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 906          * 3. Wait until the SRC (SRD) bit returns to 0x0
 907          *    (reset procedure is completed).
 908          */
 909 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 910         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 911         if (!(readl(&mmc_base->sysctl) & bit)) {
 912                 start = get_timer(0);
 913                 while (!(readl(&mmc_base->sysctl) & bit)) {
 914                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 915                                 return;
 916                 }
 917         }
 918 #endif
 919         start = get_timer(0);
 920         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 921                 if (get_timer(0) - start > MAX_RETRY_MS) {
 922                         printf("%s: timedout waiting for sysctl %x to clear\n",
 923                                 __func__, bit);
 924                         return;
 925                 }
 926         }
 927 }
 928
 929 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 930 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 931 {
 932         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 933         struct omap_hsmmc_adma_desc *desc;
 934         u8 attr;
 935
 936         desc = &priv->adma_desc_table[priv->desc_slot];
 937
 938         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 939         if (!end)
 940                 priv->desc_slot++;
 941         else
 942                 attr |= ADMA_DESC_ATTR_END;
 943
 944         desc->len = len;
 945         desc->addr = (u32)buf;
 946         desc->reserved = 0;
 947         desc->attr = attr;
 948 }
 949
 950 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 951                                           struct mmc_data *data)
 952 {
 953         uint total_len = data->blocksize * data->blocks;
 954         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 955         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 956         int i = desc_count;
 957         char *buf;
 958
 959         priv->desc_slot = 0;
 960         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 961                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 962                                 sizeof(struct omap_hsmmc_adma_desc));
 963
 964         if (data->flags & MMC_DATA_READ)
 965                 buf = data->dest;
 966         else
 967                 buf = (char *)data->src;
 968
 969         while (--i) {
 970                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 971                 buf += ADMA_MAX_LEN;
 972                 total_len -= ADMA_MAX_LEN;
 973         }
 974
 975         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 976
 977         flush_dcache_range((long)priv->adma_desc_table,
 978                            (long)priv->adma_desc_table +
 979                            ROUND(desc_count *
 980                            sizeof(struct omap_hsmmc_adma_desc),
 981                            ARCH_DMA_MINALIGN));
 982 }
 983
 984 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 985 {
 986         struct hsmmc *mmc_base;
 987         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 988         u32 val;
 989         char *buf;
 990
 991         mmc_base = priv->base_addr;
 992         omap_hsmmc_prepare_adma_table(mmc, data);
 993
 994         if (data->flags & MMC_DATA_READ)
 995                 buf = data->dest;
 996         else
 997                 buf = (char *)data->src;
 998
 999         val = readl(&mmc_base->hctl);
1000         val |= DMA_SELECT;
1001         writel(val, &mmc_base->hctl);
1002
1003         val = readl(&mmc_base->con);
1004         val |= DMA_MASTER;
1005         writel(val, &mmc_base->con);
1006
1007         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1008
1009         flush_dcache_range((u32)buf,
1010                            (u32)buf +
1011                            ROUND(data->blocksize * data->blocks,
1012                                  ARCH_DMA_MINALIGN));
1013 }
1014
1015 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1016 {
1017         struct hsmmc *mmc_base;
1018         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1019         u32 val;
1020
1021         mmc_base = priv->base_addr;
1022
1023         val = readl(&mmc_base->con);
1024         val &= ~DMA_MASTER;
1025         writel(val, &mmc_base->con);
1026
1027         val = readl(&mmc_base->hctl);
1028         val &= ~DMA_SELECT;
1029         writel(val, &mmc_base->hctl);
1030
1031         kfree(priv->adma_desc_table);
1032 }
1033 #else
1034 #define omap_hsmmc_adma_desc
1035 #define omap_hsmmc_prepare_adma_table
1036 #define omap_hsmmc_prepare_data
1037 #define omap_hsmmc_dma_cleanup
1038 #endif
1039
1040 #if !CONFIG_IS_ENABLED(DM_MMC)
1041 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1042                         struct mmc_data *data)
1043 {
1044         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1045 #else
1046 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1047                         struct mmc_data *data)
1048 {
1049         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1050         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1051         struct mmc *mmc = upriv->mmc;
1052 #endif
1053         struct hsmmc *mmc_base;
1054         unsigned int flags, mmc_stat;
1055         ulong start;
1056         priv->last_cmd = cmd->cmdidx;
1057
1058         mmc_base = priv->base_addr;
1059
1060         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1061                 return 0;
1062
1063         start = get_timer(0);
1064         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1065                 if (get_timer(0) - start > MAX_RETRY_MS) {
1066                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1067                                         __func__);
1068                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1069                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1070                         return -ETIMEDOUT;
1071                 }
1072         }
1073         writel(0xFFFFFFFF, &mmc_base->stat);
1074         if (readl(&mmc_base->stat)) {
1075                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1076                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1077         }
1078
1079         /*
1080          * CMDREG
1081          * CMDIDX[13:8] : Command index
1082          * DATAPRNT[5]  : Data Present Select
1083          * ENCMDIDX[4]  : Command Index Check Enable
1084          * ENCMDCRC[3]  : Command CRC Check Enable
1085          * RSPTYP[1:0]
1086          *      00 = No Response
1087          *      01 = Length 136
1088          *      10 = Length 48
1089          *      11 = Length 48 Check busy after response
1090          */
1091         /* Delay added before checking the status of frq change
1092          * retry not supported by mmc.c(core file)
1093          */
1094         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1095                 udelay(50000); /* wait 50 ms */
1096
1097         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1098                 flags = 0;
1099         else if (cmd->resp_type & MMC_RSP_136)
1100                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1101         else if (cmd->resp_type & MMC_RSP_BUSY)
1102                 flags = RSP_TYPE_LGHT48B;
1103         else
1104                 flags = RSP_TYPE_LGHT48;
1105
1106         /* enable default flags */
1107         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1108                         MSBS_SGLEBLK);
1109         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1110
1111         if (cmd->resp_type & MMC_RSP_CRC)
1112                 flags |= CCCE_CHECK;
1113         if (cmd->resp_type & MMC_RSP_OPCODE)
1114                 flags |= CICE_CHECK;
1115
1116         if (data) {
1117                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1118                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1119                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1120                         data->blocksize = 512;
1121                         writel(data->blocksize | (data->blocks << 16),
1122                                                         &mmc_base->blk);
1123                 } else
1124                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1125
1126                 if (data->flags & MMC_DATA_READ)
1127                         flags |= (DP_DATA | DDIR_READ);
1128                 else
1129                         flags |= (DP_DATA | DDIR_WRITE);
1130
1131 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1132                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1133                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1134                         omap_hsmmc_prepare_data(mmc, data);
1135                         flags |= DE_ENABLE;
1136                 }
1137 #endif
1138         }
1139
1140         mmc_enable_irq(mmc, cmd);
1141
1142         writel(cmd->cmdarg, &mmc_base->arg);
1143         udelay(20);             /* To fix "No status update" error on eMMC */
1144         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1145
1146         start = get_timer(0);
1147         do {
1148                 mmc_stat = readl(&mmc_base->stat);
1149                 if (get_timer(start) > MAX_RETRY_MS) {
1150                         printf("%s : timeout: No status update\n", __func__);
1151                         return -ETIMEDOUT;
1152                 }
1153         } while (!mmc_stat);
1154
1155         if ((mmc_stat & IE_CTO) != 0) {
1156                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1157                 return -ETIMEDOUT;
1158         } else if ((mmc_stat & ERRI_MASK) != 0)
1159                 return -1;
1160
1161         if (mmc_stat & CC_MASK) {
1162                 writel(CC_MASK, &mmc_base->stat);
1163                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1164                         if (cmd->resp_type & MMC_RSP_136) {
1165                                 /* response type 2 */
1166                                 cmd->response[3] = readl(&mmc_base->rsp10);
1167                                 cmd->response[2] = readl(&mmc_base->rsp32);
1168                                 cmd->response[1] = readl(&mmc_base->rsp54);
1169                                 cmd->response[0] = readl(&mmc_base->rsp76);
1170                         } else
1171                                 /* response types 1, 1b, 3, 4, 5, 6 */
1172                                 cmd->response[0] = readl(&mmc_base->rsp10);
1173                 }
1174         }
1175
1176 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1177         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1178             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1179                 u32 sz_mb, timeout;
1180
1181                 if (mmc_stat & IE_ADMAE) {
1182                         omap_hsmmc_dma_cleanup(mmc);
1183                         return -EIO;
1184                 }
1185
1186                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1187                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1188                 if (timeout < MAX_RETRY_MS)
1189                         timeout = MAX_RETRY_MS;
1190
1191                 start = get_timer(0);
1192                 do {
1193                         mmc_stat = readl(&mmc_base->stat);
1194                         if (mmc_stat & TC_MASK) {
1195                                 writel(readl(&mmc_base->stat) | TC_MASK,
1196                                        &mmc_base->stat);
1197                                 break;
1198                         }
1199                         if (get_timer(start) > timeout) {
1200                                 printf("%s : DMA timeout: No status update\n",
1201                                        __func__);
1202                                 return -ETIMEDOUT;
1203                         }
1204                 } while (1);
1205
1206                 omap_hsmmc_dma_cleanup(mmc);
1207                 return 0;
1208         }
1209 #endif
1210
1211         if (data && (data->flags & MMC_DATA_READ)) {
1212                 mmc_read_data(mmc_base, data->dest,
1213                                 data->blocksize * data->blocks);
1214         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1215                 mmc_write_data(mmc_base, data->src,
1216                                 data->blocksize * data->blocks);
1217         }
1218         return 0;
1219 }
1220
1221 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1222 {
1223         unsigned int *output_buf = (unsigned int *)buf;
1224         unsigned int mmc_stat;
1225         unsigned int count;
1226
1227         /*
1228          * Start Polled Read
1229          */
1230         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1231         count /= 4;
1232
1233         while (size) {
1234                 ulong start = get_timer(0);
1235                 do {
1236                         mmc_stat = readl(&mmc_base->stat);
1237                         if (get_timer(0) - start > MAX_RETRY_MS) {
1238                                 printf("%s: timedout waiting for status!\n",
1239                                                 __func__);
1240                                 return -ETIMEDOUT;
1241                         }
1242                 } while (mmc_stat == 0);
1243
1244                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1245                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1246
1247                 if ((mmc_stat & ERRI_MASK) != 0)
1248                         return 1;
1249
1250                 if (mmc_stat & BRR_MASK) {
1251                         unsigned int k;
1252
1253                         writel(readl(&mmc_base->stat) | BRR_MASK,
1254                                 &mmc_base->stat);
1255                         for (k = 0; k < count; k++) {
1256                                 *output_buf = readl(&mmc_base->data);
1257                                 output_buf++;
1258                         }
1259                         size -= (count*4);
1260                 }
1261
1262                 if (mmc_stat & BWR_MASK)
1263                         writel(readl(&mmc_base->stat) | BWR_MASK,
1264                                 &mmc_base->stat);
1265
1266                 if (mmc_stat & TC_MASK) {
1267                         writel(readl(&mmc_base->stat) | TC_MASK,
1268                                 &mmc_base->stat);
1269                         break;
1270                 }
1271         }
1272         return 0;
1273 }
1274
1275 #if CONFIG_IS_ENABLED(MMC_WRITE)
1276 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1277                           unsigned int size)
1278 {
1279         unsigned int *input_buf = (unsigned int *)buf;
1280         unsigned int mmc_stat;
1281         unsigned int count;
1282
1283         /*
1284          * Start Polled Write
1285          */
1286         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1287         count /= 4;
1288
1289         while (size) {
1290                 ulong start = get_timer(0);
1291                 do {
1292                         mmc_stat = readl(&mmc_base->stat);
1293                         if (get_timer(0) - start > MAX_RETRY_MS) {
1294                                 printf("%s: timedout waiting for status!\n",
1295                                                 __func__);
1296                                 return -ETIMEDOUT;
1297                         }
1298                 } while (mmc_stat == 0);
1299
1300                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1301                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1302
1303                 if ((mmc_stat & ERRI_MASK) != 0)
1304                         return 1;
1305
1306                 if (mmc_stat & BWR_MASK) {
1307                         unsigned int k;
1308
1309                         writel(readl(&mmc_base->stat) | BWR_MASK,
1310                                         &mmc_base->stat);
1311                         for (k = 0; k < count; k++) {
1312                                 writel(*input_buf, &mmc_base->data);
1313                                 input_buf++;
1314                         }
1315                         size -= (count*4);
1316                 }
1317
1318                 if (mmc_stat & BRR_MASK)
1319                         writel(readl(&mmc_base->stat) | BRR_MASK,
1320                                 &mmc_base->stat);
1321
1322                 if (mmc_stat & TC_MASK) {
1323                         writel(readl(&mmc_base->stat) | TC_MASK,
1324                                 &mmc_base->stat);
1325                         break;
1326                 }
1327         }
1328         return 0;
1329 }
1330 #else
1331 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1332                           unsigned int size)
1333 {
1334         return -ENOTSUPP;
1335 }
1336 #endif
1337 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1338 {
1339         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1340 }
1341
1342 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1343 {
1344         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1345 }
1346
1347 static void omap_hsmmc_set_clock(struct mmc *mmc)
1348 {
1349         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1350         struct hsmmc *mmc_base;
1351         unsigned int dsor = 0;
1352         ulong start;
1353
1354         mmc_base = priv->base_addr;
1355         omap_hsmmc_stop_clock(mmc_base);
1356
1357         /* TODO: Is setting DTO required here? */
1358         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1359                     (ICE_STOP | DTO_15THDTO));
1360
1361         if (mmc->clock != 0) {
1362                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1363                 if (dsor > CLKD_MAX)
1364                         dsor = CLKD_MAX;
1365         } else {
1366                 dsor = CLKD_MAX;
1367         }
1368
1369         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1370                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1371
1372         start = get_timer(0);
1373         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1374                 if (get_timer(0) - start > MAX_RETRY_MS) {
1375                         printf("%s: timedout waiting for ics!\n", __func__);
1376                         return;
1377                 }
1378         }
1379
1380         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1381         mmc->clock = priv->clock;
1382         omap_hsmmc_start_clock(mmc_base);
1383 }
1384
1385 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1386 {
1387         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1388         struct hsmmc *mmc_base;
1389
1390         mmc_base = priv->base_addr;
1391         /* configue bus width */
1392         switch (mmc->bus_width) {
1393         case 8:
1394                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1395                         &mmc_base->con);
1396                 break;
1397
1398         case 4:
1399                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1400                         &mmc_base->con);
1401                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1402                         &mmc_base->hctl);
1403                 break;
1404
1405         case 1:
1406         default:
1407                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1408                         &mmc_base->con);
1409                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1410                         &mmc_base->hctl);
1411                 break;
1412         }
1413
1414         priv->bus_width = mmc->bus_width;
1415 }
1416
1417 #if !CONFIG_IS_ENABLED(DM_MMC)
1418 static int omap_hsmmc_set_ios(struct mmc *mmc)
1419 {
1420         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1421 #else
1422 static int omap_hsmmc_set_ios(struct udevice *dev)
1423 {
1424         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1425         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1426         struct mmc *mmc = upriv->mmc;
1427 #endif
1428         struct hsmmc *mmc_base = priv->base_addr;
1429         int ret = 0;
1430
1431         if (priv->bus_width != mmc->bus_width)
1432                 omap_hsmmc_set_bus_width(mmc);
1433
1434         if (priv->clock != mmc->clock)
1435                 omap_hsmmc_set_clock(mmc);
1436
1437         if (mmc->clk_disable)
1438                 omap_hsmmc_stop_clock(mmc_base);
1439         else
1440                 omap_hsmmc_start_clock(mmc_base);
1441
1442 #if CONFIG_IS_ENABLED(DM_MMC)
1443         if (priv->mode != mmc->selected_mode)
1444                 omap_hsmmc_set_timing(mmc);
1445
1446 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1447         if (priv->signal_voltage != mmc->signal_voltage)
1448                 ret = omap_hsmmc_set_signal_voltage(mmc);
1449 #endif
1450 #endif
1451         return ret;
1452 }
1453
1454 #ifdef OMAP_HSMMC_USE_GPIO
1455 #if CONFIG_IS_ENABLED(DM_MMC)
1456 static int omap_hsmmc_getcd(struct udevice *dev)
1457 {
1458         int value = -1;
1459 #if CONFIG_IS_ENABLED(DM_GPIO)
1460         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1461         value = dm_gpio_get_value(&priv->cd_gpio);
1462 #endif
1463         /* if no CD return as 1 */
1464         if (value < 0)
1465                 return 1;
1466
1467         return value;
1468 }
1469
1470 static int omap_hsmmc_getwp(struct udevice *dev)
1471 {
1472         int value = 0;
1473 #if CONFIG_IS_ENABLED(DM_GPIO)
1474         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1475         value = dm_gpio_get_value(&priv->wp_gpio);
1476 #endif
1477         /* if no WP return as 0 */
1478         if (value < 0)
1479                 return 0;
1480         return value;
1481 }
1482 #else
1483 static int omap_hsmmc_getcd(struct mmc *mmc)
1484 {
1485         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1486         int cd_gpio;
1487
1488         /* if no CD return as 1 */
1489         cd_gpio = priv->cd_gpio;
1490         if (cd_gpio < 0)
1491                 return 1;
1492
1493         /* NOTE: assumes card detect signal is active-low */
1494         return !gpio_get_value(cd_gpio);
1495 }
1496
1497 static int omap_hsmmc_getwp(struct mmc *mmc)
1498 {
1499         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1500         int wp_gpio;
1501
1502         /* if no WP return as 0 */
1503         wp_gpio = priv->wp_gpio;
1504         if (wp_gpio < 0)
1505                 return 0;
1506
1507         /* NOTE: assumes write protect signal is active-high */
1508         return gpio_get_value(wp_gpio);
1509 }
1510 #endif
1511 #endif
1512
1513 #if CONFIG_IS_ENABLED(DM_MMC)
1514 static const struct dm_mmc_ops omap_hsmmc_ops = {
1515         .send_cmd       = omap_hsmmc_send_cmd,
1516         .set_ios        = omap_hsmmc_set_ios,
1517 #ifdef OMAP_HSMMC_USE_GPIO
1518         .get_cd         = omap_hsmmc_getcd,
1519         .get_wp         = omap_hsmmc_getwp,
1520 #endif
1521 #ifdef MMC_SUPPORTS_TUNING
1522         .execute_tuning = omap_hsmmc_execute_tuning,
1523 #endif
1524         .wait_dat0      = omap_hsmmc_wait_dat0,
1525 };
1526 #else
1527 static const struct mmc_ops omap_hsmmc_ops = {
1528         .send_cmd       = omap_hsmmc_send_cmd,
1529         .set_ios        = omap_hsmmc_set_ios,
1530         .init           = omap_hsmmc_init_setup,
1531 #ifdef OMAP_HSMMC_USE_GPIO
1532         .getcd          = omap_hsmmc_getcd,
1533         .getwp          = omap_hsmmc_getwp,
1534 #endif
1535 };
1536 #endif
1537
1538 #if !CONFIG_IS_ENABLED(DM_MMC)
1539 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1540                 int wp_gpio)
1541 {
1542         struct mmc *mmc;
1543         struct omap_hsmmc_data *priv;
1544         struct mmc_config *cfg;
1545         uint host_caps_val;
1546
1547         priv = calloc(1, sizeof(*priv));
1548         if (priv == NULL)
1549                 return -1;
1550
1551         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1552
1553         switch (dev_index) {
1554         case 0:
1555                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1556                 break;
1557 #ifdef OMAP_HSMMC2_BASE
1558         case 1:
1559                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1560 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1561         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1562         defined(CONFIG_AM43XX) || defined(CONFIG_ARCH_KEYSTONE)) && \
1563                 defined(CONFIG_HSMMC2_8BIT)
1564                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1565                 host_caps_val |= MMC_MODE_8BIT;
1566 #endif
1567                 break;
1568 #endif
1569 #ifdef OMAP_HSMMC3_BASE
1570         case 2:
1571                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1572 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1573                 /* Enable 8-bit interface for eMMC on DRA7XX */
1574                 host_caps_val |= MMC_MODE_8BIT;
1575 #endif
1576                 break;
1577 #endif
1578         default:
1579                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1580                 return 1;
1581         }
1582 #ifdef OMAP_HSMMC_USE_GPIO
1583         /* on error gpio values are set to -1, which is what we want */
1584         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1585         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1586 #endif
1587
1588         cfg = &priv->cfg;
1589
1590         cfg->name = "OMAP SD/MMC";
1591         cfg->ops = &omap_hsmmc_ops;
1592
1593         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1594         cfg->host_caps = host_caps_val & ~host_caps_mask;
1595
1596         cfg->f_min = 400000;
1597
1598         if (f_max != 0)
1599                 cfg->f_max = f_max;
1600         else {
1601                 if (cfg->host_caps & MMC_MODE_HS) {
1602                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1603                                 cfg->f_max = 52000000;
1604                         else
1605                                 cfg->f_max = 26000000;
1606                 } else
1607                         cfg->f_max = 20000000;
1608         }
1609
1610         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1611
1612 #if defined(CONFIG_OMAP34XX)
1613         /*
1614          * Silicon revs 2.1 and older do not support multiblock transfers.
1615          */
1616         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1617                 cfg->b_max = 1;
1618 #endif
1619
1620         mmc = mmc_create(cfg, priv);
1621         if (mmc == NULL)
1622                 return -1;
1623
1624         return 0;
1625 }
1626 #else
1627
1628 #ifdef CONFIG_IODELAY_RECALIBRATION
1629 static struct pad_conf_entry *
1630 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1631 {
1632         int index = 0;
1633         struct pad_conf_entry *padconf;
1634
1635         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1636         if (!padconf) {
1637                 debug("failed to allocate memory\n");
1638                 return 0;
1639         }
1640
1641         while (index < count) {
1642                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1643                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1644                 index++;
1645         }
1646
1647         return padconf;
1648 }
1649
1650 static struct iodelay_cfg_entry *
1651 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1652 {
1653         int index = 0;
1654         struct iodelay_cfg_entry *iodelay;
1655
1656         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1657         if (!iodelay) {
1658                 debug("failed to allocate memory\n");
1659                 return 0;
1660         }
1661
1662         while (index < count) {
1663                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1664                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1665                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1666                 index++;
1667         }
1668
1669         return iodelay;
1670 }
1671
1672 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1673                                                    const char *name, int *len)
1674 {
1675         const void *fdt = gd->fdt_blob;
1676         int offset;
1677         const fdt32_t *pinctrl;
1678
1679         offset = fdt_node_offset_by_phandle(fdt, phandle);
1680         if (offset < 0) {
1681                 debug("failed to get pinctrl node %s.\n",
1682                       fdt_strerror(offset));
1683                 return 0;
1684         }
1685
1686         pinctrl = fdt_getprop(fdt, offset, name, len);
1687         if (!pinctrl) {
1688                 debug("failed to get property %s\n", name);
1689                 return 0;
1690         }
1691
1692         return pinctrl;
1693 }
1694
1695 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1696                                                 char *prop_name)
1697 {
1698         const void *fdt = gd->fdt_blob;
1699         const __be32 *phandle;
1700         int node = dev_of_offset(mmc->dev);
1701
1702         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1703         if (!phandle) {
1704                 debug("failed to get property %s\n", prop_name);
1705                 return 0;
1706         }
1707
1708         return fdt32_to_cpu(*phandle);
1709 }
1710
1711 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1712                                                char *prop_name)
1713 {
1714         const void *fdt = gd->fdt_blob;
1715         const __be32 *phandle;
1716         int len;
1717         int count;
1718         int node = dev_of_offset(mmc->dev);
1719
1720         phandle = fdt_getprop(fdt, node, prop_name, &len);
1721         if (!phandle) {
1722                 debug("failed to get property %s\n", prop_name);
1723                 return 0;
1724         }
1725
1726         /* No manual mode iodelay values if count < 2 */
1727         count = len / sizeof(*phandle);
1728         if (count < 2)
1729                 return 0;
1730
1731         return fdt32_to_cpu(*(phandle + 1));
1732 }
1733
1734 static struct pad_conf_entry *
1735 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1736 {
1737         int len;
1738         int count;
1739         struct pad_conf_entry *padconf;
1740         u32 phandle;
1741         const fdt32_t *pinctrl;
1742
1743         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1744         if (!phandle)
1745                 return ERR_PTR(-EINVAL);
1746
1747         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1748                                                &len);
1749         if (!pinctrl)
1750                 return ERR_PTR(-EINVAL);
1751
1752         count = (len / sizeof(*pinctrl)) / 2;
1753         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1754         if (!padconf)
1755                 return ERR_PTR(-EINVAL);
1756
1757         *npads = count;
1758
1759         return padconf;
1760 }
1761
1762 static struct iodelay_cfg_entry *
1763 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1764 {
1765         int len;
1766         int count;
1767         struct iodelay_cfg_entry *iodelay;
1768         u32 phandle;
1769         const fdt32_t *pinctrl;
1770
1771         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1772         /* Not all modes have manual mode iodelay values. So its not fatal */
1773         if (!phandle)
1774                 return 0;
1775
1776         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1777                                                &len);
1778         if (!pinctrl)
1779                 return ERR_PTR(-EINVAL);
1780
1781         count = (len / sizeof(*pinctrl)) / 3;
1782         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1783         if (!iodelay)
1784                 return ERR_PTR(-EINVAL);
1785
1786         *niodelay = count;
1787
1788         return iodelay;
1789 }
1790
1791 static struct omap_hsmmc_pinctrl_state *
1792 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1793 {
1794         int index;
1795         int npads = 0;
1796         int niodelays = 0;
1797         const void *fdt = gd->fdt_blob;
1798         int node = dev_of_offset(mmc->dev);
1799         char prop_name[11];
1800         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1801
1802         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1803                          malloc(sizeof(*pinctrl_state));
1804         if (!pinctrl_state) {
1805                 debug("failed to allocate memory\n");
1806                 return 0;
1807         }
1808
1809         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1810         if (index < 0) {
1811                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1812                 goto err_pinctrl_state;
1813         }
1814
1815         sprintf(prop_name, "pinctrl-%d", index);
1816
1817         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1818                                                          &npads);
1819         if (IS_ERR(pinctrl_state->padconf))
1820                 goto err_pinctrl_state;
1821         pinctrl_state->npads = npads;
1822
1823         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1824                                                         &niodelays);
1825         if (IS_ERR(pinctrl_state->iodelay))
1826                 goto err_padconf;
1827         pinctrl_state->niodelays = niodelays;
1828
1829         return pinctrl_state;
1830
1831 err_padconf:
1832         kfree(pinctrl_state->padconf);
1833
1834 err_pinctrl_state:
1835         kfree(pinctrl_state);
1836         return 0;
1837 }
1838
1839 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1840         do {                                                            \
1841                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1842                 char str[20];                                           \
1843                 if (!(cfg->host_caps & capmask))                        \
1844                         break;                                          \
1845                                                                         \
1846                 if (priv->hw_rev) {                                     \
1847                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1848                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1849                 }                                                       \
1850                                                                         \
1851                 if (!s)                                                 \
1852                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1853                                                                         \
1854                 if (!s && !optional) {                                  \
1855                         debug("%s: no pinctrl for %s\n",                \
1856                               mmc->dev->name, #mode);                   \
1857                         cfg->host_caps &= ~(capmask);                   \
1858                 } else {                                                \
1859                         priv->mode##_pinctrl_state = s;                 \
1860                 }                                                       \
1861         } while (0)
1862
1863 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1864 {
1865         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1866         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1867         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1868
1869         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1870                 return 0;
1871
1872         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1873         if (!default_pinctrl) {
1874                 printf("no pinctrl state for default mode\n");
1875                 return -EINVAL;
1876         }
1877
1878         priv->default_pinctrl_state = default_pinctrl;
1879
1880         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1881         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1882         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1883         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1884         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1885
1886         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1887         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1888         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1889
1890         return 0;
1891 }
1892 #endif
1893
1894 #if CONFIG_IS_ENABLED(OF_REAL)
1895 #ifdef CONFIG_OMAP54XX
1896 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1897 {
1898         return NULL;
1899 }
1900 #endif
1901
1902 static int omap_hsmmc_of_to_plat(struct udevice *dev)
1903 {
1904         struct omap_hsmmc_plat *plat = dev_get_plat(dev);
1905         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1906
1907         struct mmc_config *cfg = &plat->cfg;
1908 #ifdef CONFIG_OMAP54XX
1909         const struct mmc_platform_fixups *fixups;
1910 #endif
1911         const void *fdt = gd->fdt_blob;
1912         int node = dev_of_offset(dev);
1913         int ret;
1914
1915         plat->base_addr = map_physmem(dev_read_addr(dev),
1916                                       sizeof(struct hsmmc *),
1917                                       MAP_NOCACHE);
1918
1919         ret = mmc_of_parse(dev, cfg);
1920         if (ret < 0)
1921                 return ret;
1922
1923         if (!cfg->f_max)
1924                 cfg->f_max = 52000000;
1925         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1926         cfg->f_min = 400000;
1927         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1928         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1929         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1930                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1931         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1932                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1933         if (of_data)
1934                 plat->controller_flags |= of_data->controller_flags;
1935
1936 #ifdef CONFIG_OMAP54XX
1937         fixups = platform_fixups_mmc(dev_read_addr(dev));
1938         if (fixups) {
1939                 plat->hw_rev = fixups->hw_rev;
1940                 cfg->host_caps &= ~fixups->unsupported_caps;
1941                 cfg->f_max = fixups->max_freq;
1942         }
1943 #endif
1944
1945         return 0;
1946 }
1947 #endif
1948
1949 #ifdef CONFIG_BLK
1950
1951 static int omap_hsmmc_bind(struct udevice *dev)
1952 {
1953         struct omap_hsmmc_plat *plat = dev_get_plat(dev);
1954         plat->mmc = calloc(1, sizeof(struct mmc));
1955         return mmc_bind(dev, plat->mmc, &plat->cfg);
1956 }
1957 #endif
1958 static int omap_hsmmc_probe(struct udevice *dev)
1959 {
1960         struct omap_hsmmc_plat *plat = dev_get_plat(dev);
1961         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1962         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1963         struct mmc_config *cfg = &plat->cfg;
1964         struct mmc *mmc;
1965 #ifdef CONFIG_IODELAY_RECALIBRATION
1966         int ret;
1967 #endif
1968
1969         cfg->name = "OMAP SD/MMC";
1970         priv->base_addr = plat->base_addr;
1971         priv->controller_flags = plat->controller_flags;
1972         priv->hw_rev = plat->hw_rev;
1973
1974 #ifdef CONFIG_BLK
1975         mmc = plat->mmc;
1976 #else
1977         mmc = mmc_create(cfg, priv);
1978         if (mmc == NULL)
1979                 return -1;
1980 #endif
1981 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1982         device_get_supply_regulator(dev, "pbias-supply",
1983                                     &priv->pbias_supply);
1984 #endif
1985 #if defined(OMAP_HSMMC_USE_GPIO)
1986 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1987         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1988         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1989 #endif
1990 #endif
1991
1992         mmc->dev = dev;
1993         upriv->mmc = mmc;
1994
1995 #ifdef CONFIG_IODELAY_RECALIBRATION
1996         ret = omap_hsmmc_get_pinctrl_state(mmc);
1997         /*
1998          * disable high speed modes for the platforms that require IO delay
1999          * and for which we don't have this information
2000          */
2001         if ((ret < 0) &&
2002             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
2003                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2004                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2005                                     UHS_CAPS);
2006         }
2007 #endif
2008
2009         return omap_hsmmc_init_setup(mmc);
2010 }
2011
2012 #if CONFIG_IS_ENABLED(OF_REAL)
2013
2014 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2015         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2016 };
2017
2018 static const struct udevice_id omap_hsmmc_ids[] = {
2019         { .compatible = "ti,omap3-hsmmc" },
2020         { .compatible = "ti,omap4-hsmmc" },
2021         { .compatible = "ti,am33xx-hsmmc" },
2022         { .compatible = "ti,am335-sdhci" },
2023         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2024         { }
2025 };
2026 #endif
2027
2028 U_BOOT_DRIVER(omap_hsmmc) = {
2029         .name   = "omap_hsmmc",
2030         .id     = UCLASS_MMC,
2031 #if CONFIG_IS_ENABLED(OF_REAL)
2032         .of_match = omap_hsmmc_ids,
2033         .of_to_plat = omap_hsmmc_of_to_plat,
2034         .plat_auto      = sizeof(struct omap_hsmmc_plat),
2035 #endif
2036 #ifdef CONFIG_BLK
2037         .bind = omap_hsmmc_bind,
2038 #endif
2039         .ops = &omap_hsmmc_ops,
2040         .probe  = omap_hsmmc_probe,
2041         .priv_auto      = sizeof(struct omap_hsmmc_data),
2042 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2043         .flags  = DM_FLAG_PRE_RELOC,
2044 #endif
2045 };
2046 #endif