drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <mmc.h>
  29 #include <part.h>
  30 #include <i2c.h>
  31 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  32 #include <palmas.h>
  33 #endif
  34 #include <asm/io.h>
  35 #include <asm/arch/mmc_host_def.h>
  36 #if !defined(CONFIG_SOC_KEYSTONE)
  37 #include <asm/gpio.h>
  38 #include <asm/arch/sys_proto.h>
  39 #endif
  40 #ifdef CONFIG_MMC_OMAP36XX_PINS
  41 #include <asm/arch/mux.h>
  42 #endif
  43 #include <dm.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  48 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  49         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  50 #define OMAP_HSMMC_USE_GPIO
  51 #else
  52 #undef OMAP_HSMMC_USE_GPIO
  53 #endif
  54
  55 /* common definitions for all OMAPs */
  56 #define SYSCTL_SRC      (1 << 25)
  57 #define SYSCTL_SRD      (1 << 26)
  58
  59 struct omap_hsmmc_data {
  60         struct hsmmc *base_addr;
  61 #if !CONFIG_IS_ENABLED(DM_MMC)
  62         struct mmc_config cfg;
  63 #endif
  64 #ifdef OMAP_HSMMC_USE_GPIO
  65 #if CONFIG_IS_ENABLED(DM_MMC)
  66         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  67         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  68         bool cd_inverted;
  69 #else
  70         int cd_gpio;
  71         int wp_gpio;
  72 #endif
  73 #endif
  74 };
  75
  76 /* If we fail after 1 second wait, something is really bad */
  77 #define MAX_RETRY_MS    1000
  78
  79 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  80 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  81                         unsigned int siz);
  82
  83 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
  84 {
  85 #if CONFIG_IS_ENABLED(DM_MMC)
  86         return dev_get_priv(mmc->dev);
  87 #else
  88         return (struct omap_hsmmc_data *)mmc->priv;
  89 #endif
  90 }
  91 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
  92 {
  93 #if CONFIG_IS_ENABLED(DM_MMC)
  94         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
  95         return &plat->cfg;
  96 #else
  97         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
  98 #endif
  99 }
 100
 101 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 102 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 103 {
 104         int ret;
 105
 106 #ifndef CONFIG_DM_GPIO
 107         if (!gpio_is_valid(gpio))
 108                 return -1;
 109 #endif
 110         ret = gpio_request(gpio, label);
 111         if (ret)
 112                 return ret;
 113
 114         ret = gpio_direction_input(gpio);
 115         if (ret)
 116                 return ret;
 117
 118         return gpio;
 119 }
 120 #endif
 121
 122 static unsigned char mmc_board_init(struct mmc *mmc)
 123 {
 124 #if defined(CONFIG_OMAP34XX)
 125         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 126         t2_t *t2_base = (t2_t *)T2_BASE;
 127         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 128         u32 pbias_lite;
 129 #ifdef CONFIG_MMC_OMAP36XX_PINS
 130         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 131 #endif
 132
 133         pbias_lite = readl(&t2_base->pbias_lite);
 134         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 135 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 136         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 137         pbias_lite &= ~PBIASLITEVMODE0;
 138 #endif
 139 #ifdef CONFIG_MMC_OMAP36XX_PINS
 140         if (get_cpu_family() == CPU_OMAP36XX) {
 141                 /* Disable extended drain IO before changing PBIAS */
 142                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 143                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 144         }
 145 #endif
 146         writel(pbias_lite, &t2_base->pbias_lite);
 147
 148         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 149                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 150                 &t2_base->pbias_lite);
 151
 152 #ifdef CONFIG_MMC_OMAP36XX_PINS
 153         if (get_cpu_family() == CPU_OMAP36XX)
 154                 /* Enable extended drain IO after changing PBIAS */
 155                 writel(wkup_ctrl |
 156                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 157                                 OMAP34XX_CTRL_WKUP_CTRL);
 158 #endif
 159         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 160                 &t2_base->devconf0);
 161
 162         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 163                 &t2_base->devconf1);
 164
 165         /* Change from default of 52MHz to 26MHz if necessary */
 166         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 167                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 168                         &t2_base->ctl_prog_io1);
 169
 170         writel(readl(&prcm_base->fclken1_core) |
 171                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 172                 &prcm_base->fclken1_core);
 173
 174         writel(readl(&prcm_base->iclken1_core) |
 175                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 176                 &prcm_base->iclken1_core);
 177 #endif
 178
 179 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
 180         /* PBIAS config needed for MMC1 only */
 181         if (mmc_get_blk_desc(mmc)->devnum == 0)
 182                 vmmc_pbias_config(LDO_VOLT_3V0);
 183 #endif
 184
 185         return 0;
 186 }
 187
 188 void mmc_init_stream(struct hsmmc *mmc_base)
 189 {
 190         ulong start;
 191
 192         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 193
 194         writel(MMC_CMD0, &mmc_base->cmd);
 195         start = get_timer(0);
 196         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 197                 if (get_timer(0) - start > MAX_RETRY_MS) {
 198                         printf("%s: timedout waiting for cc!\n", __func__);
 199                         return;
 200                 }
 201         }
 202         writel(CC_MASK, &mmc_base->stat)
 203                 ;
 204         writel(MMC_CMD0, &mmc_base->cmd)
 205                 ;
 206         start = get_timer(0);
 207         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 208                 if (get_timer(0) - start > MAX_RETRY_MS) {
 209                         printf("%s: timedout waiting for cc2!\n", __func__);
 210                         return;
 211                 }
 212         }
 213         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 214 }
 215
 216 static int omap_hsmmc_init_setup(struct mmc *mmc)
 217 {
 218         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 219         struct hsmmc *mmc_base;
 220         unsigned int reg_val;
 221         unsigned int dsor;
 222         ulong start;
 223
 224         mmc_base = priv->base_addr;
 225         mmc_board_init(mmc);
 226
 227         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 228                 &mmc_base->sysconfig);
 229         start = get_timer(0);
 230         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 231                 if (get_timer(0) - start > MAX_RETRY_MS) {
 232                         printf("%s: timedout waiting for cc2!\n", __func__);
 233                         return -ETIMEDOUT;
 234                 }
 235         }
 236         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 237         start = get_timer(0);
 238         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 239                 if (get_timer(0) - start > MAX_RETRY_MS) {
 240                         printf("%s: timedout waiting for softresetall!\n",
 241                                 __func__);
 242                         return -ETIMEDOUT;
 243                 }
 244         }
 245         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 246         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 247                 &mmc_base->capa);
 248
 249         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 250
 251         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 252                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 253                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 254
 255         dsor = 240;
 256         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 257                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 258         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 259                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 260         start = get_timer(0);
 261         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 262                 if (get_timer(0) - start > MAX_RETRY_MS) {
 263                         printf("%s: timedout waiting for ics!\n", __func__);
 264                         return -ETIMEDOUT;
 265                 }
 266         }
 267         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 268
 269         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 270
 271         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 272                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 273                 &mmc_base->ie);
 274
 275         mmc_init_stream(mmc_base);
 276
 277         return 0;
 278 }
 279
 280 /*
 281  * MMC controller internal finite state machine reset
 282  *
 283  * Used to reset command or data internal state machines, using respectively
 284  * SRC or SRD bit of SYSCTL register
 285  */
 286 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 287 {
 288         ulong start;
 289
 290         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 291
 292         /*
 293          * CMD(DAT) lines reset procedures are slightly different
 294          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 295          * According to OMAP3 TRM:
 296          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 297          * returns to 0x0.
 298          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 299          * procedure steps must be as follows:
 300          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 301          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 302          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 303          * 3. Wait until the SRC (SRD) bit returns to 0x0
 304          *    (reset procedure is completed).
 305          */
 306 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 307         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 308         if (!(readl(&mmc_base->sysctl) & bit)) {
 309                 start = get_timer(0);
 310                 while (!(readl(&mmc_base->sysctl) & bit)) {
 311                         if (get_timer(0) - start > MAX_RETRY_MS)
 312                                 return;
 313                 }
 314         }
 315 #endif
 316         start = get_timer(0);
 317         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 318                 if (get_timer(0) - start > MAX_RETRY_MS) {
 319                         printf("%s: timedout waiting for sysctl %x to clear\n",
 320                                 __func__, bit);
 321                         return;
 322                 }
 323         }
 324 }
 325 #if !CONFIG_IS_ENABLED(DM_MMC)
 326 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 327                         struct mmc_data *data)
 328 {
 329         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 330 #else
 331 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 332                         struct mmc_data *data)
 333 {
 334         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 335 #endif
 336         struct hsmmc *mmc_base;
 337         unsigned int flags, mmc_stat;
 338         ulong start;
 339
 340         mmc_base = priv->base_addr;
 341         start = get_timer(0);
 342         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 343                 if (get_timer(0) - start > MAX_RETRY_MS) {
 344                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 345                                         __func__);
 346                         return -ETIMEDOUT;
 347                 }
 348         }
 349         writel(0xFFFFFFFF, &mmc_base->stat);
 350         start = get_timer(0);
 351         while (readl(&mmc_base->stat)) {
 352                 if (get_timer(0) - start > MAX_RETRY_MS) {
 353                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 354                                 __func__, readl(&mmc_base->stat));
 355                         return -ETIMEDOUT;
 356                 }
 357         }
 358         /*
 359          * CMDREG
 360          * CMDIDX[13:8] : Command index
 361          * DATAPRNT[5]  : Data Present Select
 362          * ENCMDIDX[4]  : Command Index Check Enable
 363          * ENCMDCRC[3]  : Command CRC Check Enable
 364          * RSPTYP[1:0]
 365          *      00 = No Response
 366          *      01 = Length 136
 367          *      10 = Length 48
 368          *      11 = Length 48 Check busy after response
 369          */
 370         /* Delay added before checking the status of frq change
 371          * retry not supported by mmc.c(core file)
 372          */
 373         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 374                 udelay(50000); /* wait 50 ms */
 375
 376         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 377                 flags = 0;
 378         else if (cmd->resp_type & MMC_RSP_136)
 379                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 380         else if (cmd->resp_type & MMC_RSP_BUSY)
 381                 flags = RSP_TYPE_LGHT48B;
 382         else
 383                 flags = RSP_TYPE_LGHT48;
 384
 385         /* enable default flags */
 386         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 387                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 388
 389         if (cmd->resp_type & MMC_RSP_CRC)
 390                 flags |= CCCE_CHECK;
 391         if (cmd->resp_type & MMC_RSP_OPCODE)
 392                 flags |= CICE_CHECK;
 393
 394         if (data) {
 395                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 396                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 397                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 398                         data->blocksize = 512;
 399                         writel(data->blocksize | (data->blocks << 16),
 400                                                         &mmc_base->blk);
 401                 } else
 402                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 403
 404                 if (data->flags & MMC_DATA_READ)
 405                         flags |= (DP_DATA | DDIR_READ);
 406                 else
 407                         flags |= (DP_DATA | DDIR_WRITE);
 408         }
 409
 410         writel(cmd->cmdarg, &mmc_base->arg);
 411         udelay(20);             /* To fix "No status update" error on eMMC */
 412         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 413
 414         start = get_timer(0);
 415         do {
 416                 mmc_stat = readl(&mmc_base->stat);
 417                 if (get_timer(0) - start > MAX_RETRY_MS) {
 418                         printf("%s : timeout: No status update\n", __func__);
 419                         return -ETIMEDOUT;
 420                 }
 421         } while (!mmc_stat);
 422
 423         if ((mmc_stat & IE_CTO) != 0) {
 424                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 425                 return -ETIMEDOUT;
 426         } else if ((mmc_stat & ERRI_MASK) != 0)
 427                 return -1;
 428
 429         if (mmc_stat & CC_MASK) {
 430                 writel(CC_MASK, &mmc_base->stat);
 431                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 432                         if (cmd->resp_type & MMC_RSP_136) {
 433                                 /* response type 2 */
 434                                 cmd->response[3] = readl(&mmc_base->rsp10);
 435                                 cmd->response[2] = readl(&mmc_base->rsp32);
 436                                 cmd->response[1] = readl(&mmc_base->rsp54);
 437                                 cmd->response[0] = readl(&mmc_base->rsp76);
 438                         } else
 439                                 /* response types 1, 1b, 3, 4, 5, 6 */
 440                                 cmd->response[0] = readl(&mmc_base->rsp10);
 441                 }
 442         }
 443
 444         if (data && (data->flags & MMC_DATA_READ)) {
 445                 mmc_read_data(mmc_base, data->dest,
 446                                 data->blocksize * data->blocks);
 447         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 448                 mmc_write_data(mmc_base, data->src,
 449                                 data->blocksize * data->blocks);
 450         }
 451         return 0;
 452 }
 453
 454 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 455 {
 456         unsigned int *output_buf = (unsigned int *)buf;
 457         unsigned int mmc_stat;
 458         unsigned int count;
 459
 460         /*
 461          * Start Polled Read
 462          */
 463         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 464         count /= 4;
 465
 466         while (size) {
 467                 ulong start = get_timer(0);
 468                 do {
 469                         mmc_stat = readl(&mmc_base->stat);
 470                         if (get_timer(0) - start > MAX_RETRY_MS) {
 471                                 printf("%s: timedout waiting for status!\n",
 472                                                 __func__);
 473                                 return -ETIMEDOUT;
 474                         }
 475                 } while (mmc_stat == 0);
 476
 477                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 478                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 479
 480                 if ((mmc_stat & ERRI_MASK) != 0)
 481                         return 1;
 482
 483                 if (mmc_stat & BRR_MASK) {
 484                         unsigned int k;
 485
 486                         writel(readl(&mmc_base->stat) | BRR_MASK,
 487                                 &mmc_base->stat);
 488                         for (k = 0; k < count; k++) {
 489                                 *output_buf = readl(&mmc_base->data);
 490                                 output_buf++;
 491                         }
 492                         size -= (count*4);
 493                 }
 494
 495                 if (mmc_stat & BWR_MASK)
 496                         writel(readl(&mmc_base->stat) | BWR_MASK,
 497                                 &mmc_base->stat);
 498
 499                 if (mmc_stat & TC_MASK) {
 500                         writel(readl(&mmc_base->stat) | TC_MASK,
 501                                 &mmc_base->stat);
 502                         break;
 503                 }
 504         }
 505         return 0;
 506 }
 507
 508 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 509                                 unsigned int size)
 510 {
 511         unsigned int *input_buf = (unsigned int *)buf;
 512         unsigned int mmc_stat;
 513         unsigned int count;
 514
 515         /*
 516          * Start Polled Write
 517          */
 518         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 519         count /= 4;
 520
 521         while (size) {
 522                 ulong start = get_timer(0);
 523                 do {
 524                         mmc_stat = readl(&mmc_base->stat);
 525                         if (get_timer(0) - start > MAX_RETRY_MS) {
 526                                 printf("%s: timedout waiting for status!\n",
 527                                                 __func__);
 528                                 return -ETIMEDOUT;
 529                         }
 530                 } while (mmc_stat == 0);
 531
 532                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 533                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 534
 535                 if ((mmc_stat & ERRI_MASK) != 0)
 536                         return 1;
 537
 538                 if (mmc_stat & BWR_MASK) {
 539                         unsigned int k;
 540
 541                         writel(readl(&mmc_base->stat) | BWR_MASK,
 542                                         &mmc_base->stat);
 543                         for (k = 0; k < count; k++) {
 544                                 writel(*input_buf, &mmc_base->data);
 545                                 input_buf++;
 546                         }
 547                         size -= (count*4);
 548                 }
 549
 550                 if (mmc_stat & BRR_MASK)
 551                         writel(readl(&mmc_base->stat) | BRR_MASK,
 552                                 &mmc_base->stat);
 553
 554                 if (mmc_stat & TC_MASK) {
 555                         writel(readl(&mmc_base->stat) | TC_MASK,
 556                                 &mmc_base->stat);
 557                         break;
 558                 }
 559         }
 560         return 0;
 561 }
 562
 563 #if !CONFIG_IS_ENABLED(DM_MMC)
 564 static int omap_hsmmc_set_ios(struct mmc *mmc)
 565 {
 566         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 567 #else
 568 static int omap_hsmmc_set_ios(struct udevice *dev)
 569 {
 570         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 571         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 572         struct mmc *mmc = upriv->mmc;
 573 #endif
 574         struct hsmmc *mmc_base;
 575         unsigned int dsor = 0;
 576         ulong start;
 577
 578         mmc_base = priv->base_addr;
 579         /* configue bus width */
 580         switch (mmc->bus_width) {
 581         case 8:
 582                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 583                         &mmc_base->con);
 584                 break;
 585
 586         case 4:
 587                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 588                         &mmc_base->con);
 589                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 590                         &mmc_base->hctl);
 591                 break;
 592
 593         case 1:
 594         default:
 595                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 596                         &mmc_base->con);
 597                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 598                         &mmc_base->hctl);
 599                 break;
 600         }
 601
 602         /* configure clock with 96Mhz system clock.
 603          */
 604         if (mmc->clock != 0) {
 605                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 606                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 607                         dsor++;
 608         }
 609
 610         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 611                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 612
 613         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 614                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 615
 616         start = get_timer(0);
 617         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 618                 if (get_timer(0) - start > MAX_RETRY_MS) {
 619                         printf("%s: timedout waiting for ics!\n", __func__);
 620                         return -ETIMEDOUT;
 621                 }
 622         }
 623         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 624
 625         return 0;
 626 }
 627
 628 #ifdef OMAP_HSMMC_USE_GPIO
 629 #if CONFIG_IS_ENABLED(DM_MMC)
 630 static int omap_hsmmc_getcd(struct udevice *dev)
 631 {
 632         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 633         int value;
 634
 635         value = dm_gpio_get_value(&priv->cd_gpio);
 636         /* if no CD return as 1 */
 637         if (value < 0)
 638                 return 1;
 639
 640         if (priv->cd_inverted)
 641                 return !value;
 642         return value;
 643 }
 644
 645 static int omap_hsmmc_getwp(struct udevice *dev)
 646 {
 647         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 648         int value;
 649
 650         value = dm_gpio_get_value(&priv->wp_gpio);
 651         /* if no WP return as 0 */
 652         if (value < 0)
 653                 return 0;
 654         return value;
 655 }
 656 #else
 657 static int omap_hsmmc_getcd(struct mmc *mmc)
 658 {
 659         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 660         int cd_gpio;
 661
 662         /* if no CD return as 1 */
 663         cd_gpio = priv->cd_gpio;
 664         if (cd_gpio < 0)
 665                 return 1;
 666
 667         /* NOTE: assumes card detect signal is active-low */
 668         return !gpio_get_value(cd_gpio);
 669 }
 670
 671 static int omap_hsmmc_getwp(struct mmc *mmc)
 672 {
 673         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 674         int wp_gpio;
 675
 676         /* if no WP return as 0 */
 677         wp_gpio = priv->wp_gpio;
 678         if (wp_gpio < 0)
 679                 return 0;
 680
 681         /* NOTE: assumes write protect signal is active-high */
 682         return gpio_get_value(wp_gpio);
 683 }
 684 #endif
 685 #endif
 686
 687 #if CONFIG_IS_ENABLED(DM_MMC)
 688 static const struct dm_mmc_ops omap_hsmmc_ops = {
 689         .send_cmd       = omap_hsmmc_send_cmd,
 690         .set_ios        = omap_hsmmc_set_ios,
 691 #ifdef OMAP_HSMMC_USE_GPIO
 692         .get_cd         = omap_hsmmc_getcd,
 693         .get_wp         = omap_hsmmc_getwp,
 694 #endif
 695 };
 696 #else
 697 static const struct mmc_ops omap_hsmmc_ops = {
 698         .send_cmd       = omap_hsmmc_send_cmd,
 699         .set_ios        = omap_hsmmc_set_ios,
 700         .init           = omap_hsmmc_init_setup,
 701 #ifdef OMAP_HSMMC_USE_GPIO
 702         .getcd          = omap_hsmmc_getcd,
 703         .getwp          = omap_hsmmc_getwp,
 704 #endif
 705 };
 706 #endif
 707
 708 #if !CONFIG_IS_ENABLED(DM_MMC)
 709 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 710                 int wp_gpio)
 711 {
 712         struct mmc *mmc;
 713         struct omap_hsmmc_data *priv;
 714         struct mmc_config *cfg;
 715         uint host_caps_val;
 716
 717         priv = malloc(sizeof(*priv));
 718         if (priv == NULL)
 719                 return -1;
 720
 721         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 722
 723         switch (dev_index) {
 724         case 0:
 725                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 726                 break;
 727 #ifdef OMAP_HSMMC2_BASE
 728         case 1:
 729                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 730 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 731         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
 732         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
 733                 defined(CONFIG_HSMMC2_8BIT)
 734                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
 735                 host_caps_val |= MMC_MODE_8BIT;
 736 #endif
 737                 break;
 738 #endif
 739 #ifdef OMAP_HSMMC3_BASE
 740         case 2:
 741                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
 742 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
 743                 /* Enable 8-bit interface for eMMC on DRA7XX */
 744                 host_caps_val |= MMC_MODE_8BIT;
 745 #endif
 746                 break;
 747 #endif
 748         default:
 749                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 750                 return 1;
 751         }
 752 #ifdef OMAP_HSMMC_USE_GPIO
 753         /* on error gpio values are set to -1, which is what we want */
 754         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
 755         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 756 #endif
 757
 758         cfg = &priv->cfg;
 759
 760         cfg->name = "OMAP SD/MMC";
 761         cfg->ops = &omap_hsmmc_ops;
 762
 763         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 764         cfg->host_caps = host_caps_val & ~host_caps_mask;
 765
 766         cfg->f_min = 400000;
 767
 768         if (f_max != 0)
 769                 cfg->f_max = f_max;
 770         else {
 771                 if (cfg->host_caps & MMC_MODE_HS) {
 772                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
 773                                 cfg->f_max = 52000000;
 774                         else
 775                                 cfg->f_max = 26000000;
 776                 } else
 777                         cfg->f_max = 20000000;
 778         }
 779
 780         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 781
 782 #if defined(CONFIG_OMAP34XX)
 783         /*
 784          * Silicon revs 2.1 and older do not support multiblock transfers.
 785          */
 786         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 787                 cfg->b_max = 1;
 788 #endif
 789         mmc = mmc_create(cfg, priv);
 790         if (mmc == NULL)
 791                 return -1;
 792
 793         return 0;
 794 }
 795 #else
 796 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 797 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
 798 {
 799         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
 800         struct mmc_config *cfg = &plat->cfg;
 801         const void *fdt = gd->fdt_blob;
 802         int node = dev_of_offset(dev);
 803         int val;
 804
 805         plat->base_addr = map_physmem(devfdt_get_addr(dev),
 806                                       sizeof(struct hsmmc *),
 807                                       MAP_NOCACHE);
 808
 809         cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 810         val = fdtdec_get_int(fdt, node, "bus-width", -1);
 811         if (val < 0) {
 812                 printf("error: bus-width property missing\n");
 813                 return -ENOENT;
 814         }
 815
 816         switch (val) {
 817         case 0x8:
 818                 cfg->host_caps |= MMC_MODE_8BIT;
 819         case 0x4:
 820                 cfg->host_caps |= MMC_MODE_4BIT;
 821                 break;
 822         default:
 823                 printf("error: invalid bus-width property\n");
 824                 return -ENOENT;
 825         }
 826
 827         cfg->f_min = 400000;
 828         cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
 829         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 830         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 831
 832 #ifdef OMAP_HSMMC_USE_GPIO
 833         plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
 834 #endif
 835
 836         return 0;
 837 }
 838 #endif
 839
 840 #ifdef CONFIG_BLK
 841
 842 static int omap_hsmmc_bind(struct udevice *dev)
 843 {
 844         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
 845
 846         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 847 }
 848 #endif
 849 static int omap_hsmmc_probe(struct udevice *dev)
 850 {
 851         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
 852         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 853         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 854         struct mmc_config *cfg = &plat->cfg;
 855         struct mmc *mmc;
 856
 857         cfg->name = "OMAP SD/MMC";
 858         priv->base_addr = plat->base_addr;
 859 #ifdef OMAP_HSMMC_USE_GPIO
 860         priv->cd_inverted = plat->cd_inverted;
 861 #endif
 862
 863 #ifdef CONFIG_BLK
 864         mmc = &plat->mmc;
 865 #else
 866         mmc = mmc_create(cfg, priv);
 867         if (mmc == NULL)
 868                 return -1;
 869 #endif
 870
 871 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
 872         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
 873         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
 874 #endif
 875
 876         mmc->dev = dev;
 877         upriv->mmc = mmc;
 878
 879         return omap_hsmmc_init_setup(mmc);
 880 }
 881
 882 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 883 static const struct udevice_id omap_hsmmc_ids[] = {
 884         { .compatible = "ti,omap3-hsmmc" },
 885         { .compatible = "ti,omap4-hsmmc" },
 886         { .compatible = "ti,am33xx-hsmmc" },
 887         { }
 888 };
 889 #endif
 890
 891 U_BOOT_DRIVER(omap_hsmmc) = {
 892         .name   = "omap_hsmmc",
 893         .id     = UCLASS_MMC,
 894 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 895         .of_match = omap_hsmmc_ids,
 896         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
 897         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
 898 #endif
 899 #ifdef CONFIG_BLK
 900         .bind = omap_hsmmc_bind,
 901 #endif
 902         .ops = &omap_hsmmc_ops,
 903         .probe  = omap_hsmmc_probe,
 904         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
 905         .flags  = DM_FLAG_PRE_RELOC,
 906 };
 907 #endif